Microchip Technology Inc MCP4725A0T-E-CH, MCP4725 Datasheet

MCP4725

Resistive

Power-on

Reset

Charge

Pump

EEPROM

I2C Interface Logic

Input

Register

DAC Register

Op

Amp

Power-down

Control

V

DD

V

SS

SCL SDA

V

OUT

A0

String DAC

3

V

DD

SCL SDA

V

SS

A0

SOT-23-6

V

OUT

2

1

4

5

6

12-Bit Digital-to-Analog Converter with EEPROM Memory

in SOT-23-6

Features

• 12-Bit Resolution

• On-Board Non-Volatile Memory (EEPROM)

• ±0.2 LSB DNL (typical)

• External A0 Address Pin

• Normal or Power-Down Mode

• Fast Settling Time of 6 µs (typical)

• External Voltage Reference (V

• Rail-to-Rail Output

• Low Power Consumption

• Single-Supply Operation: 2.7V to 5.5V

2CTM

•I

• Small 6-lead SOT-23 Package

• Extended Temperature Range: -40°C to +125°C

Interface:

- Eight Available Addresses

- Standard (100 kbps), Fast (400 kbps), and High-Speed (3.4 Mbps) Modes

DD

)

Applications

• Set Point or Offset Trimming

• Sensor Calibration

• Closed-Loop Servo Control

• Low Power Portable Instrumentation

• PC Peripherals

• Data Acquisition Systems

Block Diagram

DESCRIPTION

The MCP4725 is a low-power, high accuracy, single channel, 12-bit buffered voltage output Digital-to-Analog Convertor (DAC) with non-volatile memory (EEPROM). Its on-board precision output amplifier allows it to achieve rail-to-rail analog output swing.

The DAC input and configuration data can be programmed to the non-volatile memory (EEPROM) by the user using I memory feature enables the DAC device to hold the DAC input code during power-off time, and the DAC output is available immediately after power-up. This feature is very useful when the DAC device is used as a supporting device for other devices in the network.

The device includes a Power-On-Reset (POR) circuit to ensure reliable power-up and an on-board charge pump for the EEPROM programming voltage. The DAC reference is driven from V power-down mode, the output amplifier can be configured to present a low, medium, or high resistance output load.

The MCP4725 has an external A0 address pin. This A0 pin can be tied to V board.

The MCP4725 has a two-wire I interface for standard (100 kHz), fast (400 kHz), or high speed (3.4 MHz) mode.

The MCP4725 is an ideal DAC device where design simplicity and small footprint is desired, and for applications requiring the DAC device settings to be saved during power-off time.

The device is available in a small 6-pin SOT-23 package.

Package Type

2

C interface command. The non-volatile

DD directly. In

DD or VSS of the user’s application

2

C™ compatible serial

MCP4725

1.0 ELECTRICAL CHARACTERISTICS

† Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functi onal operation of the device at these or any other conditions above those

Absolute Maximum Ratings†

VDD...................................................................................6.5V

All inputs and outputs w.r.t V

Current at Input Pins ....................................................±2 mA

Current at Supply Pins ...............................................±50 mA

Current at Output Pins ...............................................±25 mA

Storage Temperature ....................................-65°C to +150°C

Ambient Temp. with Power Applied ..............-55°C to +125°C

ESD protection on all pins ................ ≥ 6kV HBM, ≥ 400V MM

Maximum Junction Temperature (T

.................–0.3V to VDD+0.3V

SS

) ......................... +150°C

J

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V,

RL = 5 kΩ from V

Parameter Sym Min Typ Max Units Conditions

Power Requirements

Operating Voltage V Supply Current I

Power-Down Current I Power-On-Reset

Threshold

DC Accuracy

Resolution n 12 — — Bits Code Range = 000h to FFFh INL Error INL — ±2 ±14.5 LSB Note 1 DNL DNL -0.75 ±0.2 ±0.75 LSB Note 1 Offset Error V Offset Error Drift ΔV

Gain Error G

Gain Error Drift ΔGE/°C — -3 — ppm/°C

Output Amplifier

Phase Margin Capacitive Load Stability CL — — 1000 pF RL = 5 kΩ, Note 2 Slew Rate SR — 0.55 — V/µs Short Circuit Current I Output Voltage Settling

Time

Note 1: Test Code Range: 100 to 4000.

2: This parameter is ensure by design and not 100% tested. 3: Within 1/2 LSB of the final value when code changes from 1/4 to 3/4 (400h to C00h) of full-scale. 4: Logic state of external address pin (A0 pin).

to VSS, CL = 100 pF, TA = -40°C to +125°C. Typical values are at +25°C.

OUT

DD D

DDP

V

POR

OS

/°C — ±1 — ppm/°C -45°C to +25°C

OS

2.7 5.5 V — 210 400 µA Digital input grounded, out-

— 0.06 2.0 µA VDD = 5.5V —2 — V

0.02 0.75 % of FSR Code = 000h

— ±2 — ppm/°C +25°C to +85°C

-2 -0.1 2 % of FSR Code FFFh, not including

E

p

— 66 — Degree(°) CL = 400 pF, RL = ∞

M

—15 24 mA V

SC

TS —6 — µsNote 3

put unloaded, code = 000h

offset error

= 5V, V

DD

= Grounded

OUT

MCP4725

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V,

RL = 5 kΩ from V

Parameter Sym Min Typ Max Units Conditions

Power Up Time T

DC Output Impedance R

Dynamic Performance

Major Code Transition Glitch

Digital Feedthrough — <10 — nV-s Note 2

Digital Interface

Output Low Voltage V Input High Voltage

(SDA and SCL Pins) Input Low Voltage

(SDA and SCL Pins) Input High Voltage

(A0 Pin) Input Low Voltage

(A0 Pin) Input Leakage I

Pin Capacitance C

EEPROM

EEPROM Write Time T

Data Retention — 200 — Years At +25°C, (Note 2) Endurance 1 — — Million

Note 1: Test Code Range: 100 to 4000.

2: This parameter is ensure by design and not 100% tested. 3: Within 1/2 LSB of the final value when code changes from 1/4 to 3/4 (400h to C00h) of full-scale. 4: Logic state of external address pin (A0 pin).

to VSS, CL = 100 pF, TA = -40°C to +125°C. Typical values are at +25°C.

OUT

PU

—2.5 — µsV —5 — µsV

—1 — Ω Normal mode (V

OUT

—1 — kΩ Power-Down Mode 1

—100 — kΩ Power-Down Mode 2

—500 — kΩ Power-Down Mode 3

— 45 — nV-s 1 LSB change around major

— — 0.4 V IOL = 3 mA

OL

VIH 0.7V

V

— —0.3VDDV

IL

V

A0-Hi

V

— — 0.2V

A0-IL

— — ±1 µA SCL = SDA = A0 = V

LI

—— 3 pF Note 2

WRITE — 25 50 ms EEPROM Write time for 14

0.8V

DD

—— V

—— Note 4

DD

Cycles

= 5V

DD

= 3V

DD

Coming out of Power-down mode, started from falling edge of ACK pulse in I command.

OUT

(V

to VSS)

OUT

(V

to VSS)

OUT

(V

to VSS)

OUT

carry (800h to 7FFh) (Note 2)

Note 4

SCL = SDA = A0 = V

bits

At +25°C, (Note 2)

2

C

to VSS)

or

SS DD

MCP4725

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD= +2.7V to +5.5V, VSS=GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range T Operating Temperature Range T Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 6L-SOT-23 θ

A A A

JA

-40 — +125 °C

-65 — +150 °C

—190—°C/W

MCP4725

-0.04

0

0.04

0.08

0.12

0.16

0 1024 2048 3072 4096

Code

DNL (LSB)

-0.1

0

0.1

0.2

0.3

0 1024 2048 3072 4096

Code

DNL (LSB)

VDD = 5.5V

-0.1

0.0

0.1

0.2

0.3

0 1024 2048 3072 4096

Code

DNL (LSB)

-0.1

0.0

0.1

0.2

0.3

0.4

0 1024 2048 3072 4096

Code

DNL (LSB)

VDD = 2.7V

-4

-3

-2

-1

0

1

2

0 1024 2048 3072 4096

Code

INL(LSB)

2.7V

5.5V

-4

-3

-2

-1

0

1

2

0 1024 2048 3072 4096

Code

INL(LSB)

+25C

+125C

- 40C

+85C

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ to VSS, CL = 100 pF.

FIGURE 2-1: DNL vs. Code (VDD = 5.5V).

FIGURE 2-2: DNL vs. Code and

Temperature (TA = -40°C to +125°C).

FIGURE 2-4: DNL vs. Code and Temperature (T

= -40°C to +125°C).

A

FIGURE 2-5: INL vs. Code.

FIGURE 2-3: DNL vs. Code (V

= 2.7V).

DD

FIGURE 2-6: INL vs. Code and Temperature (V

= 5.5V).

DD

MCP4725

-5

-4

-3

-2

-1

0

1

2

0 1024 2048 3072 4096

Code

INL(LSB)

TA = -40 C TA = 25 C TA = 85 C TA = 125 C

+125 C

- 40 C

+85 C

+25 C

-1

0

1

2

3

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

Zero Scale Error (mV)

VDD = 5.5V

VDD = 2.7V

-60

-50

-40

-30

-20

-10

0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

Full-Scale Error (mV)

VDD = 2.7V

VDD = 5.5V

-5

-4

-3

-2

-1

0

1

2

3

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

Output Error (mV)

VDD = 2.7V

VDD = 5.5V

0

50

100

150

200

250

300

350

400

450

-40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature(°C)

I

DD

(uA)

VDD = 2.7V

VDD = 5V

Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ to VSS, CL = 100 pF.

FIGURE 2-7: INL vs. Code and Temperature (V

= 2.7V).

DD

FIGURE 2-8: Zero Scale Error vs. Temperature (Code = 000d).

FIGURE 2-10: Output Error vs. Temperature (Code = 4000d).

FIGURE 2-11: I

vs. Temperature.

DD

FIGURE 2-9: Full-Scale Error vs. Temperature (Code = 4095d).

MCP4725

0

10

20

30

40

50

60

70

80

90

100

180

184

188

192

196

200

204

208

212

216

220

224

228

232

236

Current (µA)

Occurance

VDD = 5V

VDD = 2.7V

0

10

20

30

40

50

60

70

80

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

Current (µA)

Occurance

0.00

0.50

1.00

1.50

2.00

2.50

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

Offset Error (mV)

2.7V

5.5V

0

1

2

3

4

5

6

012345

Load Resistance (kΩ)

V

OUT

(V)

VDD = 5V Code = FFFh

0

1

2

3

4

5

6

0481216

I

SOURCE/SINK

(mA)

V

OUT

(V)

Code = FFFh

Code = 000h

VDD = 5V

1.00

1.50

2.00

2.50

3.00

3.50

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

V

IH

Threshold (V)

VDD = 5.5V

VDD = 5.0V

VDD = 2.7V

Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ to VSS, CL = 100 pF.

FIGURE 2-12: IDD Histogram .

FIGURE 2-13: I

Histogram.

DD

FIGURE 2-15: V

vs. Resistive Load.

OUT

FIGURE 2-16: Source and Sink Current Capability.

FIGURE 2-14: Offset Error vs. Temperature and V

.

DD

FIGURE 2-17: V Temperature and V

High Threshold vs.

IN

.

DD

MCP4725

0.50

0.70

0.90

1.10

1.30

1.50

1.70

1.90

2.10

2.30

2.50

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (C)

V

IL

Threshold (V)

VDD = 5.5V

VDD = 5.0V

VDD = 2.7V

Full-Scale Code Change: 000h to FFFh

V

OUT

(2V/Div)

CLK

Time (2µs/Div)

Full-Scale Code Change: FFFh to 000h

V

OUT

(2V/Div)

CLK

Time (2µs/Div)

Half-Scale Code Change: 000h to 7FFh

V

OUT

(2V/Div)

CLK

Time (2µs/Div)

V

OUT

(2V/Div)

CLK

Time (2µs/Div)

Half-Scale Code Change: 7FFh to 000h

Code Change: 800h to 7FFh

V

OUT

(20 mV/Div)

Time (1µs/Div)

Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ to VSS, CL = 100 pF.

FIGURE 2-18: VIN Low Threshold vs. Temperature and V

DD

.

FIGURE 2-19: Full-Scale Settling Time.

FIGURE 2-21: Half-Scale Settling Time.

FIGURE 2-22: Half-Scale Settling Time.

FIGURE 2-20: Full-Scale Settling Time.

FIGURE 2-23: Code Change Glitch.

MCP4725

V

OUT

(2V/Div)

CLK

Time (2µs/Div)

Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ to VSS, CL = 100 pF.

FIGURE 2-24: Exiting Power Down Mode.

MCP4725

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin No. SOT-23

1V 2V 3V 4SDAI 5SCLI 6 A0 Device Address Selection pin. This pin can be tied to V

Name Function

OUT

SS

DD

Analog Output Voltage Ground Reference Supply Voltage

2

C Serial Data

2

C Serial Clock Input

driven by the digital logic levels. The logic state of this pin determines what the A0 bit of the I

2

C address bits should be.

or VDD, or can be actively

SS

3.1 Analog Output Voltage (V

V

is an analog output voltage from the DAC device.

OUT

)

DAC output amplifier drives this pin with a range of V to VDD.

3.2 Supply Voltage (VDD, VSS)

VDD is the power supply pin for the device. The voltage at the V DAC reference input. The power supply at the VDD pin should be clean as possible for a good DAC performance.

This pin requires an appropriate bypass capacitor of about 0.1 µF (ceramic) to ground. An addi tional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in application boards. The supply voltage (V maintained in the 2.7V to 5.5V range for specified operation.

V

SS

device. The user must connect the V plane through a low impedance connection. If an analog ground path is available in the application PCB (printed circuit board), it is highly recommended that the V within an analog ground plane of the circuit board.

pin is used as the supply input as well as the

DD

) must be

DD

is the ground pin and the current return path of the

pin to a ground

SS

pin be tied to the analog ground path or isolated

SS

3.4 Serial Clock Pin (SCL)

SCL is the serial clock pin of the I2C interface. The MCP4725 acts only as a slave and the SCL pin accepts only external serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the MCP4725 occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the V pin. Refer to Section 7.0 “I

2

C Serial Interface Com-

munication” for more details of I

line to the SCL

DD

2

C Serial Interface

communication.

3.5 Device Address Selection Pin (A0)

This pin is used to select the A0 address bit by the user. The user can tie this pin to VSS (logic ‘0’), or VDD (logic ‘1’), or can be actively driven by the digital logic levels, such as the I “Device Addressing” for more details of the address bits.

2

C Master Output. See Section 7.2

3.3 Serial Data Pin (SDA)

SDA is the serial data pin of the I2C interface. The SDA pin is used to write or read the DAC register and EEPROM data. The SDA pin is an open-drain N-chan nel driver. Therefore, it needs a pull-up resistor from the

line to the SDA pin. Except for start and stop

V

DD

conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 7.0 “I Serial Interface Communication” for more details of I2C Serial Interface communication.

2

C

MCP4725

LSB

Ideal

V

REF

2

n

------------ -

V

Full Scale–

V

Zero Scale–

–()

2

n

1–

---------------------------------------------------------------------

==

Where:

V

REF

= The reference voltage = VDD in the

MCP4725. This V

REF

is the ideal

full-scale voltage range

n = The number of digital input bits.

(n = 12 for MCP4725)

INL

V

OUTVIdeal

–()

LSB

---------------------------------------

=

Where:

V

Ideal

= Code*LSB

V

OUT

= The output voltage measured at

the given input code

010001000

Analog

Output

(LSB)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

110

Ideal Transfer Function

Actual Transfer Function

INL = < -1 LSB

INL = 0.5 LSB

INL = - 1 LSB

DNL

ΔV

OUT

LSB–

LSB

----------------------------------=

Where:

Δ

V

OUT

= The measured DAC output

voltage difference between two adjacent input codes.

4.0 TERMINOLOGY

4.1 Resolution

The resolution is the number of DAC output states that divide the full-scale range. For the 12-bit DAC, the resolution is 212 or the DAC code ranges from 0 to

4095.

4.2 LSB

The least significant bit or the ideal voltage difference between two successive codes.

EQUATION 4-1:

4.3 Integral Nonlinearity (INL) or Relative Accuracy

INL error is the maximum deviation between an actual code transition point and its corresponding ideal transition point (straight line). Figure 2-5 shows the INL curve of the MCP4725. The end-point method is used for the calculation. The INL error at a given input DAC code is calculated as:

FIGURE 4-1: INL Accuracy.

4.4 Differential Nonlinearity (DNL)

Differential nonlinearity error (Figure 4-2) is the measure of step size between codes in actual transfer function. The ideal step size between codes is 1 LSB. A DNL error of zero would imply that every code is exactly 1 LSB wide. If the DNL error is less than 1 LSB, the DAC guarantees monotonic output and no missing codes. The DNL error between any two adjacent codes is calculated as follows:

EQUATION 4-3:

EQUATION 4-2:

MCP4725

010

001

000

Analog Output (LSB)

DAC Input Code

011

111

100

101

1

2

3

4

5

6

0

7

DNL = 2LSB

DNL = 0.5 LSB

110

Ideal Transfer Function Actual Transfer Function

Analog Output

Ideal Transfer Function

Actual Transfer Function

DAC Input Code

0

Offset

Error

FSE

V

OUTVIdeal

–()

LSB

---------------------------------------=

Where:

V

Ideal

=(V

REF

) (1 - 2-n) - V

OFFSET

V

REF

= The reference voltage.

V

REF

= VDD in the MCP4725

Analog Output

Actual Transfer Function

DAC Input Code

0

Gain Error

Ideal Transfer Function

after Offset Error Removed

Full-Scale

Error

FIGURE 4-2: DNL Accuracy.

In the MCP4725, the gain error is not calibrated at the factory and most of the gain error is contributed by the output op amp saturation near the code range beyond

4000. For the applications which need the gain error specification less than 1% maximum, the user may consider using the DAC code range between 100 and 4000 instead of using full code range (code 0 to 4095). The DAC output of the code range between 100 and 4000 is much linear than full-scale range (0 to 4095). The gain error can be calibrated by software in applications.

4.7 Full-Scale Error (FSE)

Full-scale error (Figure 4-4) is the sum of offset error plus gain error. It is the difference between the ideal and measured DAC output voltage with all bits set to one (DAC input code = FFFh).

EQUATION 4-4:

4.5 Offset Error

Offset error (Figure 4-3) is the deviation from zero voltage output when the digital input code is zero. This error affects all codes by the same amount. In the MCP4725, the offset error is not trimmed at the factory. However, it can be calibrated by software in application circuits.

FIGURE 4-3: Offset Error.

4.6 Gain Error

Gain error (see Figure 4-4) is the difference between the actual full-scale output voltage from the ideal output voltage on the transfer curve. The gain error is calculated after nullifying the offset error, or full scale error minus the offset error.

The gain error indicates how well the slope of the actual transfer function matche s the slope of th e ideal transfe r function. The gain error is usually expressed as percent of full-scale range (% of FSR) or in LSB.

FIGURE 4-4: Gain Error and Full-Scale Error.

4.8 Gain Error Drift

Gain error drift is the variation in gain error due to a change in ambient temperature. The gain error drift is typically expressed in ppm/oC.

4.9 Offset Error Drift

Offset error drift is the variation in offset error due to a change in ambient temperature. The offset error drift is typically expressed in ppm/

o

C.

4.10 Settling Time

The Settling time is the time delay required for the DAC output to settle to its new output value from the start of code transition, within specified accuracy. In the MCP4725, the settling time is a measure of the time delay until the DAC output reaches its final value (within 0.5 LSB) when the DAC code changes from 400h to C00h.

4.11 Major-Code Transition Glitch

Major-code transition glitch is the impulse energy injected into the DAC analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-Sec. and is measured when the digital code is changed by 1 LSB at the major carry transition (Example: 011...111 to 100... 000, or

100... 000 to 011 ... 111).

MCP4725

4.12 Digital Feedthrough

Digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. It is specified in nV-Sec. and is measured with a full scale change on the digital input pins (Example: 000... 000 to 111... 111, or 111... 111 to

000... 000). The digital feedthrough is measured when

the DAC is not being written to the register.

Microchip Technology Inc MCP4725A0T-E-CH, MCP4725 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 ELECTRICAL CHARACTERISTICS

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: DNL vs. Code (VDD = 5.5V).

FIGURE 2-5: INL vs. Code.

FIGURE 2-8: Zero Scale Error vs. Temperature (Code = 000d).

FIGURE 2-10: Output Error vs. Temperature (Code = 4000d).

FIGURE 2-9: Full-Scale Error vs. Temperature (Code = 4095d).

FIGURE 2-12: IDD Histogram .

FIGURE 2-16: Source and Sink Current Capability.

FIGURE 2-19: Full-Scale Settling Time.

FIGURE 2-21: Half-Scale Settling Time.

FIGURE 2-22: Half-Scale Settling Time.

FIGURE 2-20: Full-Scale Settling Time.

FIGURE 2-23: Code Change Glitch.

FIGURE 2-24: Exiting Power Down Mode.

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN FUNCTION TABLE

3.2 Supply Voltage (VDD, VSS)

3.4 Serial Clock Pin (SCL)

3.5 Device Address Selection Pin (A0)

3.3 Serial Data Pin (SDA)

4.0 TERMINOLOGY

4.1 Resolution

4.2 LSB

4.3 Integral Nonlinearity (INL) or Relative Accuracy

FIGURE 4-1: INL Accuracy.

4.4 Differential Nonlinearity (DNL)

FIGURE 4-2: DNL Accuracy.

4.7 Full-Scale Error (FSE)

4.5 Offset Error

FIGURE 4-3: Offset Error.

4.6 Gain Error

FIGURE 4-4: Gain Error and Full-Scale Error.

4.8 Gain Error Drift

4.9 Offset Error Drift

4.10 Settling Time

4.11 Major-Code Transition Glitch

4.12 Digital Feedthrough