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MCP3202-CI-SN
Datasheet
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Microchip Technology Inc MCP3202-CI-P, MCP3202-CI-SN Datasheet

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MCP3202
2.7V Dual Channel 12-Bit A/D Converter with SPI® Serial Interface

FEATURES

• 12-bit resolution
• ±1 LSB max DNL
• ±1 LSB max INL (MCP3202-B)
• ±2 LSB max INL (MCP3202-C)
• Analog inputs programmable as single-ended or pseudo-differential pairs
• On-chip sample and hold
®
• SPI
serial interface (modes 0,0 and 1,1)
• Single supply operation: 2.7V - 5.5V
• 100ksps max. sampling rate at VDD = 5V
• 50ksps max. sa mpling rate at V
= 2.7V
DD
• Low power CMOS technology
- 500nA typical standby current, 5µA max.
- 550µA max. active current at 5V
• Industrial temp range: -40°C to +85°C
• 8-pin PDIP SOIC and TSSOP packages

APPLICATIONS

• Sensor Interface
• Process Control
• Data Acquisition
• Battery Operated Systems
PAC K AGE TYPES
PDIP
CS/SHDN
CH0 CH1
V
SS
MCP3202
8
1 2
3 4
V
DD/VREF
CLK
7 6
D
OUT
5
D
IN
SOIC, TSSOP
MCP3202
CS/SHDN
CH0 CH1
V
1 2 3
4
SS
8
VDD/V CLK D
OUT
D
IN
REF
7 6
5
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
SS

DESCRIPTION

The Microchip Tech nology Inc. MCP3 202 is a succ es­sive approximation 12-bit Analog-to-Digital (A/D) Con-
CH0 CH1
verter with on-board sample and hold circuitry. The MCP3202 is programmable to provide a single pseudo-differential input pair or dual single-ended inputs. Differential Nonlinearity (DNL) is specified at ±1 LSB, and Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3202-B) and ±2 LSB (MCP3202-C) ver­sions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of conversion rates of up to 100ksps at 5V and 50ksps at 2.7V. The MCP3202 device operates over a broad voltage range (2.7V -
5.5V). Low current design permits operation with typi-
cal standby and active currents of only 500nA and 375µA, respectively. The MCP3202 is offered in 8-pin PDIP, TSSOP and 150mil SOIC packages.
1999 Microchip Technology Inc. Preliminary DS21034A-page 1
Input
Channel
Mux
Sample
and Hold
Control Logic
CS/SHDN
DAC
Comparator
D
IN
CLK
12-Bit SAR
Shift
Register
D
OUT
MCP3202
1.0 ELECTRICAL
PIN FUNCTION TABLE
CHARACTERISTICS
NAME FUNCTION
1.1 Maximum Ratings*
VDD.........................................................................7.0V
All inputs and outputs w.r.t. V
Storage temperature..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds)..+300°C
ESD protection on all pins...................................> 4kV
*Notice: Stresses above those listed under “Maximum R atings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listin gs of this spe cificat ion is not implied. Exposure to maximum rating conditions for extended peri­ods may affect device reliability.
...... -0.6V to VDD +0.6V
SS
V
CH0 CH1 CLK D D CS/SHDN
DD/VREF
IN OUT
+2.7V to 5.5V Power Supply and Reference Voltage Input
Channel 0 Analog Input Channel 1 Analog Input Serial Clock Serial Data In Serial Data Out Chip Select/Shutdown Input
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5.5V, VSS = 0V, T
unless otherwise noted.
PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Convers ion Rate
Conversion Time t
Analog Input Sample Time t
Throughput Rate f
CONV
SAMPLE
SAMPLE
DC Accuracy
Resolution 12 bits Integral Nonlinearity INL ±0.75
Different ial Nonlinea rity DNL ±0.5 ±1 LSB No missing codes over
Offset Error ±1.25 ±3 LSB Gain Error ±1.25 ±5 LSB
Dynamic Performance
Total Harmonic Distortion -82 dB V Signal to Noise and Distortion
(SINAD) Spurious Free Dynamic Range 86 dB VIN = 0.1V to 4.9V@1kHz
Analog Inputs
Input V olta ge Range for CH0 or CH1 in Single-Ended Mode
Input Voltage Range for IN+ in Pseudo-Differential Mode
Input Voltage Range for IN- in Pseudo-Differential Mode
Leakage Current .001 ±1 µA Switch Resistance R
Sample Capacitor C
SS
SAMPLE
= -40°C to +85°C, f
AMB
= 100ksps and f
SAMPLE
CLK
= 18*f
SAMPLE
12 clock
cycles
1.5 clock cycles
±1
100
50
±1 ±2
ksps ksps
LSB LSB
VDD = V VDD = V
REF REF
MCP3202-B MCP3202-C
= 5V
= 2.7V
temperature
= 0.1V to 4.9V@1kHz
IN
72 dB V
V
SS
IN- V
V
REF
+IN- See Sections 3.1 and 4.1
REF
V
= 0.1V to 4.9V@1kHz
IN
VSS-100 VSS+100 mV See Sections 3.1 and 4.1
1K Ω See Figure 4-1 20 pF See Figure 4-1
DS21034A-page 2 Preliminary 1999 Microchip Technology Inc.
MCP3202
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5.5V, VSS = 0V, T unless otherwise noted.
PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Digital Input/Output
Data Coding Format Straight Binary High Level Input Voltage V
Low Level Input Voltage V High Level Output Voltage V Low Level Output Voltage V Input Leakage Current I
Output Leakage Current I Pin Capacitance (All
Inputs/Outputs)
LO
CIN, C
IH
IL
OH
OL
LI
OUT
Timing Parameters
Clock Frequency f
Clock High Time t Clock Low Tim e t
Fall To First Rising CLK
CS Edge
Data Input Setup Time t Data Input Hold Time t CLK Fall To Output Data Valid t CLK Fall To Output Enable t CS
Rise To Output Disable t
CS Disable Time t D
Rise Time t
OUT
D
Fall Time t
OUT
CLK
t
SUCS
CSH
HI
LO
SU
HD
DO
EN
DIS
R
F
Power Requirements
Operating Voltage V Operating Current I Standby Current I
DD
DD
DDS
Note 1: This parameter is guaranteed by characterization and not 100% tested. Note 2: Because the sample ca p w il l eventually lose charge, effective clock rates below 10kHz c an affe ct linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
= -40°C to +85°C, f
AMB
0.7 V
DD
0.3 V
= 100ksps and f
SAMPLE
DD
= 18*f
CLK
SAMPLE
V V
4.1 V IOH = -1mA, VDD = 4.5V
0.4 V IOL = 1mA, VDD = 4.5V
-10 10 µA VIN = VSS or V
-10 10 µA V
= VSS or V
OUT
DD
10 pF VDD = 5.0V (Note 1)
T
= 25°C, f = 1 MHz
AMB
1.8
0.9
MHz MHz
VDD = 5V (Note 2) VDD = 2.7V (Note 2)
250 ns 250 ns 100 ns
50 ns
50 ns 200 ns See Test Circuits, Figure1-2 200 ns See Test Circuits, Figure1-2 100 ns See Test Circuits, Figure1-2
Note 1
500 ns
100 ns See Test Circuits, Figure1-2
Note 1
100 ns See Test Circuits, Figure1-2
Note 1
2.7 5.5 V 375 550 µA VDD = 5.0V, D
OUT
0.5 5 µA CS = VDD = 5.0V
DD
unloaded
1999 Microchip Technology Inc. Preliminary DS21034A-page 3
MCP3202
t
CSH
CS
t
SUCS
CLK
t
t
SU
D
IN MSB IN
D
OUT
FIGURE 1-1: Serial Timing.
Load circuit for tR, t
1.4V
3K
D
OUT
= 100pF
C
L
HD
F, tDO
Test Point
t
t
LO
HI
t
t
EN
DO
NULL BIT
MSB OUT
t
R
Load circuit for
t
F
t
DIS
LSB
and t
EN
t
DIS
Test Point
V
DD
D
3K
OUT
VDD/2
100pF
V
SS
t
Waveform 2
DIS
tEN Waveform
t
Waveform 1
DIS
Voltage Waveforms for tR, t
D
OUT
t
R
Voltage Waveforms for t
CLK
D
OUT
F
V
OH
V
OL
t
F
CS
CLK
D
OUT
DO
t
DO
Waveform 1*
Waveform 2
Voltage Waveforms for t
V oltage Waveforms for t
CS
D
OUT
D
OUT
†
EN
12
t
EN
DIS
V
IH
T
DIS
3
10%
4
B11
90%
* Waveform 1 is for an output with internal condi-
tions such that the output is high, unless dis­abled by the output control.
† Waveform 2 is for an output with internal condi-
tions such that the output is low, unless disabled by the output control.
FIGURE 1-2: Test Circuits.
DS21034A-page 4 Preliminary 1999 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, f
SAMPLE =
100ksps, f
CLK
= 18* f
SAMPLE,TA
MCP3202
= 25°C
1.0
0.8
Positive INL
0.6
0.4
0.2
0.0
-0.2
INL (LSB)
-0.4
Negative INL
-0.6
-0.8
-1.0 0 25 50 75 100 125 150
Sample Rat e (ksps)
FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate.
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
INL (LSB)
-0.4
-0.6
-0.8
-1.0
3.03.54.04.55.0
Positi ve INL
VDD(V)
F
= 100ksps
SAMPLE
Negative INL
2.0
VDD = 2.7V
1.5
1.0
Posi ti ve INL
0.5
0.0
-0.5
INL (LSB)
Negative INL
-1.0
-1.5
-2.0 0 20406080100
Sample Rate (ksps)
FIGURE 2-4: Integral Nonl inearity (INL) vs. Sample Rate (V
= 2.7V).
DD
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
INL (LSB)
-0.4
-0.6
-0.8
-1.0
2.5 3.0 3.5 4.0 4.5 5.0
Positive INL
Negative INL
F
SAMPLE
VDD(V)
= 50ksps
FIGURE 2-2: Integral Nonlinearity (INL) vs. V
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
INL (LSB)
-0.4
-0.6
-0.8
-1.0 0 512 1024 1536 2048 2560 3072 3584 4096
DD
.
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).
FIGURE 2-5: Integral Nonlinearity (INL) vs. V
1.0
VDD = 2.7V
INL (LSB)
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
= 50ksps
F
SAMPLE
0 512 1024 1536 2048 2560 3072 3584 4096
DD.
Digital Code
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, V
= 2.7V).
DD
1999 Microchip Technology Inc. Preliminary DS21034A-page 5
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, f
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
INL (LSB)
-0.4
-0.6
-0.8
-1.0
-50 -25 0 25 50 75 100
Positive INL
Negative INL
Tem perature ( °C)
FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature.
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
DNL (LSB)
-0.4
-0.6
-0.8
-1.0 0 25 50 75 100 125 150
Positive DNL
Negative DNL
Sampl e Rat e (ksps)
SAMPLE =
100ksps, f
INL (LSB)
= 18* f
CLK
1.0
VDD = 2.7V
0.8
F
SAMPLE
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-50 -25 0 25 50 75 100
SAMPLE,TA
= 50ksps
= 25°C
Positive INL
Negative INL
Tem perature ( °C)
FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (V
2.0
1.5
1.0
0.5
0.0
-0.5
DNL (LSB)
-1.0
-1.5
-2.0
= 2.7V).
DD
VDD = 2.7V
Positive DNL
Negativ e DNL
020406080100
Sample Rate (ksps)
FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
DNL (LSB)
-0.4
-0.6
-0.8
-1.0
2.5 3.0 3.5 4.0 4.5 5.0
Positive DNL
Negative DNL
VDD(V)
FIGURE 2-9: Differential Nonlinearity (DNL) vs. V
F
SAMPLE
= 100ksps
DD
FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (V
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
DNL (LSB)
-0.4
-0.6
-0.8
-1.0
2.5 3.0 3.5 4.0 4.5 5.0
.
FIGURE 2-12: Differential Nonlinearity (DNL) vs. V
= 2.7V).
DD
Positive DNL
Negative DNL
VDD(V)
F
SAMPLE
= 50ksps
DD.
DS21034A-page 6 Preliminary 1999 Microchip Technology Inc.
MCP3202
)
)
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, f
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
DNL (LSB)
-0.4
-0.6
-0.8
-1.0 0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code
FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
DNL (LSB)
-0.4
-0.6
-0.8
-1.0
-50 -25 0 25 50 75 100
Positive DNL
Negative DNL
Tem per ature (°C)
SAMPLE =
100ksps, f
DNL (LSB)
= 18* f
CLK
1.0
VDD = 2.7V
0.8
F
SAMPLE
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0 0 512 1024 1536 2048 256 0 3072 3584 4096
SAMPLE,TA
= 50ksps
= 25°C
Digit a l Code
FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, V
1.0
VDD = 2.7V
0.8
F
= 50ksps
SAMPLE
0.6
0.4
0.2
0.0
-0.2
DNL (LSB)
-0.4
-0.6
-0.8
-1.0
-50 -25 0 25 50 75 100
Tem p erature (°C)
DD
Positive DNL
Negative DNL
= 2.7V).
FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.
2.0
1.5
1.0
0.5
0.0
-0.5
Gain Error (LSB
-1.0
F
-1.5
-2.0
SAMPLE
2.5 3.0 3.5 4.0 4.5 5.0
FIGURE 2-15: Gain Error vs. V
= 100ksps
F
SAMPLE
= 10ksps
F
SAMPLE
VDD(V)
= 50ksps
DD
.
FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
Offset Error (LSB
0.4
0.2
0.0
2.53.03.54.04.55.0
FIGURE 2-18: Offset Error vs. V
= 2.7V).
DD
F
SAMPLE
= 100ksps
F
VDD(V)
SAMPLE
= 50ksps
DD
.
F
SAMPLE
= 10ksps
1999 Microchip Technology Inc. Preliminary DS21034A-page 7
MCP3202
)
)
)
Input Signal Level (dB)
)
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, f
1.0
0.8
0.6
VDD = 2.7V F
0.4
0.2
0.0
-0.2
-0.4
Gain Error (LSB
-0.6
-0.8
-1.0
-50 -25 0 25 50 75 100
SAMPLE
= 50ksps
VDD = 5V F
SAMPLE
= 100ksps
Tem p erature (°C)
FIGURE 2-19: Gain Error vs. Temperature.
100
90 80 70 60 50 40
SNR (dB)
30
V F
= 2.7V
DD
SAMPLE
= 50ksps
20 10
0
1 10 100
Input F r equency ( kH z)
V
DD
F
SAMPLE
= 5V
= 100ksps
SAMPLE =
100ksps, f
Offset Error (LSB
= 18* f
CLK
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50-25 0 25 50 75100
SAMPLE,TA
VDD = 5V F
SAMPLE
VDD = 2.7V F
SAMPLE
= 25°C
= 100ksps
= 50ksps
Tem p erature (°C)
FIGURE 2-22: Offset Error vs. Temperature.
100
90 80 70 60 50 40
SINAD (dB
30
VDD = 2.7V F
SAMPLE
= 50ksps
20 10
0
110100
Input Frequency (kH z)
V F
= 5V
DD
SAMPLE
= 100ksps
FIGURE 2-20: S ignal to No ise Rat io (SN R) vs. I nput Frequency.
0
-10
-20
-30
-40
-50
-60
THD (dB)
-70
-80
-90
-100
V
= 2.7V
DD
= 50ksps
F
SAMPLE
VDD = 5V
= 100ksps
F
SAMPLE
1 10 100
FIGURE 2-23: Signal to Noise and Distortion (SINAD) vs. Input Frequency.
80 70 60 50 40 30
SINAD (dB
20 10
0
-40-35-30-25-20-15-10 -5 0
VDD = 5V F
SAMPLE
= 100ksps
VDD = 2.7V F
SAMPLE
= 50ksps
Input F r equency (k Hz )
FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.
DS21034A-page 8 Preliminary 1999 Microchip Technology Inc.
FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Signal Level.
MCP3202
)
)
)
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, f
12.0
F
= 50ksps
SAMPLE
11.5
11.0
F
= 100ksps
10.5
10.0
ENOB (rms
9.5
9.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
SAMPLE
VDD (V)
FIGURE 2-25: Effective number of bits (ENOB) vs. V
DD
.
100
90 80 70 60 50 40
SFDR (dB)
30 20 10
0
110100
VDD = 2.7V F
SAMPLE
= 50ksps
Input F requency (kHz)
VDD = 5V F
SAMPLE
= 100ksps
SAMPLE =
100ksps, f
ENOB (rms)
= 18* f
CLK
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0 110100
SAMPLE,TA
= 25°C
VDD = 2.7V F
SAMPLE
= 50ksps
VDD = 5V F
SAMPLE
= 100ksps
Input F requency (kH z)
FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
0
-10
-20
-30
-40
-50
-60
-70
Power Supply Rejection (dB
-80 1 10 100 1000 10000
Ripple Frequency (kHz)
FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
Amplitude (dB)
-100
-110
-120
-130 0 10000 20000 30000 40000 50000
Frequency ( H z )
FIGURE 2-27: Frequency Spectrum of 10kHz input (Representative Part).
VDD = 5V
= 100ksps
F
SAMPLE
= 9.985kHz
F
INPUT
4096 points
FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
Amplitude (dB
-100
-110
-120
-130 0 5000 10000 15000 20000 25000
VDD = 2.7V F
= 50ksps
SAMPLE
F
= 998.76Hz
INPUT
4096 points
Frequenc y ( H z )
FIGURE 2-30: Frequency Spectrum of 1kHz input (Representative Part, V
= 2.7V).
DD
1999 Microchip Technology Inc. Preliminary DS21034A-page 9
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, f
500
All points at F
450
at V
400 350 300 250
(µA)
DD
I
200 150 100
50
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 2-31: IDD vs. V
500 450 400
VDD = 5V
350 300 250
IDD (µA)
200 150 100
50
0
10 100 1000 10000
= 1.8MHz except
CLK
= 2.5V, F
DD
VDD = 2.7V
CLK
= 900kHz
Cl ock Frequency ( k H z )
DD
VDD (V)
.
SAMPLE =
100ksps, f
(pA)
DDS
I
= 18* f
CLK
80
CS = V
70 60 50 40 30 20 10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SAMPLE,TA
DD
= 25°C
VDD (V)
FIGURE 2-34: I
100.00
10.00
(nA)
1.00
DDS
I
0.10
0.01
-50 -25 0 25 50 75 100
DDS
VDD = CS = 5V
vs. V
DD
.
Temperature (°C)
FIGURE 2-32: IDD vs. Clock Frequency.
500
VDD = 5V
450
F
= 1.8MHz
CLK
400 350 300 250
(µA)
DD
I
200 150 100
50
0
-50-25 0 255075100
VDD = 2.7V F
= 900kHz
CLK
Tem perature ( °C)
FIGURE 2-33: IDD vs. Temperature.
FIGURE 2-35: I
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Analog Input Leakage (nA)
0.0
-50 -25 0 25 50 75 100
vs. Temperature.
DDS
VDD = 5V F
= 1.8MHz
CLK
Tem perature (°C)
FIGURE 2-36: Analog Input leakage current vs. Temperature.
DS21034A-page 10 Preliminary 1999 Microchip Technology Inc.
MCP3202
3.0 PIN DESCRIPTIONS
3.1 CH0/CH1
Analog inputs for c han nel s 0 a nd 1 respectively. These channels can prog r am me d to b e us ed as tw o indepe n­dent channels in single ended-mode or as a single pseudo-differentia l inpu t where on e chan nel is IN+ an d one channe l is IN- . Se e S ectio n 5.0 for infor m atio n on programming the channel configuration.
3.2 CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conver­sion and put the device in low power standby when pulled high. The CS
/SHDN pin must be pulled high
between conversions.
3.3 CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed.
3.4 DIN (Serial Data Input)
The SPI port serial data input pin is used to clock in input channel configuration data.
3.5 DOUT (Serial Data output)
The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.
4.0 DEVICE OPERATION
The MCP3202 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the con­verter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100ksps are possible on the MCP3202. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface.
4.1 Analog Inputs
The MCP3202 device offers the choice of using the ana­log input channels configured as two single-ended inputs or a single pseudo-differential input. Configura­tion is done as part of the serial command before each conversion begins. When used in the ps uedo- diff eren­tial mode, CH0 and CH1 are programmed as the IN+ and IN- inputs as part of the command string transmit­ted to the device. The IN+ input can range from IN- to
(V
V
REF
from the V
+ IN-). The IN- input is limited to ±100mV
REF
rail. The IN- input can be used to cancel
SS
small signal common-mode noise which is present on both the IN+ and IN- inputs.
For the A/D Con verter to meet spe cification, the charge holding capacitor (C
) must be given enough time
SAMPLE
to acquire a 12-bit accurate voltage level during the
1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1.
In this diagram, it is shown that the source impedance
) adds to the internal sampling switch (RSS) imped-
(R
S
ance, directly affecting the time that is required to charge the capacitor, C
. Consequently, larger
SAMPLE
source impedances increase the offset, gain, and inte­gral linearity errors of the conversion.
Ideally, the impedance of the signal source should be near zero. This is achievable with an operational ampli­fier such as the MCP601 which has a closed loop out­put impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2.
When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code wi ll be 000h. If t he voltag e at IN+ is e qual to or greater than {[V
+ (IN-)] - 1 LSB}, then the out-
REF
put code will be FFFh . If the v olta ge level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below V code. Conv ersely, if IN- is more than 1 LSB ab ov e V
to see the 000h output
SS
SS
then the FFFh code wil l not be seen unless the IN+ input level goes above V
REF
level .
4.2 Digital Output Code
The digital output code produced by an A/D Converter is a function of the input signal and the reference volt­age. For the MCP3202, VDD is used as the reference voltage. As the V reduced according ly . The th eoretical dig ital output code produced by the A/D Converter is shown below.
level is reduced, the LSB size is
DD
,
Digital Output Code = 4096 * V
IN
V
DD
where:
V
= analog input voltage
IN
= supply voltage
V
DD
1999 Microchip Technology Inc. Preliminary DS21034A-page 11
MCP3202
CHx
R
S
VA
Legend
VA
= Signal Source
R
= Source Impedance
S
CHx
= Input Channel Pad
C
= Input Capacitance
PIN
V
= Threshold Voltage
T
I
= Leakage Current at the pin
LEAKAGE
C
due to various junctions
SS
= Sampling Switch
R
= Sampling Switch Resistor
SS
= Sample/Hold Capacitance
SAMPLE
C
PIN
7pF
V
DD
V
= 0.6V
T
V
= 0.6V
T
I
LEAKAGE
±1nA
Sampling Switch
R
SS
= 1kΩ
SS
C
SAMPLE
= DAC capacitance = 20 pF
V
SS
FIGURE 4-1: Analog Input Model.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
Clock Frequency (MHz)
0.2
0.0 100 1000 10000
Input R esi st a nce (O hm s)
VDD = 2.7V
VDD = 5V
FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (R
) to maintain less than a 0.1 LSB
S
deviation in INL from nominal conditions.
DS21034A-page 12 Preliminary 1999 Microchip Technology Inc.
MCP3202
5.0 SERIAL COMMUNICATIONS
5.1 Overview
Communication with the MCP3202 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the
line low. See Figure 5-1. If the device was powered
CS up with the CS low to initiate communicatio n. The first cl ock received with CS low and DIN high will constitute a start bit. The SGL/DIFF and are used to select the input channel configuration. The SGL/DIFF is used to select single ended or psuedo-differential mode. The ODD/SIGN which chann el is used in single ended mode, an d is used to determine polarity in pseudo-differential mode. Following the ODD/SIGN ted to and is used to enable the LSB first format for the device. If the MSBF bit is low, then the data will come from the device in MSB first format and any further clocks with CS zeros. If the MSBF bit is high , then the de vice will outp ut the conver ted word LSB first transmitted in the MSB first format. See Figure 5-2. Table 5-1 shows the configuration bits for the MCP3202. The device will begin to sample the analog input on the second rising edge of the clock, after the start bit has been rec eived. The sample pe riod w i ll end on the falling edge of the third clock following the start bit.
On the falling edge of the clock for the MSBF bit, the device will output a low null bit. The next sequential 12 clocks will output the result of the conversion with
pin low, it must be brought high and back
bit and the ODD/SIGN bit follow the start bit
bit selects
bit, the MSBF bit is transmit-
low will cause the device to output
after
the word has been
MSB first as shown in Figure 5-1. Data is always output from the device on the fall ing edge of the cloc k. If all 12 data bits have been transmitted and the device contin­ues to receive clocks while the CS
is held low, (and MSBF = 1), the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are pro­vided to the device while CS
is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely.
If necessary, it is possible to bring CS leading zeros on the D
line before the start bit. This is
IN
low and clock in
often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 for more details on using the MCP3202 devices with hardware SPI ports.
SINGLE
ENDED MODE
PSEUDO-
DIFFERENTIAL
MODE
CONFIG
BITS
SGL/ DIFF
ODD/ SIGN
10+ ­11 +-
00IN+IN­01IN-IN+
CHANNEL
SELECTION
01
GND
TABLE 5-1: Configuration Bits for the MC P3202.
t
CYC
t
CS
t
SUCS
CLK
ODD/
SIGN
t
SAMPLE
MS BF
Don’t Care
Null
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Bit
t
CONV
SGL/
D
IN
D
OUT
Start
DIFF
HI-Z
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See
Figure 5-2 below for details on obtaining LSB first data.
: during this time, th e bias cur rent an d the com parator power down while the refe rence in put beco mes a hi gh imp edanc e
** t
DATA
node, leaving the CLK running to clock out the LSB-first data or zeros.
CSH
t
DATA**
Start
t
HI-Z
CYC
SGL/
DIFF
ODD/ SIGN
1999 Microchip Technology Inc. Preliminary DS21034A-page 13
MCP3202
FIGURE 5-1: Communication with the MCP3202 using MSB first format only.
t
CYC
CS
t
SUCS
CLK
Power Down
t
CSH
D
IN
D
OUT
Start
HI-Z
t
SAMPLE
DIFF
SGL/
SIGN
ODD/
MSBF
Null
B11 B10B9B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
Bit
(MSB)
t
CONV
Don’t Care
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
: During this time, the bias circuit and the comparat or power down while th e referenc e input becom es a high impe dance
** t
DATA
node, leaving the CLK running to clock out LSB first data or zeroes.
FIGURE 5-2: Communication with MCP3202 using LSB first format.
t
DATA
HI-Z
*
**
DS21034A-page 14 Preliminary 1999 Microchip Technology Inc.
MCP3202
6.0 APPLICATIONS INFORMATION
6.1 Using the MCP3202 with Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of cloc k and latch data in on the rising edge. Depending on how communication routines are used, it is very possible that the number of clocks required for communication will not be a multiple of eight. Therefore, it may be necessary for the MCU to send more clocks than are actually required. This is usually
done by sending ‘leading zeros’ before the start bit, which are ignored by the device. As an example, Figure 6-1 and Figure 6-2 show how the MCP3202 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation sho wn in SPI Mode 0,0,
CS
MCU latches data from A/D Converter on rising edges of SCLK
SCLK
D
IN
1 2 3 4 5 6 7 8 9 10111213141516
Data is clocked out of A/D Converter on falling edges
SGL/
Start
DIFF
ODD/
which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the ‘high’ state .
As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains seven leading zeros before the start bit. Arranging the leading zeros this way produces the output 12 bits to fall in positions easily manipulate d by the MCU. The MSB is clocked out of the A/D Con­verter on the falling edge of clock number 12. After the second eight clocks have been sent to the device, the MCU receive buffer will contain three unknown bits (the output is at high i mpedance unt il the null bit is clocked out), the null bit and t he highest order four bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method.
17 18 19 20 21 22 23 24
SIGN
MSBF
Don’t Care
D
OUT
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
X = Don’t Care Bits
HI-Z
Start
XXXXX
XXXXXXXX
Data stored into MCU receive reg ister
after transmission of first 8 bits
Bit
1
X
X
XXX
Data stored into MCU receive register
NULL
B11 B10 B9 B8
BIT
SGL/
ODD/
MSBF
DIFF
SIGN
after transmission of second 8 bits
XX XXX
B11 B10 B9 B80
(Null)
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Data stored into MCU receive r egister
FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
MCU latches data from A/D Converter
CS
on rising edges of SCLK
SCLK
D
IN
D
OUT
MCU Transmitted Data
(Aligned with falling
edge of clock) MCU Received Data
(Aligned with rising
edge of clock)
1 2 3 4 5 6 7 8 9 101112131415 16
Data is clocked out of A/D Converter on falling edges
Start
SGL/
DIFF
ODD/
SIGN
MSBF
HI-Z
Start
Bit
00000
XXXXXXXX
1
0
0
SGL/
ODD/
DIFF
SIGN
XXX
NULL
B11 B10 B9
BIT
MSBF
XX XXX
B11 B10 B9 B80
(Null)
17 18 19 20 21 22 23 24
Don’t Care
B7
B8
XXXXX XXX
B7 B6 B5 B4 B3 B2 B1 B0
XXXXXXXX
after transmission of last 8 bits
B6 B5 B4 B3 B2 B1 B0
X = Don’t Care Bits
Data stored into MCU receive re gister
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
Data stored into MCU receive register
after transmission of last 8 bits
FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
1999 Microchip Technology Inc. Preliminary DS21034A-page 15
MCP3202
6.2 Maintaining Minimum Clock Speed
When the MCP3202 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is impor tant for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85°C (worst case condition), the part will
maintain proper charge on the sample capacitor for at least 1.2ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked o ut must n ot e xc eed 1.2 ms (effect iv e cl oc k fre­quency of 10kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specif icat ions. It sh ould b e note d that du ri ng the entire conversion cycle, the A/D Converter does not require a constant cloc k speed or du ty cycle, as long as all timing specification s are met .
6.3 Buffering/Filtering the Analog Inputs
If the signal source for the A/D Converter is not a low impedance source , it will ha v e to be b uffered or inaccu­rate conversion results may occur. It is also recom­mended that a filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Fi gure 6-3 below where an op amp is used to drive the analog input of the MCP3202. This amplifier provides a low impedance output for the con­verter input and a low pass filter, which eliminates unwanted high frequency noise.
Low pass (anti-aliasing) filters can be designed using Microchip’s i nt eracti ve FilterLab
will calculate capacitor and resistor values, as well as, determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699
Filters for Data Acqu is iti on Sys tem s.”
4.096V
Reference
0.1µF
C
1
R
1
R
V
IN
2
C
2
REF198
MCP601
+
-
R
4
R
3
ADI
™
software. FilterLab
“Anti-Aliasing Analog
1µF
0.1µF
Tant.
V
REF
IN+
MCP3202
IN-
V
DD
10uF
1µF
6.4 Layout Considerations
When layi ng out a printed ci rcuit board for u se with ana­log components, care should be taken to reduce noise wherever possible. A bypas s capacitor sh ould always be used with th is device and should be plac ed as clos e as possibl e to the d evice pin. A bypass c apa ci tor value
of 1µF is recommended. Digital and analo g trace s should be sepa rated a s muc h
as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possi­ble from analog traces.
Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing V devices in a “star” conf igurat ion can al so re duc e nois e by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converters, refer to AN688
out Tips for 12-Bit A/D Converter Applications”
V
DD
Connection
Device 1
Device 2
FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths.
connections to
DD
Device 4
Device 3
“Lay-
.
FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3202.
DS21034A-page 16 Preliminary 1999 Microchip Technology Inc.
FilterLab is a tra demark of Microchip Technolog y Inc. in the U.S.A and other countries. All rights reserved.
MCP3202

MCP3202 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
MCP3202 - G T /P
Package: P = PDIP (8 lead)
Temperature I=–40 °C to +85°C Range:
Performance B = ±1 LSB INL (TSSOP not available in this grade) Grade: C=±2 LSB INL
Device: MCP3202
SN = SOIC (150 mil Body), 8 lead
ST = TSSOP, 8 lead (C Grade only)
12-Bit Serial A/D Converter
=
MCP3202T
12-Bit Serial A/D Converter on tape and reel
=
(SOIC and TSSOP packages only)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999 (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc. Preliminary DS21034A-page 17
MCP3202
NOTES:
DS21034A-page 18 Preliminary 1999 Microchip Technology Inc.
NOTES:
MCP3202
1999 Microchip Technology Inc. Preliminary DS21034A-page 19

WORLDWIDE SALES AND SERVICE

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11/15/99
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro
devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 cer tified.
®
8-bit MCUs, KEELOQ
®
code hopping
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper.
Information contained in this publi c ation regarding device applications and the like is i nte nded for suggestion only and may be superseded by updates . No repr esentation or warranty is given and no liability is assumed by Microchip T echnology Incorpora ted with respect to the accuracy or use of such information, or infringe ment of patents or othe r intellec tual property rights arising from such use or otherwis e. Use of Microchi p’s produc ts as critical components in life s upport systems is not authorized except with expres s w ri t ten approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellect ual property rights. The Microchip logo and name are registered trademarks of Mi crochip Technology Inc. in the U.S. A. and other countries. All rights reserved. All other tradem arks mentioned herein are the property of their respective comp ani es .
1999 Microchip Technology Inc.
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