Microchip Technology Inc MCP3202-CI-P, MCP3202-CI-SN Datasheet

MCP3202

2.7V Dual Channel 12-Bit A/D Converter
with SPI® Serial Interface

FEATURES

• 12-bit resolution

• ±1 LSB max DNL

• ±1 LSB max INL (MCP3202-B)

• ±2 LSB max INL (MCP3202-C)

• Analog inputs programmable as single-ended or
pseudo-differential pairs

• On-chip sample and hold

®

• SPI

serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V - 5.5V

• 100ksps max. sampling rate at VDD = 5V

• 50ksps max. sa mpling rate at V

= 2.7V

DD

• Low power CMOS technology

- 500nA typical standby current, 5µA max.

- 550µA max. active current at 5V

• Industrial temp range: -40°C to +85°C

• 8-pin PDIP SOIC and TSSOP packages

APPLICATIONS

• Sensor Interface

• Process Control

• Data Acquisition

• Battery Operated Systems

PAC K AGE TYPES

PDIP

CS/SHDN

CH0
CH1

V

SS

MCP3202

8

1
2

3
4

V

DD/VREF

CLK

7
6

D

OUT

5

D

IN

SOIC, TSSOP

MCP3202

CS/SHDN

CH0
CH1

V

1
2
3

4

SS

8

VDD/V
CLK
D

OUT

D

IN

REF

7
6

5

FUNCTIONAL BLOCK DIAGRAM

V

DD

V

SS

DESCRIPTION

The Microchip Tech nology Inc. MCP3 202 is a succ es­sive approximation 12-bit Analog-to-Digital (A/D) Con-

CH0
CH1

verter with on-board sample and hold circuitry. The
MCP3202 is programmable to provide a single
pseudo-differential input pair or dual single-ended
inputs. Differential Nonlinearity (DNL) is specified at
±1 LSB, and Integral Nonlinearity (INL) is offered in
±1 LSB (MCP3202-B) and ±2 LSB (MCP3202-C) ver­sions. Communication with the device is done using a
simple serial interface compatible with the SPI protocol.
The device is capable of conversion rates of up to
100ksps at 5V and 50ksps at 2.7V. The MCP3202
device operates over a broad voltage range (2.7V -

5.5V). Low current design permits operation with typi-

cal standby and active currents of only 500nA and
375µA, respectively. The MCP3202 is offered in 8-pin
PDIP, TSSOP and 150mil SOIC packages.

 1999 Microchip Technology Inc. Preliminary DS21034A-page 1

Input

Channel

Mux

Sample

and
Hold

Control Logic

CS/SHDN

DAC

Comparator

D

IN

CLK

12-Bit SAR

Shift

Register

D

OUT

MCP3202

1.0 ELECTRICAL

PIN FUNCTION TABLE

CHARACTERISTICS

NAME FUNCTION

1.1 Maximum Ratings*

VDD.........................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature..........................-65°C to +150°C

Ambient temp. with power applied......-65°C to +125°C

Soldering temperature of leads (10 seconds)..+300°C

ESD protection on all pins...................................> 4kV

*Notice: Stresses above those listed under “Maximum R atings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listin gs of this spe cificat ion is
not implied. Exposure to maximum rating conditions for extended peri­ods may affect device reliability.

...... -0.6V to VDD +0.6V

SS

V

CH0
CH1
CLK
D
D
CS/SHDN

DD/VREF

IN
OUT

+2.7V to 5.5V Power Supply and
Reference Voltage Input

Channel 0 Analog Input
Channel 1 Analog Input
Serial Clock
Serial Data In
Serial Data Out
Chip Select/Shutdown Input

ELECTRICAL CHARACTERISTICS

All parameters apply at VDD = 5.5V, VSS = 0V, T

unless otherwise noted.

PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS

Convers ion Rate

Conversion Time t

Analog Input Sample Time t

Throughput Rate f

CONV

SAMPLE

SAMPLE

DC Accuracy

Resolution 12 bits
Integral Nonlinearity INL ±0.75

Different ial Nonlinea rity DNL ±0.5 ±1 LSB No missing codes over

Offset Error ±1.25 ±3 LSB
Gain Error ±1.25 ±5 LSB

Dynamic Performance

Total Harmonic Distortion -82 dB V
Signal to Noise and Distortion

(SINAD)
Spurious Free Dynamic Range 86 dB VIN = 0.1V to 4.9V@1kHz

Analog Inputs

Input V olta ge Range for CH0 or
CH1 in Single-Ended Mode

Input Voltage Range for IN+ in
Pseudo-Differential Mode

Input Voltage Range for IN- in
Pseudo-Differential Mode

Leakage Current .001 ±1 µA
Switch Resistance R

Sample Capacitor C

SS

SAMPLE

= -40°C to +85°C, f

AMB

= 100ksps and f

SAMPLE

CLK

= 18*f

SAMPLE

12 clock

cycles

1.5 clock
cycles

±1

100

50

±1
±2

ksps
ksps

LSB
LSB

VDD = V
VDD = V

REF
REF

MCP3202-B
MCP3202-C

= 5V

= 2.7V

temperature

= 0.1V to 4.9V@1kHz

IN

72 dB V

V

SS

IN- V

V

REF

+IN- See Sections 3.1 and 4.1

REF

V

= 0.1V to 4.9V@1kHz

IN

VSS-100 VSS+100 mV See Sections 3.1 and 4.1

1K Ω See Figure 4-1
20 pF See Figure 4-1

DS21034A-page 2 Preliminary  1999 Microchip Technology Inc.

MCP3202

ELECTRICAL CHARACTERISTICS (CONTINUED)

All parameters apply at VDD = 5.5V, VSS = 0V, T
unless otherwise noted.

PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS

Digital Input/Output

Data Coding Format Straight Binary
High Level Input Voltage V

Low Level Input Voltage V
High Level Output Voltage V
Low Level Output Voltage V
Input Leakage Current I

Output Leakage Current I
Pin Capacitance (All

Inputs/Outputs)

LO

CIN, C

IH

IL

OH

OL

LI

OUT

Timing Parameters

Clock Frequency f

Clock High Time t
Clock Low Tim e t

Fall To First Rising CLK

CS
Edge

Data Input Setup Time t
Data Input Hold Time t
CLK Fall To Output Data Valid t
CLK Fall To Output Enable t
CS

Rise To Output Disable t

CS Disable Time t
D

Rise Time t

OUT

D

Fall Time t

OUT

CLK

t

SUCS

CSH

HI

LO

SU

HD

DO

EN

DIS

R

F

Power Requirements

Operating Voltage V
Operating Current I
Standby Current I

DD

DD

DDS

Note 1: This parameter is guaranteed by characterization and not 100% tested.
Note 2: Because the sample ca p w il l eventually lose charge, effective clock rates below 10kHz c an affe ct linearity

performance, especially at elevated temperatures. See Section 6.2 for more information.

= -40°C to +85°C, f

AMB

0.7 V

DD

0.3 V

= 100ksps and f

SAMPLE

DD

= 18*f

CLK

SAMPLE

V
V

4.1 V IOH = -1mA, VDD = 4.5V

0.4 V IOL = 1mA, VDD = 4.5V

-10 10 µA VIN = VSS or V

-10 10 µA V

= VSS or V

OUT

DD

10 pF VDD = 5.0V (Note 1)

T

= 25°C, f = 1 MHz

AMB

1.8

0.9

MHz
MHz

VDD = 5V (Note 2)
VDD = 2.7V (Note 2)

250 ns
250 ns
100 ns

50 ns

50 ns
200 ns See Test Circuits, Figure1-2
200 ns See Test Circuits, Figure1-2
100 ns See Test Circuits, Figure1-2

Note 1

500 ns

100 ns See Test Circuits, Figure1-2

Note 1

100 ns See Test Circuits, Figure1-2

Note 1

2.7 5.5 V
375 550 µA VDD = 5.0V, D

OUT

0.5 5 µA CS = VDD = 5.0V

DD

unloaded

 1999 Microchip Technology Inc. Preliminary DS21034A-page 3

MCP3202

t

CSH

CS

t

SUCS

CLK

t

t

SU

D

IN MSB IN

D

OUT

FIGURE 1-1: Serial Timing.

Load circuit for tR, t

1.4V

3K

D

OUT

= 100pF

C

L

HD

F, tDO

Test Point

t

t

LO

HI

t

t

EN

DO

NULL BIT

MSB OUT

t

R

Load circuit for

t

F

t

DIS

LSB

and t

EN

t

DIS

Test Point

V

DD

D

3K

OUT

VDD/2

100pF

V

SS

t

Waveform 2

DIS

tEN Waveform

t

Waveform 1

DIS

Voltage Waveforms for tR, t

D

OUT

t

R

Voltage Waveforms for t

CLK

D

OUT

F

V

OH

V

OL

t

F

CS

CLK

D

OUT

DO

t

DO

Waveform 1*

Waveform 2

Voltage Waveforms for t

V oltage Waveforms for t

CS

D

OUT

D

OUT

†

EN

12

t

EN

DIS

V

IH

T

DIS

3

10%

4

B11

90%

* Waveform 1 is for an output with internal condi-

tions such that the output is high, unless dis­abled by the output control.

† Waveform 2 is for an output with internal condi-

tions such that the output is low, unless disabled
by the output control.

FIGURE 1-2: Test Circuits.

DS21034A-page 4 Preliminary  1999 Microchip Technology Inc.

2.0 TYPICAL PERFORMANCE CHARACTERISTICS

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, f

SAMPLE =

100ksps, f

CLK

= 18* f

SAMPLE,TA

MCP3202

= 25°C

1.0

0.8

Positive INL

0.6

0.4

0.2

0.0

-0.2

INL (LSB)

-0.4

Negative INL

-0.6

-0.8

-1.0
0 25 50 75 100 125 150

Sample Rat e (ksps)

FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample
Rate.

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

INL (LSB)

-0.4

-0.6

-0.8

-1.0

3.03.54.04.55.0

Positi ve INL

VDD(V)

F

= 100ksps

SAMPLE

Negative INL

2.0

VDD = 2.7V

1.5

1.0

Posi ti ve INL

0.5

0.0

-0.5

INL (LSB)

Negative INL

-1.0

-1.5

-2.0
0 20406080100

Sample Rate (ksps)

FIGURE 2-4: Integral Nonl inearity (INL) vs. Sample
Rate (V

= 2.7V).

DD

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

INL (LSB)

-0.4

-0.6

-0.8

-1.0

2.5 3.0 3.5 4.0 4.5 5.0

Positive INL

Negative INL

F

SAMPLE

VDD(V)

= 50ksps

FIGURE 2-2: Integral Nonlinearity (INL) vs. V

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

INL (LSB)

-0.4

-0.6

-0.8

-1.0
0 512 1024 1536 2048 2560 3072 3584 4096

DD

.

Digital Code

FIGURE 2-3: Integral Nonlinearity (INL) vs. Code
(Representative Part).

FIGURE 2-5: Integral Nonlinearity (INL) vs. V

1.0

VDD = 2.7V

INL (LSB)

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

= 50ksps

F

SAMPLE

0 512 1024 1536 2048 2560 3072 3584 4096

DD.

Digital Code

FIGURE 2-6: Integral Nonlinearity (INL) vs. Code
(Representative Part, V

= 2.7V).

DD

 1999 Microchip Technology Inc. Preliminary DS21034A-page 5

MCP3202

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, f

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

INL (LSB)

-0.4

-0.6

-0.8

-1.0

-50 -25 0 25 50 75 100

Positive INL

Negative INL

Tem perature ( °C)

FIGURE 2-7: Integral Nonlinearity (INL) vs.
Temperature.

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

DNL (LSB)

-0.4

-0.6

-0.8

-1.0
0 25 50 75 100 125 150

Positive DNL

Negative DNL

Sampl e Rat e (ksps)

SAMPLE =

100ksps, f

INL (LSB)

= 18* f

CLK

1.0

VDD = 2.7V

0.8

F

SAMPLE

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-50 -25 0 25 50 75 100

SAMPLE,TA

= 50ksps

= 25°C

Positive INL

Negative INL

Tem perature ( °C)

FIGURE 2-10: Integral Nonlinearity (INL) vs.
Temperature (V

2.0

1.5

1.0

0.5

0.0

-0.5

DNL (LSB)

-1.0

-1.5

-2.0

= 2.7V).

DD

VDD = 2.7V

Positive DNL

Negativ e DNL

020406080100

Sample Rate (ksps)

FIGURE 2-8: Differential Nonlinearity (DNL) vs.
Sample Rate.

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

DNL (LSB)

-0.4

-0.6

-0.8

-1.0

2.5 3.0 3.5 4.0 4.5 5.0

Positive DNL

Negative DNL

VDD(V)

FIGURE 2-9: Differential Nonlinearity (DNL) vs. V

F

SAMPLE

= 100ksps

DD

FIGURE 2-11: Differential Nonlinearity (DNL) vs.
Sample Rate (V

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

DNL (LSB)

-0.4

-0.6

-0.8

-1.0

2.5 3.0 3.5 4.0 4.5 5.0

.

FIGURE 2-12: Differential Nonlinearity (DNL) vs. V

= 2.7V).

DD

Positive DNL

Negative DNL

VDD(V)

F

SAMPLE

= 50ksps

DD.

DS21034A-page 6 Preliminary  1999 Microchip Technology Inc.