Microchip Technology Inc MCP2510-I-P Datasheet

 1999 Microchip Technology Inc. Preliminary DS21291C-page 1

MCP2510

FEATURES

• Implements Full CAN V2.0A and V2.0B at 1 Mb/s

- 0 - 8 byte message length

- Standard and extended data frames

- Programmable bit rate up to 1 Mb/s

- Support for remote frames

- Two receive buffers with prioritized message
storage

- Six full acceptance filters

- Two full acceptance filter masks

- Three transmit buffers with prioritization and
abort features

- Loop-back mode for self test operation

• Hardware Features

- High Speed SPI Interface
(5 MHz at 4.5V I temp)

- Supports SPI modes 0,0 and 1,1

- Clock out pin with programmable prescaler

- Interrupt output pin with selectable enables

- ‘Buffer full’ output pins configureable as inter­rupt pins for each receive buffer or as general
purpose digital outputs

- ‘Request to Send’ input pins configureable as
control pins to request immediate message
transmission for each transmit buffer or as
general purpose digital inputs

- Low Power Sleep mode

• Low power CMOS technology

- Operates from 3.0V to 5.5V

- 5 mA active current typical

-10 µA standby current typical at 5.5V

• 18-pin PDIP/SOIC and 20-pin TSSOP packages

• Temperature ranges supported:

DESCRIPTION

The Microchip Technology Inc. MCP2510 is a Full Con­troller Area Network (CAN) protocol controller imple­menting CAN specification V2.0 A/B. It supports CAN

1.2, CAN 2.0A, CAN 2.0B Passive, and CAN 2.0B Active
versions of the protocol, and is capable of transmitting
and receiving standard and extended messages. It is
also capable of both acceptance filtering and message
management. It includes three transmit buffers and two
receive buffers that reduce the amount of microcontroller
(MCU) management required. The MCU communication
is implemented via an industry standard Serial Periph­eral Interface (SPI) with data rates up to 5Mb/s.

PACKAGE TYPES

- Industrial (I):

-40°Cto+85°C

- Extended (E):

-40°C to +125°C

18 LEAD PDIP

TXCAN

RXCAN

V

DD

RESET

CS

SO

MCP2510

1

2

3

4

18

17

16

15

SI

SCK

INT

RX0BF

14

13

12

11

RX1BF

10

OSC2

OSC1

CLKOUT

TX2RTS

5

6

7

8

Vss

9

MCP2510

TXCAN

RXCAN

TX0RTS

OSC1

CLKOUT

OSC2

CS

VDD

RESET

SO

SCK
INT

SI

RX0BF
RX1BF

Vss

TX0RTS

TX1RTS

TX1RTS

TX2RTS

18 LEAD SOIC

MCP2510

TXCAN

RXCAN

TX0RTS

OSC1

CLKOUT

OSC2

CS

VDD

RESET

SO

SCK
INT

SI

RX0BF
RX1BF

Vss

11
10

TX1RTS
TX2RTS

20 LEAD TSSOP

NC

NC

1
2
3
4
5
6
7
8
9

18
17
16
15
14
13
12

13
12

1
2
3
4

5
6
7
8
9

20
19
18
17

16
15
14

11

10

Stand-Alone CAN Controller with SPI® Interface

SPI is a registered trademark of Motorola Inc.

MCP2510

DS21291C-page 2 Preliminary  1999 Microchip Technology Inc.

Table of Contents

1.0 Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.0 Can Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.0 Message Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.0 Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.0 Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.0 Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.0 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.0 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.0 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.0 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.0 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12.0 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

13.0 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

On-Line Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Reader Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

MCP2510 Product Identification System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

List Of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

List Of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

List Of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Worldwide Sales and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: [phone]

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit­erature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:

• Fill out and mail in the reader response form in the back of this data sheet.

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We appreciate your assistance in making this a better document.

 1999 Microchip Technology Inc. Preliminary DS21291C-page 3

MCP2510

1.0 DEVICE FUNCTIONALITY

1.1 Overview

The MCP2510 is a stand-alone CAN controller devel­oped to simplify applications that require interfacing
with a CAN bus. A simple block diagram of the
MCP2510 is shown in Figure 1-1. The device consists
of three main blocks:

1. the CAN protocol engine,

2. the control logic and SRAM registers that are
used to configure the device and its operation,
and

3. the SPI protocol block.

A typical system implementation using the device is
shown in Figure 1-2.

The CAN protocol engine handles all functions for
receiving and transmitting messages on the bus. Mes­sages are transmitted by first loading the appropriate
message buffer and control registers. Transmission is
initiated by using control register bits, via the SPI inter­face, or by using the transmit enable pins. Status and
errors can be checked by reading the appropriate reg­isters. Any message detected on the CAN bus is

checked for errors and then matched against the user
defined filters to see if it should be moved into one of
the two receive buffers.

The MCU interfaces to the device via the SPI interface.
Writing to and reading from all registers is done using
standard SPI read and write commands.

Interrupt pins are provided to allow greater system flex­ibility. There is one multi-purpose interrupt pin as well
as specific interrupt pins for each of the receive regis­ters that can be used to indicate when a valid message
has been received and loaded into one of the receive
buffers. Use of the specific interrupt pins is optional,
and the general purpose interrupt pin as well as status
registers (accessed via the SPI interface) can also be
used to determine when a valid message has been
received.

There are also three pins available to initiate immediate
transmission of a message that has been loaded into
one of the three transmit registers. Use of these pins is
optional and initiating message transmission can also
be done by utilizing control registers accessed via the
SPI interface.

Table 1-1 gives a complete list of all of the pins on the
MCP2510.

FIGURE 1-1: Block Diagram

3 TX

Buffers

2 RX Buffers

Message Assembly

6 Acceptance

Filters

SPI

Interface

Logic

SPI
Bus

INT

Buffer

CS
SCK
SI

SO

CAN

Protocol

Engine

RXCAN

TXCAN

Control Logic

RX0BF

RX1BF

TX0RTS

TX1RTS

TX2RTS

MCP2510

DS21291C-page 4 Preliminary  1999 Microchip Technology Inc.

FIGURE 1-2: Typical System Implementation

TABLE 1-1: Pin Descriptions

Name

DIP/
SOIC
Pin #

TSSOP

Pin #

I/O/P
Typ e

Description

TXCAN

11O

Transmit output pin to CAN bus

RXCAN

22 I

Receive input pin from CAN bus

CLKOUT

33O

Clock output pin with programmable prescaler

TX0RTS

44 I

Transmit buffer TXB0 request to send or general purpose digital input. -100K

TX1RTS

55 I

Transmit buffer TXB1 request to send or general purpose digital input. -100K

TX2RTS

67 I

Transmit buffer TXB2 request to send or general purpose digital input. -100K

OSC2

78O

Oscillator output

OSC1

89 I

Oscillator input

V

SS

910P

Ground reference for logic and I/O pins

RX1BF

10 11 O

Receive buffer RXB1 interrupt pin or general purpose digital output

RX0BF

11 12 O

Receive buffer RXB0 interrupt pin or general purpose digital output

INT

12 13 O

Interrupt output pin

SCK

13 14 I

Clock input pin for SPI interface

SI

14 16 I

Data input pin for SPI interface

SO

15 17 O

Data output pin for SPI interface

CS

16 18 I

Chip select input pin for SPI interface

RESET

17 19 I

Active low device reset input

V

DD

18 20 P

Positive supply for logic and I/O pins

NC

— 6,15 —

No internal connection

Note: Type Identification: I=Input; O=Output; P=Power

MCP2510

SPI

MCP2510 MCP2510 MCP2510

INTERFACE

CAN
BUS

MCP2510

CAN

Transceiver

Node

Controller

Main

System

Controller

CAN

Transceiver

CAN

Transceiver

CAN

Tr an s c ei v er

CAN

Transceiver

Node

Controller

Node

Controller

Node

Controller

 1999 Microchip Technology Inc. Preliminary DS21291C-page 5

MCP2510

1.2 Transmit/Receive Buffers

The MCP2510 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a
total of six acceptance filters. Figure 1-3 is a block diagram of these buffers and their connection to the protocol engine.

FIGURE 1-3: CAN Buffers and Protocol Engine Block Diagram

Acceptance Filter

RXF2

R
X
B
1

Identifier

Data Field Data Field

Identifier

Acceptance Mask

RXM1

Acceptance Filter

RXF3

Acceptance Filter

RXF4

Acceptance Filter

RXF5

M
A
B

Acceptance Filter

RXF0

Acceptance Filter

RXF1

R
X
B
0

TXREQ

TXB2

ABTF

MLOA

TXERR

MESSAGE

Message

Queue

Control

Transmit Byte Sequencer

TXREQ

TXB0

ABTF

MLOA

TXERR

MESSAGE

CRC<14:0>

Comparator

Receive<7:0>Transmit<7:0>

Receive

Error

Transmit

Error

Protocol

REC

TEC

ErrPas
BusOff

Finite
State

Machine

Counter

Counter

Shift<14:0>

{Transmit<5:0>, Receive<8:0>}

Transmit

Logic

Bit

Timing

Logic

TX RX

Configuration

Registers

Clock

Generator

PROTOCOL
ENGINE

BUFFERS

TXREQ

TXB1

ABTF

MLOA

TXERR

MESSAGE

A
c
c
e
p
t

Acceptance Mask

RXM0

A
c
c
e
p
t

MCP2510

DS21291C-page 6 Preliminary  1999 Microchip Technology Inc.

1.3 CAN Protocol Engine

The CAN protocol engine combines several functional
blocks, shown in Figure 1-4. These blocks and their
functions are described below.

1.4 Protocol Finite State Machine

The heart of the engine is the Finite State Machine
(FSM). This state machine sequences through mes­sages on a bit by bit basis, changing states as the fields
of the various frame types are transmitted or received.
The FSM is a sequencer controlling the sequential data
stream between the TX/RX Shift Register, the CRC Reg­ister, and the bus line. The FSM also controls the Error
Management Logic (EML) and the parallel data stream
between the TX/RX Shift Registers and the buffers. The
FSM insures that the processes of reception, arbitration,
transmission, and error signaling are performed accord­ing to the CAN protocol. The automatic retransmission of
messages on the bus line is also handled by the FSM.

1.5 Cyclic Redundancy Check

The Cyclic Redundancy Check Register generates the
Cyclic Redundancy Check (CRC) code which is trans­mitted after either the Control Field (for messages with
0 data bytes) or the Data Field, and is used to check the
CRC field of incoming messages.

1.6 Error Management Logic

The Error Management Logic is responsible for the fault
confinement of the CAN device. Its two counters, the
Receive Error Counter (REC) and the Transmit Error
Counter (TEC), are incremented and decremented by
commands from the Bit Stream Processor. According to
the values of the error counters, the CAN controller is set
into the states error-active, error-passive or bus-off.

1.7 Bit Timing Logic

The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive to
dominant bus transition at Start of Frame (hard syn­chronization) and on any further recessive to dominant
bus line transition if the CAN controller itself does not
transmit a dominant bit (resynchronization). The BTL
also provides programmable time segments to com­pensate for the propagation delay time, phase shifts,
and to define the position of the Sample Point within the
bit time. The programming of the BTL depends upon
the baud rate and external physical delay times.

FIGURE 1-4: CAN Protocol Engine Block Diagram

Bit Timing Logic

CRC<14:0>

Comparator

Receive<7:0> Transmit<7:0>

Sample<2:0>

Majority

Decision

StuffReg<5:0>

Comparator

Transmit Logic

Receive

Error Counter

Transmit

Error Counter

Protocol

FSM

Rx

SAM

BusMon

Rec/Trm Addr.

RecData<7:0>

TrmData<7:0>

Shift<14:0>

(Transmit<5:0>, Receive<7:0>)

Tx

REC

TEC

ErrPas

BusOff

Interface to Standard Buffer

 1999 Microchip Technology Inc. Preliminary DS21291C-page 7

MCP2510

2.0 CAN MESSAGE FRAMES

The MCP2510 supports Standard Data Frames,
Extended Data Frames, and Remote Frames (Standard
and Extended) as defined in the CAN 2.0B specification.

2.1 Standard Data Frame

The CAN Standard Data Frame is shown in Figure 2-1.
In common with all other frames, the frame begins with
a Start Of Frame (SOF) bit, which is of the dominant
state, which allows hard synchronization of all nodes.

The SOF is followed by the arbitration field, consisting
of 12 bits; the 11-bit ldentifier and the Remote Trans­mission Request (RTR) bit. The RTR bit is used to dis­tinguish a data frame (RTR bit dominant) from a remote
frame (RTR bit recessive).

Following the arbitration field is the control field, con­sisting of six bits. The first bit of this field is the Identifier
Extension (IDE) bit which must be dominant to specify
a standard frame. The following bit, Reserved Bit Zero
(RB0), is reserved and is defined to be a dominant bit
by the can protocol. the remaining four bits of the con­trol field are the Data Length Code (DLC) which speci­fies the number of bytes of data contained in the
message.

After the control field is the data field, which contains
any data bytes that are being sent, and is of the length
defined by the DLC above (0-8 bytes).

The Cyclic Redundancy Check (CRC) Field follows the
data field and is used to detect transmission errors. The
CRC Field consists of a 15-bit CRC sequence, followed
by the recessive CRC Delimiter bit.

The final field is the two-bit acknowledge field. During
the ACK Slot bit, the transmitting node sends out a
recessive bit. Any node that has received an error free
frame acknowledges the correct reception of the frame
by sending back a dominant bit (regardless of whether
the node is configured to accept that specific message
or not). The recessive acknowledge delimiter com­pletes the acknowledge field and may not be overwrit­ten by a dominant bit.

2.2 Extended Data Frame

In the Extended CAN Data Frame, shown in Figure 2-2,
the SOF bit is followed by the arbitration field which
consists of 32 bits. The first 11 bits are the most signif­icant bits (Base-lD) of the 29-bit identifier. These 11 bits
are followed by the Substitute Remote Request (SRR)
bit which is defined to be recessive. The SRR bit is fol­lowed by the lDE bit which is recessive to denote an
extended CAN frame.

It should be noted that if arbitration remains unresolved
after transmission of the first 11 bits of the identifier,
and one of the nodes involved in the arbitration is send­ing a standard CAN frame (11-bit identifier), then the
standard CAN frame will win arbitration due to the
assertion of a dominant lDE bit. Also, the SRR bit in an
extended CAN frame must be recessive to allow the
assertion of a dominant RTR bit by a node that is send­ing a standard CAN remote frame.

The SRR and lDE bits are followed by the remaining 18
bits of the identifier (Extended lD) and the remote trans­mission request bit.

To enable standard and extended frames to be sent
across a shared network, it is necessary to split the
29-bit extended message identifier into 11-bit (most
significant) and 18-bit (least significant) sections. This
split ensures that the lDE bit can remain at the same bit
position in both standard and extended frames.

Following the arbitration field is the six-bit control field.
the first two bits of this field are reserved and must be
dominant. the remaining four bits of the control field are
the Data Length Code (DLC) which specifies the num­ber of data bytes contained in the message.

The remaining portion of the frame (data field, CRC
field, acknowledge field, end of frame and lntermission)
is constructed in the same way as for a standard data
frame (see Section 2.1).

2.3 Remote Frame

Normally, data transmission is performed on an auton­omous basis by the data source node (e.g. a sensor
sending out a data frame). It is possible, however, for a
destination node to request data from the source. To
accomplish this, the destination node sends a remote
frame with an identifier that matches the identifier of the
required data frame. The appropriate data source node
will then send a data frame in response to the remote
frame request.

There are two differences between a remote frame
(shown in Figure 2-3) and a data frame. First, the RTR
bit is at the recessive state, and second, there is no
data field. In the event of a data frame and a remote
frame with the same identifier being transmitted at the
same time, the data frame wins arbitration due to the
dominant RTR bit following the identifier. In this way, the
node that transmitted the remote frame receives the
desired data immediately.

MCP2510

DS21291C-page 8 Preliminary  1999 Microchip Technology Inc.

2.4 Error Frame

An Error Frame is generated by any node that detects
a bus error. An error frame, shown in Figure 2-4, con­sists of two fields, an error flag field followed by an error
delimiter field. There are two types of error flag fields.
Which type of error flag field is sent depends upon the
error status of the node that detects and generates the
error flag field.

If an error-active node detects a bus error then the
node interrupts transmission of the current message by
generating an active error flag. The active error flag is
composed of six consecutive dominant bits. This bit
sequence actively violates the bit stuffing rule. All other
stations recognize the resulting bit stuffing error and in
turn generate error frames themselves, called error
echo flags. The error flag field, therefore, consists of
between six and twelve consecutive dominant bits
(generated by one or more nodes). The error delimiter
field completes the error frame. After completion of the
error frame, bus activity returns to normal and the inter­rupted node attempts to resend the aborted message.

If an error-passive node detects a bus error then the
node transmits an error-passive flag followed by the
error delimiter field. The error-passive flag consists of
six consecutive recessive bits, and the error frame for
an error-passive node consists of 14 recessive bits.
From this, it follows that unless the bus error is detected
by the node that is actually transmitting, the transmis­sion of an error frame by an error-passive node will not
affect any other node on the network. If the transmitting
node generates an error-passive flag then this will
cause other nodes to generate error frames due to the
resulting bit stuffing violation. After transmission of an
error frame, an error-passive node must wait for six
consecutive recessive bits on the bus before attempt­ing to rejoin bus communications.

The error delimiter consists of eight recessive bits and
allows the bus nodes to restart bus communications
cleanly after an error has occurred.

2.5 Overload Frame

An Overload Frame, shown in Figure 2-5, has the same
format as an active error frame. An overload frame,
however can only be generated during an lnterframe
space. In this way an overload frame can be differenti­ated from an error frame (an error frame is sent during
the transmission of a message). The overload frame
consists of two fields, an overload flag followed by an
overload delimiter. The overload flag consists of six
dominant bits followed by overload flags generated by
other nodes (and, as for an active error flag, giving a
maximum of twelve dominant bits). The overload delim­iter consists of eight recessive bits. An overload frame
can be generated by a node as a result of two condi­tions. First, the node detects a dominant bit during the
interframe space which is an illegal condition. Second,
due to internal conditions the node is not yet able to
start reception of the next message. A node may gen­erate a maximum of two sequential overload frames to
delay the start of the next message.

2.6 Interframe Space

The lnterframe Space separates a preceeding frame
(of any type) from a subsequent data or remote frame.
The interframe space is composed of at least three
recessive bits called the Intermission. This is provided
to allow nodes time for internal processing before the
start of the next message frame. After the intermission,
the bus line remains in the recessive state (bus idle)
until the next transmission starts.

 1999 Microchip Technology Inc. Preliminary DS21291C-page 9

MCP2510

FIGURE 2-1: Standard Data Frame

S

0

0

0

0

1

1 1 1

1 1 1 1

Start of Frame

Data Frame (number of bits = 44 + 8N)

12

Arbitration Field

ID 10

11

ID3

ID0

Identifier

Message

Filtering

Stored in Buffers

RTR

IDE

RB0

DLC3

DLC0

6

4

Control

Field

Data

Length

Code

Reserved Bit

8N (0

≤

N

≤

8)

Data Field

8

8

Stored in Transmit/Receive Buffers

Bit Stuffing

16

CRC Field

15

CRC

7

End of

Frame

CRC Del

Ack Slot Bit

ACK Del

IFS

1

1 1

1

MCP2510

DS21291C-page 10 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-2: Extended Data Frame

0 1 1 0 0 0 1

Start of Frame

Arbitration Field

32

11

ID10

ID3

ID0

IDE

Identifier

Message

Filtering

Stored in Buffers

SRR

EID17

EID0

RTR

RB1

RB0

DLC3

18

DLC0

6

Control

Field

4

Reserved bits

Data

Length

Code

Stored in Transmit/Receive Buffers

8 8

Data Frame (number of bits = 64 + 8N)

8N (0

≤

N

≤

8)

Data Field

1 1 1 1 1 1 1 1

16

CRC Field

15

CRC

CRC Del

Ack Slot Bit

ACK Del

End of

Frame

7

Bit Stuffing

IFS

Extended Identifier

1 1 1

 1999 Microchip Technology Inc. Preliminary DS21291C-page 11

MCP2510

FIGURE 2-3: Remote Data Frame

0 1 1 1 0 0

Start of Frame

Arbitration Field

32

11

ID10

ID3

ID0

IDE

Identifier

Message

Filtering

SRR

EID17

EID0

RTR

RB1

RB0

DLC3

18

DLC0

6

Control

Field

4

Reserved bits

Data

Length

Code

Extended Identifier

1 1 1 1 1 1 1 1 1

16

CRC Field

15

CRC

CRC Del

Ack Slot Bit

ACK Del

End of

Frame

7

Remote Data Frame with Extended Identifier

1 1 1

IFS

MCP2510

DS21291C-page 12 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-4: Error Frame

0 0

0

0

Start of Frame

Interrupted Data Frame

12

Arbitration Field

ID 10

11

ID3

ID0

Identifier

Message

Filtering

RTR

IDE

RB0

DLC3

DLC0

6

4

Control

Field

Data

Length

Code

Reserved Bit

8N (0

≤

N

≤

8)

Data Field

8

8

Bit Stuffing

0 0 0 0 0 0 0

0

0 1 1 1 1 1 1 1 1 0

Data Frame or

Remote Frame

Error Frame

6

Error

Flag

≤

6

Echo

Error

Flag

8

Error

Delimiter

Inter-Frame Space or

Overload Frame

 1999 Microchip Technology Inc. Preliminary DS21291C-page 13

MCP2510

FIGURE 2-5: Overload Frame

0 1

0

0

1

1 1 1 1 1 1 1 1

Start of Frame

Remote Frame (number of bits = 44)

12

Arbitration Field

ID 10

11

ID0

RTR

IDE

RB0

DLC3

DLC0

6

4

Control

Field

16

CRC Field

15

CRC

7

End of

Frame

CRC Del

Ack Slot Bit

ACK Del

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Overload Frame

End of Frame or

Error Delimiter or

Overload Delimiter

6

Overload

Flag

Overload

Delimiter

8

Inter-Frame Space or

Error Frame

MCP2510

DS21291C-page 14 Preliminary  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. Preliminary DS21291C-page 15

MCP2510

3.0 MESSAGE TRANSMISSION

3.1 Transmit Buffers

The MCP2510 implements three Transmit Buffers. Each
of these buffers occupies 14 bytes of SRAM and are
mapped into the device memory maps. The first byte,
TXB

NCTRL, is a control register associated with the mes-

sage buffer. The information in this register determines
the conditions under which the message will be transmit­ted and indicates the status of the message transmission.
(see Register 3-2). Five bytes are used to hold the stan­dard and extended identifiers and other message arbitra­tion information (see Register 3-3 through Register 3-8).
The last eight bytes are for the eight possible data bytes
of the message to be transmitted (see Register 3-8).

For the MCU to have write access to the message buffer,
the TXB

NCTRL.TXREQ bit must be clear, indicating that

the message buffer is clear of any pending message to be
transmitted. At a minimum, the TXB

NSIDH, TXBNSIDL,

and TXB

NDLC registers must be loaded. If data bytes are

present in the message, the TXB

NDm registers must also

be loaded. If the message is to use extended identifiers,
the TXBNEIDm registers must also be loaded and the
TXB

NSIDL.EXIDE bit set.

Prior to sending the message, the MCU must initialize
the CANINTE.TXI

NE bit to enable or disable the gener-

ation of an interrupt when the message is sent. The
MCU must also initialize the TXB

NCTRL.TXP priority

bits (see Section 3.2).

3.2 Transmit Priority

Transmit priority is a prioritization, within the MCP2510,
of the pending transmittable messages. This is indepen­dent from, and not necessarily related to, any prioritiza­tion implicit in the message arbitration scheme built into
the CAN protocol. Prior to sending the SOF, the priority
of all buffers that are queued for transmission is com­pared. The transmit buffer with the highest priority will be
sent first. For example, if transmit buffer 0 has a higher
priority setting than transmit buffer 1, buffer 0 will be sent
first. If two buffers have the same priority setting, the
buffer with the highest buffer number will be sent first. For
example, if transmit buffer 1 has the same priority setting
as transmit buffer 0, buffer 1 will be sent first. There are
four levels of transmit priority. If TXB

NCTRL.TXP<1:0>

for a particular message buffer is set to 11, that buffer
has the highest possible priority. If TXB

NC-

TRL.TXP<1:0> for a particular message buffer is 00, that
buffer has the lowest possible priority.

3.3 Initiating Transmission

To initiate message transmission the TXBNCTRL.TXREQ
bit must be set for each buffer to be transmitted. This can
be done by writing to the register via the SPI interface or
by setting the TX

NRTS pin low for the particular transmit

buffer(s) that are to be transmitted. If transmission is initi­ated via the SPI interface, the TXREQ bit can be set at the
same time as the TXP priority bits.

When TXB

NCTRL.TXREQ is set, the TXBNCTRL.ABTF,

TXB

NCTRL.MLOA and TXBNCTRL.TXERR bits will be

cleared.

Setting the TXB

NCTRL.TXREQ bit does not initiate a

message transmission, it merely flags a message
buffer as ready for transmission. Transmission will start
when the device detects that the bus is available. The
device will then begin transmission of the highest prior­ity message that is ready.

When the transmission has completed successfully the
TXB

NCTRL.TXREQ bit will be cleared, the CAN-

INTF.TX

NIF bit will be set, and an interrupt will be gen-

erated if the CANINTE.TX

NIE bit is set.

If the message transmission fails, the TXB

NCTRL.TXREQ

will remain set indicating that the message is still pending
for transmission and one of the following condition flags
will be set. If the message started to transmit but encoun­tered an error condition, the TXB

NCTRL. TXERR and the

CANINTF.MERRF bits will be set and an interrupt will be
generated on the INT

pin if the CANINTE.MERRE bit is

set. If the message lost arbitration the TXB

NCTRL.MLOA

bit will be set.

3.4 TXnRTS Pins

The TXNRTS Pins are input pins that can be configured
as request-to-send inputs, which provides a secondary
means of initiating the transmission of a message from
any of the transmit buffers, or as standard digital inputs.
Configuration and control of these pins is accomplished
using the TXRTSCTRL register (see Register 3-2). The
TXRTSCTRL register can only be modified when the
MCP2510 is in configuration mode (see Section 9.0). If
configured to operate as a request to send pin, the pin
is mapped into the respective TXB

NCTRL.TXREQ bit

for the transmit buffer. The TXREQ bit is latched by the
falling edge of the TX

NRTS pin. The TXNRTS pins are

designed to allow them to be tied directly to the RX

NBF

pins to automatically initiate a message transmission
when the RX

NBF pin goes low. The TXNRTS pins have

internal pullup resistors of 100K ohms (nominal).

3.5 Aborting Transmission

The MCU can request to abort a message in a specific
message buffer by clearing the associated TXBnC­TRL.TXREQ bit. Also, all pending messages can be
requested to be aborted by setting the CAN­CTRL.ABAT bit. If the CANCTRL.ABAT bit is set to
abort all pending messages, the user MUST reset this
bit (typically after the user verifies that all TXREQ bits
have been cleared) to continue trasmit messages. The
CANCTRL.ABTF flag will only be set if the abort was
requested via the CANCTRL.ABAT bit. Aborting a mes­sage by resetting the TXREQ bit does NOT cause the
ATBF bit to be set.

Only messages that have not already begun to be
transmitted can be aborted. Once a message has
begun transmission, it will not be possible for the user
to reset the TXBnCTRL.TXREQ bit. After transmission

MCP2510

DS21291C-page 16 Preliminary  1999 Microchip Technology Inc.

of a message has begun, if an error occurs on the bus
or if the message loses arbitration, the message will be
retransmitted regardless of a request to abort.

FIGURE 3-1: Transmit Message Flowchart

Start

Is

CAN Bus available

to start transmission

No

Examine TXBNCTRL.TXP <1:0> to

Are any

TXB

NCTRL.TXREQ

?

bits = 1

The message transmission
sequence begins when the
device determines that the
TXB

NCTRL.TXREQ for any of

the transmit registers has b een
set.

Clear:
TXB

NCTRL.ABTF

TXB

NCTRL.MLOA

TXB

NCTRL.TXERR

Ye s

?

is

TXBNCTRL.TXREQ=0

CANCTRL.ABAT=1

Clearing the TxBNCTRL.TXREQ
bit while it is set, or setting the
CANCTRL.ABAT bit before the
message has star ted transmission
will abort the message.

No

Transmit Message

Was

Message Transmitted

Successfully?

No

Ye s

Set TxBNCTRL.TXREQ=0

CANINTE.TXnIE=1?

Generate

Interrupt

Ye s

Ye s

Ye s

Set

Did

a message error

occur?

Was

Arbitration lost during

transmission?

Set

TxBNCTRL.TXERR=1

Ye s

No

No

Determine Highest Priority Message

No

?

Set

TxBNCTRL.MLOA=1

The CANINTE.TXnIE bit
determines if an interrupt
should be generated when
a message is successfully
transmitted.

GOTO START

CANTINF.TX

NIF=1

Ye s

or

No

 1999 Microchip Technology Inc. Preliminary DS21291C-page 17

MCP2510

REGISTER 3-1: TXBNCTRL Transmit Buffer N Control Register (ADDRESS: 30h, 40h, 50h)

U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0

— ABTF MLOA TXERR TXREQ — TXP1 TXP0

R = Readable bit
W = Writable bit
C = Bit can be cleared by

MCU but not set

U = Unimplemented -

reads as ‘0’

- n = Value at POR reset

bit 7 bit 0

bit 7: Unimplemented: Reads as ‘0’

bit 6: ABTF: Message Aborted Flag

1 = Message was aborted

0 = Message completed transmission successfully

bit 5: MLOA: Message Lost Arbitration

1 = Message lost arbitration while being sent

0 = Message did not lose arbitration while being sent

bit 4: TXERR: Transmission Error Detected

1 = A bus error occurred while the message was being transmitted

0 = No bus error occurred while the message was being transmitted

bit 3: TXREQ: Message Transmit Request

1 = Buffer is currently pending transmission

(MCU sets this bit to request message be transmitted - bit is automatically cleared when

the message is sent)

0 = Buffer is not currently pending transmission

(MCU can clear this bit to request a message abort)

bit 2: Unimplemented: Reads as ‘0’

bit 1-0: TXP<1:0>: Transmit Buffer Priority

11 = Highest Message Priority

10 = High Intermediate Message Priority

01 = Low Intermediate Message Priority

00 = Lowest Message Priority

MCP2510

DS21291C-page 18 Preliminary  1999 Microchip Technology Inc.

REGISTER 3-2: TXRTSCTRL - TXNRTS Pin Control and Status Register (ADDRESS: 0Dh)

REGISTER 3-3: TXB

NSIDH - Transmit Buffer N Standard Identifier High (ADDRESS: 31h, 41h, 51h)

U-0 U-0 R-x R-x R-x R/W-0 R/W-0 R/W-0

— — B2RTS B1RTS B0RTS B2RTSM B1RTSM B0RTSM

R = Readable bit
W = Writable bit
C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7 bit 0

bit 7: Unimplemented: Reads as ‘0’

bit 6: Unimplemented: Reads as ‘0’

bit 5: B2RTS: TX2RTS

Pin State

- Reads state of TX2RTS

pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

bit 4: B1RTS: TX1RTX

Pin State

- Reads state of TX1RTS

pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

bit 3: B0RTS: TX0RTS

Pin State

- Reads state of TX0RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

bit 2: B2RTSM: TX2RTS Pin Mode

1 = Pin is used to request message transmission of TXB2 buffer (on falling edge)
0 = Digital input

bit 1: B1RTSM: TX1RTS Pin Mode

1 = Pin is used to request message transmission of TXB1 buffer (on falling edge)
0 = Digital input

bit 0: B0RTSM: TX0RTS Pin Mode

1 = Pin is used to request message transmission of TXB0 buffer (on falling edge)
0 = Digital input

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3

R = Readable bit
W = Writable bit
C = Bit can be cleared by

MCU but not set

U = Unimplemented -

reads as ‘0’

- n = Value at POR reset

bit 7 bit 0

bit 7-0: SID<10:3>: Standard Identifier Bits <10:3>

 1999 Microchip Technology Inc. Preliminary DS21291C-page 19

MCP2510

REGISTER 3-4: TXBNSIDL - Transmit Buffer N Standard Identifier Low (ADDRESS: 32h, 42h, 52h)

REGISTER 3-5: TXB

NEID8 - Transmit Buffer N Extended Identifier High (ADDRESS: 33h, 43h, 53h)

REGISTER 3-6: TXB

NEID0 - Transmit Buffer N Extended Identifier LOW (ADDRESS: 34h, 44h, 54h)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID2 SID1 SID0

— EXIDE — EID17 EID16

R = Readable bit
W = Writable bit
C = Bit can be cleared by

MCU but not set

U = Unimplemented -

reads as ‘0’

- n = Value at POR reset

bit 7 bit 0

bit 7-5: SID<2:0>: Standard Identifier Bits <2:0>

bit 4: Unimplemented: Reads as '0’

bit 3: EXIDE: Extended Identifier Enable

1 = Message will transmit extended identifier

0 = Message will transmit standard identifier

bit 2: Unimplemented: Reads as '0’

bit 1-0: EID<17:16>: Extended Identifier Bits <17:16>

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

R = Readable bit
W = Writable bit
C = Bit can be cleared by

MCU but not set

U = Unimplemented -

reads as ‘0’

- n = Value at POR reset

bit 7 bit 0

bit 7-0: EID<15:8>: Extended Identifier Bits <15:8>

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

R = Readable bit
W = Writable bit
C = Bit can be cleared by

MCU but not set

U = Unimplemented -

reads as ‘0’

- n = Value at POR reset

bit 7 bit 0

bit 7-0: EID<7:0>: Extended Identifier Bits <7:0>

MCP2510

DS21291C-page 20 Preliminary  1999 Microchip Technology Inc.

REGISTER 3-7: TXBNDLC - Transmit Buffer N Data Length Code (ADDRESS: 35h, 45h, 55h)

REGISTER 3-8: TXBNDM - Transmit Buffer N Data Field Byte m (ADDRESS: 36h-3Dh, 46h-4Dh, 56h-5Dh)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— RTR — — DLC3 DLC2 DLC1 DLC0

R = Readable bit
W = Writable bit
C = Bit can be cleared by

MCU but not set

U = Unimplemented -

reads as ‘0’

- n = Value at POR reset

bit 7 bit 0

bit 7: Unimplemented: Reads as ‘0’

bit 6: RTR: Remote Transmission Request Bit

1 = Transmitted Message will be a Remote Transmit Request
0 = Transmitted Message will be a Data Frame

bit 5-4: Unimplemented: Reads as ‘0’

bit 3-0: DLC<3:0>: Data Length Code

Sets the number of data bytes to be transmitted (0 to 8 bytes)
NOTE: It is possible to set the DLC to a value greater than 8, however only 8 bytes are transmitted

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

TXB

NDm7 TXBNDm6 TXBNDm5 TXBNDm4 TXBNDm3 TXBNDm2 TXBNDm1 TXBNDm0

R = Readable bit
W = Writable bit
C = Bit can be cleared

by
MCU but not set

U = Unimplemented

- reads as ‘0’

- n = Value at POR
reset

bit 7 bit 0

bit 7-0: TXBNDM7:TXBNDM0: Transmit Buffer N Data Field Byte m

 1999 Microchip Technology Inc. Preliminary DS21291C-page 21

MCP2510

4.0 MESSAGE RECEPTION

4.1 Receive Message Buffering

The MCP2510 includes two full receive buffers with
multiple acceptance filters for each. There is also a
separate Message Assembly Buffer (MAB) which acts
as a third receive buffer (see Figure 4-1).

4.2 Receive Buffers

Of the three Receive Buffers, the MAB is always com­mitted to receiving the next message from the bus. The
remaining two receive buffers are called RXB0 and
RXB1 and can receive a complete message from the
protocol engine. The MCU can access one buffer while
the other buffer is available for message reception or
holding a previously received message.

The MAB assembles all messages received. These
messages will be transferred to the RXB

N buffers (See

Register 4-4 to Register 4-9) only if the acceptance fil­ter criteria are met.

When a message is moved into either of the receive
buffers the appropriate CANINTF.RX

NIF bit is set. This

bit must be cleared by the MCU, when it has completed
processing the message in the buffer, in order to allow
a new message to be received into the buffer. This bit
provides a positive lockout to ensure that the MCU has
finished with the message before the MCP2510
attempts to load a new message into the receive buffer.
If the CANINTE.RX

NIE bit is set an interrupt will be gen-

erated on the INT

pin to indicate that a valid message

has been received.

4.3 Receive Priority

RXB0 is the higher priority buffer and has two message
acceptance filters associated with it. RXB1 is the lower
priority buffer and has four acceptance filters associ­ated with it. The lower number of acceptance filters
makes the match on RXB0 more restrictive and implies
a higher priority for that buffer. Additionally, the
RXB0CTRL register can be configured such that if
RXB0 contains a valid message, and another valid
message is received, an overflow error will not occur
and the new message will be moved into RXB1 regard­less of the acceptance criteria of RXB1. There are also
two programmable acceptance filter masks available,
one for each receive buffer (see Section 4.5).

When a message is received, bits <3:0> of the RXB

NCTRL

Register will indicate the acceptance filter number that
enabled reception, and whether the received message is a
remote transfer request.

The RXB

NCTRL.RXM bits set special receive modes.

Normally, these bits are set to 00 to enable reception of
all valid messages as determined by the appropriate
acceptance filters. In this case, the determination of
whether or not to receive standard or extended mes­sages is determined by the RFX

NSIDL.EXIDE bit in the

acceptance filter register. If the RXB

NCTRL.RXM bits

are set to 01 or 10, the receiver will accept only mes­sages with standard or extended identifiers respec­tively. If an acceptance filter has the RFX

NSIDL.EXIDE

bit set such that it does not correspond with the
RXB

NCTRL.RXM mode, that acceptance filter is ren-

dered useless. These two modes of RXB

NCTRL.RXM

bits can be used in systems where it is known that only
standard or extended messages will be on the bus. If
the RXB

NCTRL.RXM bits are set to 11, the buffer will

receive all messages regardless of the values of the
acceptance filters. Also, if a message has an error
before the end of frame, that portion of the message
assembled in the MAB before the error frame will be
loaded into the buffer. This mode has some value in
debugging a CAN system and would not be used in an
actual system environment.

4.4 RX0BF and RX1BF Pins

In addition to the INT pin which provides an interrupt
signal to the MCU for many different conditions, the
receive buffer full pins (RX0BF

and RX1BF) can be
used to indicate that a valid message has been loaded
into RXB0 or RXB1, respectively.

The RXB

NBF full pins can be configured to act as buffer

full interrupt pins or as standard digital outputs. Config­uration and status of these pins is available via the
BFPCTRL register (Register 4-3). When set to operate
in interrupt mode (by setting BFPCTRL.BxBFE and
BFPCTRL.BxBFM bits to a 1), these pins are active low
and are mapped to the CANINTF.RX

NIF bit for each

receive buffer. When this bit goes high for one of the
receive buffers, indicating that a valid message has
been loaded into the buffer, the corresponding RX

NBF

pin will go low. When the CANINTF.RXNIF bit is cleared
by the MCU, then the corresponding interrupt pin will go
to the logic high state until the next message is loaded
into the receive buffer.

When used as digital outputs the BFPCTRL.BxBFM
and BFPCTRL.BxBFE bits must be set to a ‘1’ for the
associated buffer. In this mode the state of the pin is
controlled by the BFPCTRL.BxBFS bits. Writting a ‘1’
to the BxBFS bit will cause a high level to be driven on
the assicated buffer full pin, and a ‘0’ will cause the pin
to drive low. When using the pins in this mode the state
of the pin should be modified only by using the Bit Mod­ify SPI command to prevent glitches from occuring on
either of the buffer full pins.

Note: The entire contents of the MAB is moved into

the receive buffer once a message is
accepted. This means that regardless of the
type of identifier (standard or extended) and
the number of data bytes received, the entire
receive buffer is overwritten with the MAB
contents. Therefore the contents of all regis­ters in the buffer must be assumed to have
been modified when any message is
received.

MCP2510

DS21291C-page 22 Preliminary  1999 Microchip Technology Inc.

FIGURE 4-1: Receive Buffer Block Diagram

Acceptance Mask

RXM1

Acceptance Filter

RXF2

Acceptance Filter

RXF3

Acceptance Filter

RXF4

Acceptance Filter

RXF5

Acceptance Mask

RXM0

Acceptance Filter

RXF0

Acceptance Filter

RXF1

Identifier

Data Field Data Field

Identifier

A
c
c
e
p

t

A

c
c
e
p

t

R
X
B

0

R
X
B
1

M

A
B

 1999 Microchip Technology Inc. Preliminary DS21291C-page 23

MCP2510

FIGURE 4-2: Message Reception Flowchart

Set RXBF0

Start

Detect

Start of

Message

?

Val id
Message
Received

?

Generate

Error

Message

Identifier meets

a filter criteria

?

Is

CANINTF.RX0IF=0

?

Go to Start

Move message into RXB0

Set RXB0CTRL.FILHIT <2:0>

Is

CANINTF.RX1IF = 0

?

Move message into RXB1

Set CANINTF.RX1IF=1

Yes, meets criteria

for RXBO

No

Generate

Interrupt on INT

Ye s

Ye s

No

No

Ye s

Ye s

No

No

Ye s

Ye s

Fram e

The CANINTF.RX

NIF bit

determines if the receive
register is empty and able
to accept a new message

No

Ye s

No

Begin Loading Message into

Message Assembly Buffer (MAB)

according to which filter criteria

was met

Set RXB0CTRL.FILHIT <0>

according to which filter criteria

Set CANSTAT <3:0> accord­ing to which receive buffer
the message was loaded into

Is

RXB0CTRL.BUKT=1

?

The RXB0CTRL.BUKT
bit determines if RXB0
can roll over into RXB1

Generate Overflow Error:

Set EFLG.RX1OVR

Is

CANINTE.ERRIE=1

?

No

Go to Start

Ye s

No

Are

BFPCTRL.B0BFM=1

?

BF1CTRL.B0BFE=1

and

Pin = 0

No

Set RXBF1

Pin = 0

No

Ye s

Ye s

CANINTE.RX0IE=1?

CANINTE.RX1IE=1?

RXB1

RXB0

Yes, meets criteria

for RXB1

Set EFLG.RX0OVR

Generate Overflow Error:

Set CANINTF.RX0IF=1

Are

BFPCTRL. B1BFM=1

?

BF1CTRL.B1BFE=1

and