Microchip Technology Inc 93C86T-I-SN, 93C86T-I-P, 93C86T-E-SN, 93C86T-SN, 93C86T-P Datasheet



1996 Microchip Technology Inc.

Preliminary

DS21132C-page 1

FEATURES

• Single 5.0V supply

• Low power CMOS technology

- 1 mA active current typical

• ORG pin selectable memory configuration
1024 x 8- or 512 x 16-bit organization (93C76)
2048 x 8- or 1024 x 16-bit organization (93C86)

• Self-timed ERASE and WRITE cycles
(including auto-erase)

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during ERASE/WRITE cycles

• Sequential READ function

• 10,000,000 ERASE/WRITE cycles guaranteed

• Data retention > 200 years

• 8-pin PDIP/SOIC package

• Temperature ranges supported

DESCRIPTION

The Microchip Technology Inc. 93C76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
non-volatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93C76/86 is available in standard 8-pin DIP and 8­pin surface mount SOIC packages.

- Commercial (C): 0 ° C to +70 ° C

- Industrial -40 ° C to +85 ° C

- Automotive (E) -40 ° C to +125 ° C

P ACKA GE TYPES

BLOCK DIAGRAM

SOIC Package

DIP Package

CS

CLK

DI

DO

V

SS

PE

V

CC

ORG

CS

CLK

DI

DO

V

CC

PE
ORG
V

SS

93C76/86

93C76/86

1
2
3

4

8
7
6

5

1
2
3

4

8
7
6

5

DO

CS

CLK

VCCV

SS

Memory

Array

Address

Decoder

Data

Register

Counter

Address

Output

Buffer

Mode

Decode

Logic

Generator

Clock

DI

PE

93C76/86

8K/16K 5.0V Microwire



Serial EEPROM

Microwire is a registered trademark of National Semiconductor Incorporated.

93C76/86

DS21132C-page 2

Preliminary



1996 Microchip Technology Inc.

1.0 ELECTRICAL
CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

...................................................................................7.0V

All inputs and outputs w.r.t. V

SS

...............-0.6V to Vcc +1.0V

Storage temperature..................................... -65˚C to +150˚C

Ambient temp. with power applied................. -65˚C to +125˚C

Soldering temperature of leads (10 seconds)............. +300˚C

ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability

TABLE 1-1: PIN FUNCTION TABLE

Name Function

CS

CLK

DI

DO

V

SS

ORG

PE

V

CC

Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Program Enable
Power Supply

1.2 A

C Test Conditions

AC Waveform:

V

LO

= 2.0V

V

HI

= Vcc - 0.2V

(Note 1)

V

HI

= 4.0V for

(Note 2)

Timing Measurement Reference Level

Input 0.5 V

CC

Output 0.5 V

CC

Note 1: For V

CC

≤

4.0V

2: For V

CC

> 4.0V

TABLE 1-2: DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

= +4.5V to +5.5V
Commercial (C): Tamb = 0 ° C to -40 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

Parameter Symbol Min. Max. Units Conditions

High level input voltage V

IH1

2.0 V

CC

+1 V —

Low level input voltage V

IL1

-0.3 0.8 V —

Low level output voltage V

OL1

— 0.4 V I

OL

= 2.1 mA; V

CC

= 4.5V

V

OL2

— 0.2 V I

OL

=100 µ A; V

CC

= 4.5V

High level output voltage V

OH1

2.4 — V I

OH

= -400 µ A; V

CC

= 4.5V

V

OH2

V

CC

-0.2 — V I

OH

= -100 µ A; V

CC

= 4.5V.

Input leakage current I

LI

-10 10

µ

AV

IN

= 0.1V to V

CC

Output leakage current I

LO

-10 10

µ

AV

OUT

= 0.1V to V

CC

Pin capacitance
(all inputs/outputs)

C

INT

—7pF

(Note Note:)
Tamb = +25˚C, F

CLK

= 1 MHz

Operating current I

CC

write — 3 mA F

CLK

= 2 MHz; V

CC

= 5.5V

I

CC

read — 1.5 mA F

CLK

= 2 MHz; V

CC

= 5.5V

Standby current I

CCS

— 100

µ

A CLK = CS = 0V; V

CC

= 5.5V

Note: This parameter is periodically sampled and not 100% tested.



1996 Microchip Technology Inc.

Preliminary

DS21132C-page 3

93C76/86

TABLE 1-3: AC CHARACTERISTICS

TABLE 1-4: INSTRUCTION SET FOR 93C76: ORG=1 (X16 ORGANIZATION)

TABLE 1-5: INSTRUCTION SET FOR 93C76: ORG=0 (X8 ORGANIZATION)

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

= +4.5V to +5.5V
Commercial (C): Tamb = 0 ° C to -40 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

Parameter Symbol Min. Max. Units Conditions

Clock frequency F

CLK

— 2 MHz Vcc ≥ 4.5V

Clock high time T

CKH

300 — ns

Clock low time T

CKL

200 — ns

Chip select setup time T

CSS

50 — ns Relative to CLK

Chip select hold time T

CSH

0—ns

Chip select low time T

CSL

250 — ns Relative to CLK

Data input setup time T

DIS

100 — ns Relative to CLK

Data input hold time T

DIH

100 — ns Relative to CLK

Data output delay time T

PD

— 400 ns C

L

= 100 pF

Data output disable time T

CZ

— 100 ns

(Note 1)

Status valid time T

SV

— 500 ns C

L

= 100 pF

Program cycle time T

WC

—10ms

ERASE/WRITE mode (Note 2)

T

EC

— 15 ms ERAL mode

T

WL

— 30 ms WRAL mode

Endurance — 10M — cycles 25 ° C, V

CC

= 5.0V, Block Mode

(Note 3)

Note 1: This parameter is periodically sampled and not 100% tested.

2: Typical program cycle is 4 ms per word.
3: This parameter is not tested but guaranteed b y characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 29
EWEN 1 00 1 1 X X X X X X X X — High-Z 13
ERASE 1 11 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 13
ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 13
WRITE 1 01 X A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29
WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29
EWDS 1 00 0 0 X X X X X X X X — High-Z 13

Instruction SB Opcode Address Data In Data Out

Req. CLK

Cycles

READ 1 10 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 22
EWEN 1 00 1 1 X X X X X X X X X — High-Z 14
ERASE 1 11 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 14
ERAL 1 00 1 0 X X X X X X X X X — (RDY/BSY) 14
WRITE 1 01 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22
WRAL 1 00 0 1 X X X X X X X X X D7 - D0 (RDY/BSY) 22
EWDS 1 00 0 0 X X X X X X X X X — High-Z 14

93C76/86

DS21132C-page 4

Preliminary



1996 Microchip Technology Inc.

TABLE 1-6: INSTRUCTION SET FOR 93C86: ORG=1 (X16 ORGANIZATION)

TABLE 1-7: INSTRUCTION SET FOR 93C86: ORG=0 (X8 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 29
EWEN 1 00 1 1 X X X X X X X X — High-Z 13
ERASE 1 11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 13
ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 13
WRITE 1 01 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29
WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29
EWDS 1 00 0 0 X X X X X X X X — High-Z 13

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 22
EWEN 1 00 1 1 X X X X X X X X X — High-Z 14
ERASE 1 11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 14
ERAL 1 00 1 0 X X X X X X X X X — (RDY/BSY) 14
WRITE 1 01 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22
WRAL 1 00 0 1 X X X X X X X X X D7 - D0 (RDY/BSY) 22
EWDS 1 00 0 0 X X X X X X X X X — High-Z 14

 1996 Microchip Technology Inc. Preliminary DS21132C-page 5

93C76/86

2.0 PRINCIPLES OF OPERATION

When the ORG pin is connected to VCC, the x16 orga-
nization is selected. When it is connected to ground, the
x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the READY/B

USY status dur-

ing a programming operation. The READY/B

USY sta­tus can be verified during an Erase/Write operation by
polling the DO pin; DO low indicates that programming
is still in progress, while DO high indicates the device is
ready. The DO will enter the high impedance state on
the falling edge of the CS.

2.1 START Condition

The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.

Before a START condition is detected, CS , CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper­ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.

An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.

After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.

2.2 DI/DO

It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “b us conflict” to occur during the “dumm y zero” that
precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0, the
higher the voltage at the Data Out pin.

2.3 Erase/Write Enable and Disable

(EWEN, EWDS)

The 93C76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be pre­ceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V

CC is removed from the device. To protect against

accidental data disturb, the EWDS instruction can be
used to disable all Erase/Write functions and should fol-

low all programming operations. Execution of a READ
instruction is independent of both the EWEN and
EWDS instructions.

2.4 Data Protection

During power-up, all programming modes of operation
are inhibited until V

CC has reached a level greater than

1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V

CC has fallen below 1.4V.

The EWEN and EWDS commands give additional pro­tection against accidentally programming during nor­mal operation.

After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.

93C76/86

DS21132C-page 6 Preliminary  1996 Microchip Technology Inc.

3.0 DEVICE OPERATION

3.1 READ

The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable after
the specified time delay (T

PD). Sequential read is pos-

sible when CS is held high and clock transitions con­tinue. The memory address pointer will automatically
increment and output data sequentially.

3.2 ERASE

The ERASE instruction forces all data bits of the spec­ified address to the logical “1” state . The self-timed pro­gramming cycle is initiated on the rising edge of CLK as
the last address bit (A0) is clocked in. At this point, the
CLK, CS, and DI inputs become don’t cares.

The DO pin indicates the READY/B

USY status of the

device if the CS is high. The READY/B

USY status will
be displayed on the DO pin until the next star t bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO pin
to enter the high impedance state. DO at logical “0” indi­cates that programming is still in progress. DO at logical
“1” indicates that the register at the specified address
has been erased and the device is ready for another
instruction.

The ERASE cycle takes 3 ms per word (Typical).

3.3 WRITE

The WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the ris­ing edge of CLK as the last data bit (D0) is clocked in.
At this point, the CLK, CS, and DI inputs become don’t
cares.

The DO pin indicates the READY/B

USY status of the

device if the CS is high. The READY/B

USY status will
be displayed on the DO pin until the next star t bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO pin
to enter the high impedance state. DO at logical “0” indi­cates that programming is still in progress. DO at logical
“1” indicates that the register at the specified address
has been written and the device is ready for another
instruction.

The WRITE cycle takes 3 ms per word (Typical).

3.4 Erase All (ERAL)

The ERAL instruction will erase the entire memory
array to the logical “1” state . The ERAL cycle is identical
to the ERASE cycle except for the diff erent opcode. The
ERAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that

the least significant 8 or 9 address bits are don’t care
bits, depending on selection of x16 or x8 mode. Clock­ing of the CLK pin is not necessary after the device has
entered the self clocking mode. The ERAL instruction is
guaranteed at Vcc = +4.5V to +5.5V.

The DO pin indicates the READY/B

USY status of the

device if the CS is high. The READY/B

USY status will
be displayed on the DO pin until the next star t bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO pin
to enter the high impedance state. DO at logical “0” indi­cates that programming is still in progress. DO at logical
“1” indicates that the entire device has been er ased and
is ready for another instruction.

The ERAL cycle takes 15 ms maximum (8 ms typical).

3.5 Write All (WRAL)

The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences on the
rising edge of the last address bit (A0). Note that the
least significant 8 or 9 address bits are don’t cares,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL instruction but the chip must be in the EWEN sta­tus. The WRAL instruction is guaranteed at Vcc = +4.5V
to +5.5V.

The DO pin indicates the READY/B

USY status of the

device if the CS is high. The READY/B

USY status will
be displayed on the DO pin until the next star t bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO pin
to enter the high impedance state. DO at logical “0” indi­cates that programming is still in progress. DO at logical
“1” indicates that the entire device has been written and
is ready for another instruction.

The WRAL cycle takes 30 ms maximum (16 ms typical).

 1996 Microchip Technology Inc. Preliminary DS21132C-page 7

93C76/86

FIGURE 3-1: SYNCHRONOUS DATA TIMING

FIGURE 3-2: READ

FIGURE 3-3: EWEN

FIGURE 3-4: EWDS

The memory automatically cycles to the next register.

VIH

VIL

VIH

VIL

VIH

VOH
VOL
VOH
VOL

VIL

TSV

TDIS

TPD

TDIH

TCSS TCKH TCKL

TPD

TCSH

TCZ

TCZ

CS

CLK

DI

DO

DO

(Program)

(Read)

ST ATUS VALID

110A

N

A

0

D

N

D

N

D

0

D

0

...

...

...

HIGH IMPEDANCE

T

CSL

CS

CLK

DI

DO

0

EWEN

CS

CLK

DI

11100

T

CSL

XX

...

ORG=VCC, 8 X’s
ORG=V

SS

, 9 X’s

10000X X

...

CS

CLK

DI

TCSL

ORG=V

CC

, 8 X’s

ORG=V

SS

, 9 X’S

93C76/86

DS21132C-page 8 Preliminary  1996 Microchip Technology Inc.

FIGURE 3-5: WRITE

FIGURE 3-6: WRAL

FIGURE 3-7: ERASE

101A

N

A

0

...

D

N

...

D

0

TWC

READY

BUSY

HIGH IMPEDANCE

CS

CLK

DI

DO

STANDBY

TCZ

Guarantee at Vcc = +4.5V to +5.5V.

10001X

...

XD

N

...

D

0

BUSY

READY

HIGH IMPEDANCE

STANDBY

CS

CLK

DI

DO

ORG=VCC, 8 X’s
ORG=V

SS

, 9 X’s

TWL

TCZ

111A

N

...

A

0

TCZ

HIGH IMPEDANCE

CS

CLK

DI

DO

STANDBY

READY

BUSY

TWC

...

 1996 Microchip Technology Inc. Preliminary DS21132C-page 9

93C76/86

FIGURE 3-8: ERAL

Guarantee at VCC = +4.5V to +5.5V.

ORG=VCC, 8 X’s
ORG=V

SS

, 9 X’s

10010XX

...

CS

CLK

DI

DO

T

EC

TCZ

HIGH IMPEDANCE

B

USY READY

STANDBY

4.0 PIN DESCRIPTIONS

4.1 Chip Select (CS)

A HIGH level selects the de vice. A LOW lev el deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated will be
completed, regardless of the CS input signal. If CS is
brought LOW during a program cycle, the de vice will go
into standby mode as soon as the programming cycle
is completed.

CS must be LOW for 250 ns minimum (T

CSL) between

consecutive instructions. If CS is LOW, the internal con­trol logic is held in a RESET status.

4.2 Serial Clock (CLK)

The Serial Clock is used to synchronize the communi­cation between a master device and the 93C76/86.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.

CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW lev el) and can be continued
anytime with respect to clock HIGH time (T

CKH) and

clock LOW time (T

CKL). This gives the controlling mas-

ter freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is LO W (de vice deselected).

If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).

CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.

After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH tr ansitions of
CLK) must be provided. These clock cycles are
required to clock in all opcode, address, and data bits
before an instruction is executed (see Table 1-4 through

Table 1-7 for more details). CLK and DI then become
don't care inputs waiting for a new start condition to be
detected.

4.3 Data In (DI)

Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.

4.4 Data Out (DO)

Data Out is used in the READ mode to output data syn­chronously with the CLK input (T

PD after the positive

edge of CLK).
This pin also provides READ Y/B

USY status information

during ERASE and WRITE cycles. READY/B

USY sta­tus information is available when CS is high. It will be
displayed until the next star t bit occurs as long as CS
stays high.

4.5 Organization (ORG)

When ORG is connected to V CC , the x16 memory orga­nization is selected. When ORG is tied to V

SS, the x8

memory organization is selected. There is an internal
pull-up resistor on the ORG pin that will select x16 orga­nization when left unconnected.

4.6 Program Enable (PE)

This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is
floated or tied to V

CC, the device can be programmed.

If the PE pin is tied to V

SS, programming will be inhib-

ited. There is an internal pull-up on this device that
enables programming if this pin is left floating.

Note: CS must go LOW between consecutive

instructions, except when performing a
sequential read (Refer to Section 3.1 for
more detail on sequential reads).

93C76/86

DS21132C-page 10 Preliminary  1996 Microchip Technology Inc.

NOTES:

DS21132C-page 11 Preliminary  1996 Microchip Technology Inc.

93C76/86

93C76/86 Product Identification System

To order or obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales office.

93C76/86 – \P

Package: P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Temperature Blank = 0°C to +70°C
Range: I = -40°C to +85°C

E = -40°C to +125°C

Device: 93C76/86 Microwire Serial EEPROM

93C76T/86T Microwire Serial EEPROM (Tape and Reel)

Sales and Support

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

Your local Microchip sales office (see below)

The Microchip Corporate Literature Center U.S. FAX: [phone]
The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

1.

2.

3.

DS21132C-page 12 Preliminary  1996 Microchip Technology Inc.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre­sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho­rized except with express written approval by Microchip . No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

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United Kingdom

Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: [phone] Fax: [phone]

France

Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: [phone] Fax: [phone]

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: [phone] Fax: [phone]

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: [phone] Fax: [phone]

JAPAN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: [phone] Fax: [phone]

11/7/96

AMERICAS

Corporate Office

Microchip T echnology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone] Fax: [phone]

Technical Support:

602 786-7627

Web:

http://www.microchip.com

Atlanta

Microchip T echnology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: [phone] Fax: [phone]

Boston

Microchip T echnology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: [phone] Fax: [phone]

Chicago

Microchip T echnology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: [phone] Fax: [phone]

Dallas

Microchip T echnology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: [phone] Fax: [phone]

Dayton

Microchip T echnology Inc.
Suite 150
Two Prestige Place
Miamisburg, OH 45342
Tel: [phone] Fax: [phone]

Los Angeles

Microchip T echnology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: [phone] Fax: [phone]

New Y ork

Microchip T echnology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: [phone] Fax: [phone]

San Jose

Microchip T echnology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: [phone] Fax: [phone]

Toronto

Microchip T echnology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: [phone] Fax: [phone]

All rights reserved.  1996, Microchip Technology Incorporated, USA. 11/96

Printed on recycled paper.