Microchip Technology Inc 93C66BT-E-SN, 93C66BT-E-P, 93C66B-E-SN, 93C66B-E-P, 93C66AT-E-SN Datasheet



M

4K 5.0V Automotive Temperature Microwire

FEATURES

• Single supply 5.0V operation

• Low power CMOS technology

- 1 mA active current (typical)

-1 µ A standby current (maximum)

• 512x 8 bit organization (93C66A)

• 256x 16 bit organization (93C66B)

• Self-timed ERASE and WRITE cycles (including
auto-erase)

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial interface

• Device status signal during ERASE/WRITE
cycles

• Sequential READ function

• 100,000 E/W cycles guaranteed

• Data retention > 200 years

• 8-pin PDIP and SOIC packages

• Available for the following temperature ranges:

- Automotive (E): -40 ° C to +125 ° C

93C66A/B

®

Serial EEPROM

PACKA GE TYPE

PDIP

CS

1

CLK

2

DI

3

4

DO

SOIC

1

CS

2

CLK

3

DI

4

DO

BLOCK DIAGRAM

8

93C66A/B

7

6

5

8

93C66A/B

7

6

5

V
NC

NC

V

CC

SS

V

NC

NC

V

CC

SS

DESCRIPTION

The Microchip Technology Inc. 93C66A/B is a 4K-bit,
low-voltage serial Electrically Erasable PROM. The
device memory is configured as 512 x 8 bits (93C66A)
or 256 x 16 bits (93C66B). Advanced CMOS
technology makes this device ideal for low-power,
nonvolatile memory applications. The 93C66A/B is
available in standard 8-pin DIP and surface mount
SOIC packages. This device is only recommended

for 5V automotive temperature applications. For all
commercial and industrial temperature applica­tions, the 93LC66A/B is recommended.

DI

CS

CLK

MEMORY

ARRAY

DATA

REGISTER

MEMORY
DECODE

LOGIC

CLOCK

GENERATOR

ADDRESS
DECODER

ADDRESS
COUNTER

OUTPUT

BUFFER

VCC
VSS

DO

Microwire is a registered trademark of National Semiconductor.

1998 Microchip Technology Inc.

Preliminary

DS21207B-page 1



93C66A/B

µ

µ

2:

3:

1.0 ELECTRICAL
CHARACTERISTICS

1.1 Maximum Ratings*

...................................................................................7.0V

V

CC

All inputs and outputs w.r.t.

Storage temperature.....................................-65 ° C to +150 ° C

Ambient temp. with power applied.................-65 ° C to +125 ° C

Soldering temperature of leads (10 seconds).............+300 ° C

ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings” may

cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri­ods may affect device reliability.

................ -0.6V to

SS

V

V

CC

+1.0V

TABLE 1-1: PIN FUNCTION TABLE

Name Function

CS Chip Select

CLK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

V

SS

NC No Connect

V

CC

Ground

Power Supply

TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS

All parameters apply over the

Automotive (E):V

specified operating ranges
unless otherwise noted

Parameter Symbol Min. Max. Units Conditions

High level input voltage V
Low level input voltage V
Low level output voltage V
High level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance

(all inputs/outputs)
Operating current
Standby current I

Clock frequency F
Clock high time T
Clock low time T
Chip select setup time T
Chip select hold time T
Chip select low time T
Data input setup time T
Data input hold time T
Data output delay time T
Data output disable time T
Status valid time T

Program cycle time

IH

IL
OL
OH
LI

LO

C

, C

IN

OUT

I

CC

write — 1.5 mA

CC

I

read — 1 mA

CCS

CLK
CKH
CKL
CSS
CSH
CSL

DIS
DIH

PD
CZ
SV

T

WC

EC

T

WL

T

Endurance — 100K — cycles 25 ° C, V

Note 1: This parameter is tested at Tamb = 25 ° C and F

This parameter is periodically sampled and not 100% tested.
This application is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or web­site.

= +4.5V to +5.5VTamb = -40 ° C to +125 ° C

CC

2.0 V

CC

+1 V (Note 2)

-0.3 0.8 V
— 0.4 V I

2.4 — V I

-10 10

-10 10
—7pF

OL

= 2.1 mA; V

OH

= -400 µ A; V
AV
AV

V

= V

IN
OUT

/V

IN

Tamb = +25 ° C, F

—1 µ A CS = V

— 2 MHz
250 — ns
250 — ns

50 — ns Relative to CLK

0 — ns Relative to CLK
250 — ns
100 — ns Relative to CLK
100 — ns Relative to CLK

— 400 ns C
— 100 ns C
— 500 ns C

= 100 pF

L
L

= 100 pF (Note 2)
= 100 pF

L

— 2 ms ERASE/WRITE mode
— 6 ms ERAL mode
— 15 ms WRAL mode

CLK

= 1 MHz.

CC

= 4.5V

CC

= 4.5V

to V

SS

CC

SS

= V

OUT

SS

CC

CC

to V

= 0 V (Notes 1 & 2)

CLK

= 1 MHz

= 5.0V, Block Mode (Note 3)

DS21207B-page 2

Preliminary

1998 Microchip Technology Inc.



93C66A/B

2.0 PIN DESCRIPTION

2.1 Chip Select (CS)

A high level selects the de vice; a low lev el deselects the
device and forces it into standb y mode. How ev er , a pro­gramming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought lo w during a program cycle , the
device will go into standby mode as soon as the pro­gramming cycle is completed.

CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal con­trol logic is held in a RESET status.

2.2 Serial Clock (CLK)

The Serial Clock (CLK) is used to synchronize the com­munication between a master device and
the 93C66A/B. Opcodes, addresses, and data bits
are clocked in on the positive edge of CLK. Data bits
are also clocked out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
freedom in preparing opcode, address, and data.

CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).

). This gives the controlling master

CKL

) between

CSL

CKH

) and

CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.

After detecting a START condition, the specified num­ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table 2-1 and Table 2-2). CLK and DI then become
don't care inputs waiting for a new START condition to
be detected.

Note: CS must go low between consecutive

instructions.

2.3 Data In (DI)

Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.

2.4 Data Out (DO)

Data Out (DO) is used in the READ mode to output
data synchronously with the CLK input (T
positive edge of CLK).

This pin also provides READY/B
tion during ERASE and WRITE cycles. READY/B
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (T
has been initiated. The status signal is not available on
DO, if CS is held low during the entire ERASE or
WRITE cycle. In this case, DO is in the HIGH-Z mode.
If status is checked after the ERASE/WRITE cycle, the
data line will be high to indicate the device is ready.

CSL

) and an ERASE or WRITE operation

USY status informa-

after the

PD

USY

TABLE 2-1: INSTRUCTION SET FOR 93C66A

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE

ERAL
EWDS
EWEN

READ

WRITE

WRAL

1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)12
1 00 10XXXXXXX — (RDY/BSY)12
1 00 00XXXXXXX — HIGH-Z 12
1 00 11XXXXXXX — HIGH-Z 12
1 10 A8A7A6A5A4A3A2A1A0 — D7 - D0 20
1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)20
1 00 01XXXXXXX D7 - D0 (RDY/BSY)20

TABLE 2-2: INSTRUCTION SET FOR 93C66B

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE

ERAL
EWEN
EWDS

READ

WRITE

WRAL

1 11 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11
1 00 10XXXXXX — (RDY/BSY)11
1 00 11XXXXXX — HIGH-Z 11
1 00 00XXXXXX — HIGH-Z 11
1 10 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27
1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)27
1 00 01XXXXXXD15 - D0 (RDY/BSY)27

1998 Microchip Technology Inc.

Preliminary

DS21207B-page 3

93C66A/B

3.0 FUNCTIONAL DESCRIPTION

Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a HIGH-Z state except when
reading data from the device, or when checking the
READY/B
The READY/B
ERASE/WRITE operation by polling the DO pin; DO
low indicates that programming is still in progress, while
DO high indicates the device is ready. The DO will enter
the HIGH-Z state on the falling edge of the CS.

3.1 START Condition

The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.

Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any de vice oper­ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.

An instruction following a START condition will only be
executed if the required amount of opcodes,
addresses, and data bits for any particular instruction is
clocked in.

After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new START condition is
detected.

USY status during a programming operation.

USY status can be verified during an

3.2 Data In (DI) and Data Out (DO)

It is possible to connect the Data In (DI) and Data
Out (DI) pins together. However, with this configuration
it is possible for a “bus conflict” to occur during the
“dummy zero” that precedes the READ oper ation, if A0
is a logic-high level. Under such a condition the voltage
level seen at DO is undefined and will depend upon the
relative impedances of DO and the signal source driv­ing A0. The higher the current sourcing capability of A0,
the higher the voltage at the DO pin.

3.3 Data Protection

During power-up, all programming modes of operation
are inhibited until V

3.8V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 3.8V at nominal conditions.

The ERASE/WRITE Disable (EWDS) and ERASE/
WRITE Enable (EWEN) commands give additional pro­tection against accidentally programming during nor­mal operation.

After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.

CC has reached a level greater than

FIGURE 3-1: SYNCHRONOUS DATA TIMING

VIH

CS

VIL

VIH

TCSS

CLK

VIL

TDIS

VIH

DI

VIL

VOH

DO

(READ)

(PROGRAM)

DO

VOL
VOH

VOL

TSV

Note: AC Test Conditions: VIL = 0.4V, VIH = 2.4V.

TCKH

TDIH

TPD

TCKL

STATUS VALID

TPD

TCSH

TCZ

TCZ

DS21207B-page 4 Preliminary  1998 Microchip Technology Inc.

93C66A/B

3.4 ERASE

The ERASE instruction forces all data bits of the spec­ified address to the logical “1” state. This cycle begins
on the rising clock edge of the last address bit.

The DO pin indicates the READY/B

USY status of the
device if CS is brought high after a minimum of 250 ns
low (T

CSL). DO at logical “0” indicates that program-

ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.

FIGURE 3-2: ERASE TIMING

CS

CLK

DI

1

1

N

1A

AN-1 AN-2

3.5 Erase All (ERAL)

The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle, except f or the different
opcode. The ERAL cycle is completely self-timed and
commences at the rising clock edge of the last address
bit. Clocking of the CLK pin is not necessary after the
device has entered the ERAL cycle.

The DO pin indicates the READY/B
device, if CS is brought high after a minimum of 250 ns
low (T

CSL) and before the entire ERAL cycle is com-

plete.

T

CSL

CHECK STATUS

A0

•••

T

SV TCZ

USY status of the

DO

HIGH-Z

FIGURE 3-3: ERAL TIMING

CS

CLK

10010X

DO

DI

HIGH-Z

•••

BUSY READY

WC

T

CSL

T

CHECK STATUS

X

T

SV TCZ

BUSY READY

T

EC

HIGH-Z

HIGH-Z

 1998 Microchip Technology Inc. Preliminary DS21207B-page 5

93C66A/B

3.6 ERASE/WRITE Disable and Enable
(EWDS/EWEN)

The device powers up in the ERASE/WRITE Disable
(EWDS) state. All programming modes must be pre­ceded by an ERASE/WRITE Enable (EWEN) instruc­tion. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruc­tion is executed or V

CC is removed from the device. To

protect against accidental data disturbance, the EWDS
instruction can be used to disable all ERASE/WRITE
functions and should follow all programming opera­tions. Execution of a READ instruction is independent
of both the EWEN and EWDS instructions.

FIGURE 3-4: EWDS TIMING

CS

CLK

DI

10

000X

3.7 READ

The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (93C66A) or 16-bit
(93C66B) output string. The output data bits will toggle
on the rising edge of the CLK and are stable after the
specified time delay (T
when CS is held high. The memory data will automati­cally cycle to the next register and output sequentially.

•••

X

PD). Sequential read is possible

T

CSL

FIGURE 3-5: EWEN TIMING

CS

CLK

00 1 1X

DI

1X

FIGURE 3-6: READ TIMING

CS

CLK

DI

110

An

•••

TCSL

•••

A0

DO

DS21207B-page 6 Preliminary  1998 Microchip Technology Inc.

HIGH-Z

0Dx

•••

D0 Dx

•••

D0

Dx D0

•••

93C66A/B

3.8 WRITE

The WRITE instruction is followed by 8 bits (93C66A)
or 16 bits (93C66B) of data which are written into the
specified address. After the last data bit is clocked into
the DI pin the self-timed auto-erase and programming
cycle begins.

The DO pin indicates the READY/B

USY status of the
device, if CS is brought high after a minimum of 250 ns
low (T

CSL) and before the entire write cycle is complete.

DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc­tion.

FIGURE 3-7: WRITE TIMING

CS

CLK

0

DI

1

An

1

•••

A0 Dx

3.9 Write All (WRAL)

The WRAL instruction will write the entire memory
array with the data specified in the command. The
WRAL cycle is completely self-timed and commences
at the rising clock edge of the last data bit. Clocking of
the CLK pin is not necessary after the device has
entered the WRAL cycle. The WRAL command does
include an automatic ERAL cycle for the device . There­fore, the WRAL instruction does not require an ERAL
instruction but the chip must be in the EWEN status.

The DO pin indicates the READY/B
device if CS is brought high after a minimum of 250 ns
low (T

CSL).

T

CSL

D0

•••

TSV

USY status of the

TCZ

DO

HIGH-Z

FIGURE 3-8: WRAL TIMING

CS

CLK

0

DO

DI

1

HIGH-Z

0

01X

•••

B

USY READY

Twc

TCSL

•••

Dx

X

D0

B

USY READY

T

WL

TSV

HIGH-Z

TCZ

HIGH-Z

 1998 Microchip Technology Inc. Preliminary DS21207B-page 7

93C66A/B

NOTES:

DS21207B-page 8 Preliminary  1998 Microchip Technology Inc.

NOTES:

93C66A/B

 1998 Microchip Technology Inc. Preliminary DS21207B-page 9

93C66A/B

NOTES:

DS21207B-page 10 Preliminary  1998 Microchip Technology Inc.

93C66A/B

93C66A/B PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

93C66A/B /P

Package:

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Temperature
Range:

Device:

93C66AT 4K Microwire Serial EEPROM (x8) Tape and Reel
93C66BT 4K Microwire Serial EEPROM (x16) Tape and Reel

E = -40°C to +125°C

93C66A 4K Microwire Serial EEPROM (x8)
93C66B 4K Microwire Serial EEPROM (x16)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office.

2. The Microchip Corporate Literature Center U.S. FAX: [phone].

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

 1998 Microchip Technology Inc. Preliminary DS21207B-page 11



M

W

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12/30/97

All rights reserved. © 1998, Microchip Technology Incorporated, USA. 1/98 Printed on recycled paper.

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DS21207B-page 12

Preliminary

1998 Microchip Technology Inc.