Microchip Technology Inc 93AA86-SN, 93AA76T-SN, 93AA76T-P, 93AA76-SN, 93AA76-P Datasheet



1996 Microchip Technology Inc.

Preliminary

DS21130C-page 1

FEATURES

• Single supply operation down to 1.8V

• Low power CMOS technology

- 1 mA active current typical

-5 µ A standby current (typical) at 3.0V

• ORG pin selectable memory configuration

- 1024 x 8 or 512 x 16-bit organization
(93AA76)

- 2048 x 8 or 1024 x 16-bit organization
(93AA86)

• Self-timed ERASE and WRITE cycles

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during ERASE/WRITE cycles

• Sequential READ function

• 10,000,000 ERASE/WRITE cycles guaranteed

• Data retention > 200 years

• 8-pin PDIP/SOIC package

• Temperature ranges available:

- Commercial (C): 0 ° C to +70 ° C

DESCRIPTION

The Microchip Technology Inc. 93AA76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
non-volatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93AA76/86 is available in standard 8-pin DIP and
8-pin surface mount SOIC packages.

P ACKA GE TYPES

BLOCK DIAGRAM

SOIC Package

DIP Package

CS

CLK

DI

DO

V

SS

PE

V

CC

ORG

CS

CLK

DI

DO

V

CC

PE
ORG
V

SS

93AA76/86

93AA76/86

1
2
3

4

8
7
6

5

1
2
3

4

8
7
6

5

DO

CS

CLK

VCCV

SS

Memory

Array

Address

Decoder

Data

Register

Counter

Address

Output

Buffer

Mode

Decode

Logic

Generator

Clock

DI

PE

93AA76/86

8K/16K 1.8V Microwire



Serial EEPROM

Microwire is a registered trademark of National Semiconductor Incorporated.

93AA76/86

DS21130C-page 2

Preliminary



1996 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

..................................................................................7.0V

All inputs and outputs w.r.t. V

SS

...............-0.6V to Vcc +1.0V

Storage temperature..................................... -65˚C to +150˚C

Ambient temp. with power applied................. -65˚C to +125˚C

Soldering temperature of leads (10 seconds)............. +300˚C

ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability

TABLE 1-1: PIN FUNCTION TABLE

1.2 A

C Test Conditions

Name Function

CS

CLK

DI

DO

V

SS

ORG

PE

V

CC

Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Program Enable
Power Supply

AC Waveform:

V

LO

= 2.0V

V

HI

= Vcc - 0.2V

(Note 1)

V

HI

= 4.0V for

(Note 2)

Timing Measurement Reference Level

Input 0.5 V

CC

Output 0.5 V

CC

Note 1: For V

CC

≤

4.0V

2: For V

CC

> 4.0V

TABLE 1-2: DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

= +1.8V to +6.0V

Commercial (C): Tamb = 0˚C to +70˚C

Parameter Symbol Min. Max. Units Conditions

High level input voltage V

IH1

2.0 V

CC

+1 V V

CC

≥

2.7V

V

IH2

0.7 V

CC

V

CC

+1 V V

CC

< 2.7V

Low level input voltage V

IL1

-0.3 0.8 V V

CC

≥

2.7V

V

IL2

-0.3 0.2 V

CC

VV

CC

< 2.7V

Low level output voltage V

OL1

— 0.4 V I

OL

= 2.1 mA; V

CC

= 4.5V

V

OL2

— 0.2 V I

OL

=100 µ A; V

CC

= V

CC

Min.

High level output voltage V

OH1

2.4 — V I

OH

= -400 µ A; V

CC

= 4.5V

V

OH2

V

CC

-0.2 — V I

OH

= -100 µ A; V

CC

= V

CC

Min.

Input leakage current I

LI

-10 10

µ

AV

IN

= 0.1V to V

CC

Output leakage current I

LO

-10 10

µ

AV

OUT

= 0.1V to V

CC

Pin capacitance
(all inputs/outputs)

C

INT

—7pF

(Note Note:)
Tamb = +25˚C, F

CLK

= 1 MHz

Operating current I

CC

write — 3 mA V

CC

= 5.5V

I

CC

read — 1

500

mA

µ

A

F

CLK

= 3 MHz; V

CC

= 5.5V

F

CLK

= 1 MHz; V

CC

= 3.0V

Standby current I

CCS

— 100

30

µ A µ

A

CLK = CS = 0V; V

CC

= 5.5V

CLK = CS = 0V; V

CC

= 3.0V

Note: This parameter is periodically sampled and not 100% tested.



1996 Microchip Technology Inc.

Preliminary

DS21130C-page 3

93AA76/86

TABLE 1-3: AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

= +1.8V to +6.0V

Commercial (C): Tamb = 0˚C to +70˚C

Parameter Symbol Min. Max. Units Conditions

Clock frequency F

CLK

—3

2
1

MHz
MHz

Mhz

4.5V ≤ V

CC

≤

6.0V

2.5V ≤ V

CC

≤

4.5V

1.8V ≤ V

CC

<

2.5V

Clock high time T

CKH

200
300
500

—ns

ns
ns

4.5V ≥ V

CC

≤

6.0V

2.5V ≤ V

CC

<

4.5V

1.8V ≤ V

CC

<

2.5V

Clock low time T

CKL

100
200
500

—ns

ns
ns

4.5V ≤ V

CC

≤

6.0V

2.5V ≤ V

CC

< 4.5V

1.8V ≤ V

CC < 2.5V

Chip select setup time T

CSS 50

100
250

—ns

ns
ns

4.5V ≤ VCC ≤ 6.0V, Relative to CLK

2.5V ≤ V

CC < 4.5V, Relative to CLK

1.8V ≤ V

CC < 2.5V, Relative to CLK

Chip select hold time T

CSH 0 — ns 1.8V ≤ VCC ≤ 6.0V

Chip select low time T

CSL 250 — ns 1.8V ≤ VCC ≤ 6.0V, Relative to CLK

Data input setup time T

DIS 50

100
250

—ns

ns
ns

4.5V ≤ VCC ≤ 6.0V, Relative to CLK

2.5V ≤ V

CC <4.5V, Relative to CLK

1.8V ≤ V

CC < 2.5V, Relative to CLK

Data input hold time T

DIH 50

100
250

—ns

ns
ns

4.5V ≤ VCC ≤ 6.0V, Relative to CLK

2.5V ≤ V

CC < 4.5V, Relative to CLK

1.8V ≤ V

CC < 2.5V, Relative to CLK

Data output delay time T

PD — 100

250
500

ns
ns
ns

4.5V ≤ VCC ≤ 6.0V, CL = 100 pF

2.5V ≤ V

CC < 4.5V, CL = 100 pF

1.8V ≤ V

CC < 2.5V, CL = 100 pF

Data output disable time T

CZ — 100

500

ns
ns

4.5V ≤ V

CC ≤ 5.5V (Note 1)

1.8V ≤ V

CC < 4.5V (Note 1)

Status valid time T

SV — 200

300
500

ns
ns
ns

4.5V ≥ VCC ≤ 6.0V, CL = 100 pF

2.5V ≤ V

CC < 4.5V, CL = 100 pF

1.8V ≤ V

CC < 2.5V, CL = 100 pF

Program cycle time T

WC — 5 ms ERASE/WRITE mode

T

EC — 15 ms ERAL mode

T

WL — 30 ms WRAL mode

Endurance — 10M — cycles 25°C, V

CC = 5.0V, Block Mode

(Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our BBS or website.

93AA76/86

DS21130C-page 4 Preliminary  1996 Microchip Technology Inc.

TABLE 1-4: INSTRUCTION SET FOR 93AA76: ORG=1 (X16 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 29
EWEN 1 00 1 1 X X X X X X X X — High-Z 13
ERASE 1 11 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 13
ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 13
WRITE 1 01 X A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29
WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29
EWDS 1 00 0 0 X X X X X X X X — High-Z 13

TABLE 1-5: INSTRUCTION SET FOR 93AA76: ORG=0 (X8 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out

Req. CLK

Cycles

READ 1 10 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 22
EWEN 1 00 1 1 X X X X X X X X — High-Z 14
ERASE 1 11 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 14
ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 14
WRITE 1 01 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22
WRAL 1 00 0 1 X X X X X X X X D7 - D0 (RDY/BSY) 22
EWDS 1 00 0 0 X X X X X X X X — High-Z 14

TABLE 1-6: INSTRUCTION SET FOR 93AA86: ORG=1 (X16 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 29
EWEN 1 00 1 1 X X X X X X X X — High-Z 13
ERASE 1 11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 13
ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 13
WRITE 1 01 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29
WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29
EWDS 1 00 0 0 X X X X X X X X — High-Z 13

TABLE 1-7: INSTRUCTION SET FOR 93AA86: ORG=0 (X8 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 22
EWEN 1 00 1 1 X X X X X X X X — High-Z 14
ERASE 1 11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 14
ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 14
WRITE 1 01 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22
WRAL 1 00 0 1 X X X X X X X X D7 - D0 (RDY/BSY) 22
EWDS 1 00 0 0 X X X X X X X X — High-Z 14