Microchip Technology Inc 93AA66XTSN, 93AA66XSN, 93AA66TSN, 93AA66TSM, 93AA66TP Datasheet
...
1996 Microchip Technology Inc. DS20067G-page 1
FEATURES
• Single supply with programming operation down
to 1.8V
• Low power CMOS technology
- 70
µ
A typical active READ current at 1.8V
-2
µ
A typical standby current at 1.8V
• ORG pin selectable memory configuration
- 128 x 8- or 64 x 16-bit organization (93AA46)
- 256 x 8- or 128 x 16-bit organization
(93AA56)
- 512 x 8 or 256 x 16 bit organization (93AA66)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles guaranteed on
93AA56 and 93AA66
• 1,000,000 E/W cycles guaranteed on 93AA46
• Data retention > 200 years
• 8-pin PDIP/SOIC
(SOIC in JEDEC and EIAJ standards)
• Temperature ranges supported
DESCRIPTION
The Microchip Technology Inc. 93AA46/56/66 are 1K,
2K and 4K low voltage serial Electrically Erasable
PROMs. The device memory is configured as x8 or x16
bits depending on the ORG pin setup. Advanced
CMOS technology makes these devices ideal for low
power non-volatile memory applications. The 93AA
Series is available in standard 8-pin DIP and surface
mount SOIC packages. The rotated pin-out 93AA46X/
56X/66X are offered in the “SN” package only.
- Commercial (C): 0 ° C to +70 ° C
PACKA GE TYPES
BLOCK DIAGRAM
1
2
3
4
8
7
6
5
CS
CLK
DI
DO
SS
V
NU
ORG
V
CC
1
2
3
4
8
7
6
5
SS
V
NU
ORG
V
CC
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
ORG
Vss
DO
DI
NU
Vcc
CS
CLK
DIP
SOIC
SOIC
93AA46
93AA56
93AA66
93AA46
93AA56
93AA66
93AA46X
93AA56X
93AA66X
MEMORY
ARRAY
ADDRESS
DECODER
V
CC VSS
DATA REGISTER
DO
MODE
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DI
CS
ORG
CLK
ADDRESS
COUNTER
93AA46/56/66
1K/2K/4K 1.8V Microwire
Serial EEPROM
Microwire is a registered trademark of National Semiconductor Incorporated.
93AA46/56/66
DS20067G-page 2
1996 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maxim
um Ratings
V
CC
............................................................................7.0V
All inputs and outputs w.r.t. V
SS
..........-0.6V to V
CC
+1.0V
Storage temperature................................-65˚C to +150˚C
Ambient temp. with power applied...........-65˚C to +125˚C
Soldering temperature of leads (10 seconds)........+300˚C
ESD protection on all pins ......................................... 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
V
SS
Ground
ORG Memory Configuration
NU Not Utilized
V
CC
Power Supply
TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS
V
CC
= +1.8V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C
Parameter Symbol Min Typ Max Units Conditions
High level input voltage V
IH
1 2.0 — V
CC
+1 V V
CC
≥
2.7V
V
IH
2 0.7 V
CC
—V
CC
+1 V V
CC
< 2.7V
Low level input voltage V
IL
1 -0.3 — 0.8 V V
CC
≥
2.7V
V
IL
2 -0.3 — 0.2 V
CC
VV
CC
< 2.7V
Low level output voltage V
OL
1 — — 0.4 V I
OL
= 2.1 mA; V
CC
= 4.5V
V
OL
2 — — 0.2 V I
OL
= 100 µ A; V
CC
= 1.8V
High level output voltage V
OH
1 2.4 — — V I
OH
= -400 µ A; V
CC
= 4.5V
V
OH
2V
CC
-0.2 — — V I
OH
= -100 µ A; V
CC
= 1.8V
Input leakage current I
LI
-10 — 10
µ
AV
IN
= 0.1V to V
CC
Output leakage current I
LO
-10 — 10
µ
AV
OUT
= 0.1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
—— 7 pFV
IN
/V
OUT
= 0V (Note 1 & 2)
Tamb = +25˚C, F
CLK
= 1 MHz
Operating current I
CC
write — — 3 mA F
CLK
=2 MHz; V
CC
=5.5V (Note 2)
I
CC
read — —
70
1
500
mA
µ A µ
A
F
CLK
= 2 MHz; V
CC
= 5.5V
F
CLK
= 1 MHz; V
CC
= 3.0V
F
CLK
= 1 MHz; V
CC
= 1.8V
Standby current I
CCS
2
100
30
µ A µ A µ
A
CLK = CS = 0V; V
CC
= 5.5V
CLK = CS = 0V; V
CC
= 3.0V
CLK = CS = 0V; V
CC
= 1.8V
Clock frequency F
CLK
2
1
MHz
MHz
V
CC
≥
4.5V
V
CC
< 4.5V
Clock high time T
CKH
250 ns
Clock low time T
CKL
250 ns
Chip select setup time T
CSS
50 ns Relative to CLK
Chip select hold time T
CSH
0 ns Relative to CLK
Chip select low time T
CSL
250 ns
Data input setup time T
DIS
100 ns Relative to CLK
Data input hold time T
DIH
100 ns Relative to CLK
Data output delay time T
PD
400 ns CL = 100 pF
Data output disable time T
CZ
100 ns CL = 100 pF (Note 2)
Status valid time T
SV
500 ns CL = 100 pF
Program cycle time T
WC
4 10 ms ERASE/WRITE mode
T
EC
8 15 ms ERAL mode (Vcc = 5V ± 10%)
T
WL
16 30 ms WRAL mode (Vcc = 5V ± 10%)
Endurance
93AA46
93AA56/66
—
—
1M
10M
—
—
1M
10M
—
—
25 ° C, Vcc = 5.0V, Block Mode
(Note 3)
Note 1: This parameter is tested at Tamb = 25 ° C and F
CLK
= 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
1996 Microchip Technology Inc. DS20067G-page 3
93AA46/56/66
TABLE 1-3: INSTRUCTION SET FOR 93AA46: ORG = 1 (X 16 ORGANIZATION)
TABLE 1-4: INSTRUCTION SET FOR 93AA46: ORG = 0 (X 8 ORGANIZATION)
TABLE 1-5: INSTRUCTION SET FOR 93AA56: ORG = 1 (X 16 ORGANIZATION)
TABLE 1-6: INSTRUCTION SET FOR 93AA56: ORG = 0 (X 8 ORGANIZATION)
TABLE 1-7: INSTRUCTION SET FOR 93AA66: ORG = 1 (X 16 ORGANIZATION)
TABLE 1-8: INSTRUCTION SET FOR 93AA66: ORG = 0 (X 8 ORGANIZATION)
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25
EWEN 1 00 1 1 X X X X — High-Z 9
ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY
)9
ERAL 1 00 1 0 X X X X — (RDY/BSY
)9
WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY
)25
WRAL 1 00 0 1 X X X X D15 - D0 (RDY/BSY
)25
EWDS 1 00 0 0 X X X X — High-Z 9
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
READ 1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18
EWEN 1 00 1 1 X X X X X — High-Z 10
ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY
)10
ERAL 1 00 1 0 X X X X X — (RDY/BSY
)10
WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY
)18
WRAL 1 00 0 1 X X X X X D7 - D0 (RDY/BSY
)18
EWDS 1 00 0 0 X X X X X — High-Z 10
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27
EWEN 1 00 1 1 X X X X X X — High-Z 11
ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY
)11
ERAL 1 00 1 0 X X X X X X — (RDY/BSY
)11
WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY
)27
WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY
)27
EWDS 1 00 0 0 X X X X X X — High-Z 11
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20
EWEN 1 00 1 1 X X X X X X X — High-Z 12
ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY
)12
ERAL 1 00 1 0 X X X X X X X — (RDY/BSY
)12
WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY
)20
WRAL 1 00 0 1 X X X X X X X D7 - D0 (RDY/BSY
)20
EWDS 1 00 0 0 X X X X X X X — High-Z 12
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27
EWEN 1 00 1 1 X X X X X X — High-Z 11
ERASE 1 11 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY
)11
ERAL 1 00 1 0 X X X X X X — (RDY/BSY
)11
WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY
)27
WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY) 27
EWDS 1 00 0 0 X X X X X X — High-Z 11
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
READ 1 10 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20
EWEN 1 00 1 1 X X X X X X X — High-Z 12
ERASE 1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY
)12
ERAL 1 00 1 0 X X X X X X X — (RDY/BSY
)12
WRITE 1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY
)20
WRAL 1 00 0 1 X X X X X X X D7 - D0 (RDY/BSY
)20
EWDS 1 00 0 0 X X X X X X X — High-Z 12
93AA46/56/66
DS20067G-page 4
1996 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
When the ORG pin is connected to V
CC
, the (x16) organization is selected. When it is connected to ground,
the (x8) organization is selected. Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data
from the device, or when checking the READY/BUSY
status during a programming operation. The ready/
busy status can be verified during an Erase/Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates
the device is ready. The DO will enter the high-Z state
on the falling edge of the CS.
2.1 ST
ART Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a STAR T condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
STAR T condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2 DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero” that
precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
2.3 Data Protection
During power-up, all programming modes of operation
are inhibited until V
CC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V
CC has fallen below 1.4V at nominal conditions.
The EWEN and EWDS commands give additional protection against accidentally programming during normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
2.4 READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable after
the specified time delay (T
PD). Sequential read is pos-
sible when CS is held high. The memory data will automatically cycle to the next register and output
sequentially.
2.5 Erase/Write Enable and Disable
(EWEN,EWDS)
The 93AA46/56/66 power up in the Erase/Write Disable
(EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V
CC is removed from the device. To protect against
accidental data disturb, the EWDS instruction can be
used to disable all Erase/Write functions and should follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and
EWDS instructions.
2.6 ERASE
The ERASE instruction forces all data bits of the specified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY
status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The ERASE cycle takes 4 ms per word typical.
2.7 WRITE
The WRITE instruction is followed by 16 bits (or by 8
bits) of data which are written into the specified
address. After the last data bit is put on the DI pin, CS
must be brought low before the next rising edge of the
CLK clock. This falling edge of CS initiates the selftimed auto-erase and programming cycle.
The DO pin indicates the READY/BUSY
status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL) and before the entire write cycle is complete.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruction.
The WRITE cycle takes 4 ms per word typical.
1996 Microchip Technology Inc. DS20067G-page 5
93AA46/56/66
2.8 Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences at
the falling edge of the CS. Clocking of the CLK pin is not
necessary after the device has entered the self clocking
mode. The ERAL instruction is guaranteed at 5V ±
10%.
The DO pin indicates the READY/BUSY
status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL) and before the entire write cycle is complete.
The ERAL cycle takes (8 ms typical).
2.9 Write All (WRAL)
The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences at the
falling edge of the CS. Clocking of the CLK pin is not
necessary after the device has entered the self clocking
mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL
instruction does not require an ERAL instruction but the
chip must be in the EWEN status. The WRAL instruction is guaranteed at 5V ± 10%.
The DO pin indicates the READY/BUSY
status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL).
The WRAL cycle takes 16 ms typical.
FIGURE 2-1: SYNCHRONOUS DATA TIMING
FIGURE 2-2: READ TIMING
CLK
STATUS VALID
VIH
VIL
CS
TCSS
TDIS
TDIH
TSV
TCSH
TCKH TCKL
TPD
TCZ
TCZ
TPD
VIH
VIL
DI
VIH
VIL
DO
(READ)
VOH
VOL
DO
(PROGRAM)
VOH
VOL
Tri-State is a registered trademark of National Semiconductor Incorporated.
CLK
CS
T
CSL
• A • • • A001 1
DI
DO
Dx • • • D00 Dx* • • • D0 Dx*
TRI-STATE™
n
D0
• • •
TRI-STATE
93AA46/56/66
DS20067G-page 6 1996 Microchip Technology Inc.
FIGURE 2-3: EWEN TIMING
FIGURE 2-4: EWDS TIMING
FIGURE 2-5: WRITE TIMING
CLK
CS
T
CSL
0 01
DI
1 1
• • •
XX
CLK
CS
T
CSL
0 01
DI
0 0
• • •
XX
CLK
CS
TCSL
01
DI
• • •
BUSY
D0
•A1 A0
• • •
Dx
READY
TWC
DO
TRI-STATE
n
1996 Microchip Technology Inc. DS20067G-page 7
93AA46/56/66
FIGURE 2-6: WRAL TIMING
FIGURE 2-7: ERASE TIMING
FIGURE 2-8: ERAL TIMING
CLK
CS
T
CSL
01
DI
• • •
BUSY
D0X0 X • • •Dx
READY
TWL
DO
01
TRI-STATE
TRI-STATE
STANDBY
Guaranteed at Vcc = +4.5V to +6.0V.
CLK
CS
TCSL
1
DI
An
BUSY
A0• • •
READY
TWC
DO
11
CHECK STATUS
STANDBY
TCZ
TRI-STATE
TSV
TRI-STATE
An-1 An-2
• Guaranteed at VCC = 5.0V ±10%.
CLK
CS
T
CSL
0
DI
0
BUSY
0
READY
T
EC
DO
11
CHECK STATUS
STANDBY
TCZ
TRI-STATE
TS
V
TRI-STATE
93AA46/56/66
DS20067G-page 8 1996 Microchip Technology Inc.
3.0 PIN DESCRIPTION
3.1 Chip Select (CS)
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought LOW during a program cycle,
the device will go into standby mode as soon as the programming cycle is completed.
CS must be LOW for 250 ns minimum (T
CSL) between
consecutive instructions. If CS is LOW, the internal control logic is held in a RESET status.
3.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communication between a master device and the 93AAXX.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be continued
anytime with respect to clock HIGH time (T
CKH) and
clock LOW time (T
CKL). This gives the controlling mas-
ter freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruction set truth table). CLK and DI then become don't care
inputs waiting for a new start condition to be detected.
3.3 Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
Note: CS must go LOW between consecutive
instructions.
3.4 Data Out (DO)
Data Out is used in the READ mode to output data synchronously with the CLK input (T
PD after the positive
edge of CLK).
This pin also provides READY/BUSY
status information
during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought HIGH after being LOW for minimum chip select
LOW time (T
CSL) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a pullup resistor on DO is required to read the READY signal.
3.5 Organization (ORG)
When ORG is connected to VCC, the (x16) memory
organization is selected. When ORG is tied to V
SS, the
(x8) memory organization is selected. ORG can only be
floated for clock speeds of 1MHz or less for the (x16)
memory organization. For clock speeds greater than 1
MHz, ORG must be tied to V
CC or VSS.
1996 Microchip Technology Inc. DS20067G-page 9
93AA46/56/66
NOTES:
93AA46/56/66
DS20067G-page 10 1996 Microchip Technology Inc.
NOTES:
93AA46/56/66
1996 Microchip Technology Inc. DS20067G-page 11
93AA46/56/66 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body), 8-lead
(93AA46/56/66)
Temperature Blank = 0°C to +70°C
Range:
Device:
93AA46/56/66
Microwire Serial EEPROM
93AA46/56/66X
Microwire Serial EEPROM in alternate
pinouts (SN package only)
93AA46T/56T/66T Microwire Serial EEPROM (Tape and Reel)
93AA46XT/56XT/66XT Microwire Serial EEPROM (Tape and Reel)
93AA46/56/66 -/P
DS20067G-page 12 1996 Microchip Technology Inc.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
WORLDWIDE SALES & SERVICE
ASIA/PACIFIC
China
Microchip Technology
Unit 406 of Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, Peoples Republic of China
Tel: 86 21 6275 5700
Fax: 011 86 21 6275 5060
Hong Kong
Microchip Technology
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431
India
Microchip Technology
No. 6, Legacy, Convent Road
Bangalore 560 025 India
Tel: 91 80 526 3148 Fax: 91 80 559 9840
Korea
Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
Singapore
Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
Taiwan, R.O.C
Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139
EUROPE
United Kingdom
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 1628 850303 Fax: 44 1628 850178
France
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: 39 39 6899939 Fax: 39 39 689 9883
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Y okohama
Kanagawa 222 Japan
Tel: 81 45 471 6166 Fax: 81 45 471 6122
9/3/96
AMERICAS
Corporate Office
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support:
602 786-7627
Web:
http://www.microchip.com
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508 480-9990 Fax: 508 480-8575
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972 991-7177 Fax: 972 991-8588
Dayton
Microchip Technology Inc.
Suite 150
Two Prestige Place
Miamisburg, OH 45342
Tel: 513 291-1654 Fax: 513 291-9175
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 714 263-1888 Fax: 714 263-1338
New Y ork
Microchip Technmgy Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279 Fax: 905 405-6253
All rights reserved. 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
Loading...