Microchip Technology Inc 37LV36-TI-P, 37LV36-TI-L, 37LV36-T-P, 37LV36-T-L, 37LV36-I-SN Datasheet



1996 Microchip Technology Inc. DS21109E-page 1

37LV36/65/128

FEATURES

• Operationally equivalent to Xilinx



XC1700 family

• Wide voltage range 3.0 V to 6.0 V

• Maximum read current 10 mA at 5.0 V

• Standby current 100 µ A typical

• Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock

• Full Static Operation

• Sequential Read/Program

• Cascadable Output Enable

• 10 MHz Maximum Clock Rate @ 5.0 Vdc

• Programmable Polarity on Hardware Reset

• Programming with industry standard EPROM pro­grammers

• Electrostatic discharge protection > 4,000 volts

• 8-pin PDIP/SOIC and 20-pin PLCC packages

• Data Retention > 200 years

• Temperature ranges:

- Commercial: 0 ° C to +70 ° C

- Industrial: -40 ° C to +85 ° C

DESCRIPTION

The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter­nally in a x32 configuration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V V

CC

range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot­strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.

Device Bits Programming Word

37LV36 36,288 1134 x 32
37LV65 65,536 2048 x 32

37LV128 131,072 4096 x 32

PACKA GE TYPES

BLOCK DIAGRAM

CLK



RESET/OE



CE

CEO

V

PP

Vss

9

10

11

12

13

321

20

19

18
17
16
15
14

4
5
6
7
8

VCCDATA

1

2

3

4

8

7

6

5

VCC

VPP

CEO

VSS

DATA

CLK

RESET/OE

CE



1

2

3

4

8

7

6

5

DATA

CLK

RESET/OE

CE

VCC

VPP

CEO

VSS

PDIP

37LV36

37LV65

37LV128

SOIC

PLCC

37LV36

37LV65

37LV128

37LV36

37LV65

37LV128

OE

DATA

EPROM
ARRAY

CEO

ADDRESS

Counter

CLK

RESET/OE

CE

36K, 64K, and 128K Serial EPROM Family

Xilinx is a registered trademark of Xilinx Corporation.

37LV36/65/128

DS21109E-page 2



1996 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

and input voltages w.r.t. V

SS

..........-0.6V to +0.6V

V

PP

voltage w.r.t. V

SS

during

programming......................................-0.6V to +14.0V

Output voltage w.r.t. V

SS

............... -0.6V to V

CC

+0.6V

Storage temperature ..........................-65˚C to +150˚C

Ambient temp. with power applied .....-65˚C to +125˚C

Soldering temperature of leads (10 sec.).........+300 ° C

ESD protection on all pins .....................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con­ditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function 8 20

DATA Data I/O 1 2

CLK Clock Input 2 4

RESET/OE

Reset Input and Output
Enable

36

CE

Chip Enable Input 4 8

V

SS

Ground 5 10

CEO

Chip Enable Output 6 14

V

PP

Programming Voltage Supply 7 17

V

CC

+3.0V to 6.0V Power Supply 8 20

Not Labeled Not utilized, not connected

TABLE 1-2: READ OPERATION DC CHARACTERISTICS

V

CC

= +3.0 to 6.0V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C

Parameter Symbol Min. Max. Units Conditions

DATA, CE

, CEO and Reset pins:
High level input voltage
Low level input voltage
High level output voltage

Low level output voltage

V

IH

V

IL

V

OH1

V

OH2

V

OL

2.0

-0.3

3.86

2.4
—

V

CC

0.8

.32

V
V
VVI

OH

= -4 mA V

CC

≥

4.5V

I

OH

= -4 mA V

CC

≥

3.0V

I

OL

= 4.0 mA

Input Leakage I

LI

-10 10

µ

AV

IN

= .1V to V

CC

Output Leakage I

LO

-10 10

µ

AV

OUT

= .1V to V

CC

Input Capacitance
(all inputs/outputs)

C

INT

— 10 pF Tamb = 25 ° C; F

CLK

= 1 MHz (Note 1)

Operating Current I

CC

Read —

—

10

2

mAmAV

CC

= 6.0V, CLK = 10 MHz

V

CC

= 3.6V, CLK = 2.5 MHz

Outputs open

Standby Current I

CCS

— 100

50

µ A µ

A

V

CC

= 6.0V, CE = 5.8V

V

CC

= 3.6V, CE = 3.4V

Note 1: This parameter is initially characterized and not 100% tested.



1996 Microchip Technology Inc. DS21109E-page 3

37LV36/65/128

2.0 DATA

2.1 Data I/O

Three-state DATA output for reading and input during
programming.

3.0 CLK

3.1 Cloc

k Input

Used to increment the internal address and bit
counters for reading and programming.

4.0 RESET/OE

4.1 Reset Input and Output Enab

le

A LOW level on both the CE

and RESET/OE inputs
enables the data output driver. A HIGH level on
RESET/OE

resets both the address and bit counters.
In the 37LVXXX, the logic polarity of this input is pro­grammable as either RESET/OE

or OE/RESET. This

document describes the pin as RESET/OE

although
the opposite polarity is also possible. This option is
defined and set at device program time.

5.0 CE

5.1 Chip Enab

le Input

CE

is used for device selection. A LOW level on both

CE

and OE enables the data output driver. A HIGH

level on CE

disables both the address and bit counters

and forces the device into a low power mode.

6.0 CEO

6.1 Chip Enab

le Output

This signal is asserted LOW on the clock cycle follow­ing the last bit read from the memory. It will stay LOW
as long as CE

and OE are both LOW. It will then follow

CE

until OE goes HIGH. Thereafter, CEO will stay
HIGH until the entire EPROM is read again. This pin
also used to sense the status of RESET polarity when
Programming Mode is entered.

7.0 VPP

7.1 Pr

ogramming Voltage Supply

Used to enter programming mode (+13 volts) and to
program the memory (+13 volts). Must be connected
directly to Vcc for normal Read operation. No over­shoot above +14 volts is permitted.

8.0 CASCADING SERIAL EPROMS

Cascading Serial EPROMs provide additional memory
for multiple FPGAs configured as a daisy-chain, or for
future applications requiring larger configuration mem­ories.

When the last bit from the first Serial EPROM is read,
the next clock signal to the Serial EPROM asserts its
CEO

output LOW and disables its DATA line. The sec­ond Serial EPROM recognizes the LOW level on its CE
input and enables its DATA output.

When configuration is complete, the address counters
of all cascaded Serial EPROMs are reset if RESET
goes LOW forcing the RESET/OE

on each Serial
EPROM to go HIGH. If the address counters are not to
be reset upon completion, then the RESET/OE

inputs

can be tied to ground.
Additional logic may be required if cascaded memories

are so large that the rippled chip enable is not fast
enough to activate successive Serial EPROMs.

9.0 STANDBY MODE

The 37LVXXX enters a low-power Standby Mode
whenever CE

is HIGH. In Standby Mode, the Serial
EPROM consumes less than 100 µ A of current. The
output will remain in a high-impedance state regardless
of the state of the OE

input.

10.0 PROGRAMMING MODE

Programming Mode is entered by holding V

PP

HIGH

(+13 volts) for two clock edges and then holding V

PP

=

V

DD

for one clock edge. Programming mode is exited

by driving a LOW on both CE

and OE and then remov­ing power from the device. Figures 4 through 7 show
the programming algorithm.

11.0 37LVXXX RESET POLARITY

The 37LVXXX lets the user choose the reset polarity as
either RESET/OE

or OE/RESET. Any third-party com­mercial programmer should prompt the user for the
desired reset polarity.

The programming of the overflow word should be han­dled transparently by the EPROM programmer; it is
mentioned here as supplemental information only.

The polarity is programmed into the first overflow word
location, maximum address+1. 00000000 in these
locations makes the reset active LOW, FFFFFFFF in
these locations makes the reset active HIGH. The
default condition is RESET active HIGH.

37LV36/65/128

DS21109E-page 4



1996 Microchip Technology Inc.

FIGURE 11-1: READ CHARACTERISTICS TIMING

TABLE 11-1: READ CHARACTERISTICS

AC Testing Waveform: V

IL

= 0.2V; V

IH

= 3.0V
AC Test Load: 50 pF
V

OL

= V

OL

_MAX; V

OH

= V

OH

_MIN

Symbol Parameter

Limits 3.0V ≤

Vcc ≤ 6.0V

Limits 4.5V ≤

Vcc ≤ 6.0V

Units Conditions

Min. Max. Min. Max.

T

OE

OE

to Data Delay — 45 — 45 ns

T

CE

CE

to Data Delay — 60 — 50 ns

T

CAC

CLK to Data Delay — 200 — 60 ns

T

OH

Data Hold from CE

, OE or CLK 0—0—ns

T

DF

CE

or OE to Data Float Delay — 50 — 50 ns Notes 1, 2

T

LC

CLK Low Time 100 — 25 — ns

T

HC

CLK High Time 100 — 25 — ns

T

SCE

CE

Set up Time to CLK

(to guarantee proper counting)

40 — 25 — ns Note 1

T

SCED

CE setup time to CLK
(to guarantee proper DATA read)

100 — 80 — ns

T

HCE

CE

Hold Time to CLK

(to guarantee proper counting)

0—0—nsNote 1

T

HCED

CE

hold time to CLK

(to guarantee proper DATA read)

50 — 0 — ns

T

HOE

OE

High Time

(Guarantees counters are Reset)

100 20 — ns

CLK max Clock Frequency — 2.5 — 10 MHz

Note 1: This parameter is periodically sampled and not 100% tested.

2: Float delays are measured with output pulled through 1k Ω to V

LOAD

= V

CC

/2.

THCE

TSCE

THOE

TDF

TOH

TOH

THC

TCAC

TLC

TSCE

TOE

DATA

CLK

RESET/OE

CE

TCE

TSCED

THCED