Microchip Technology Inc 24LCS52T-I-ST, 24LCS52T-I-SN, 24LCS52T-I-P, 24LCS52T-ST, 24LCS52T-SN Datasheet



C 

24LCS52

2

2K 2.5V I



C

Serial EEPROM with Software Write Protect

FEATURES

• Single supply with operation down to 2.5V

• Low power CMOS technology

- 1 mA active current typical

- 10 µ A standby current typical at 5.5V

-5 µ A standby current typical at 3.0V

• Organized as a single block of 256 bytes (256 x 8)

• Software write protection for lower 128 bytes

• Hardware write protection for entire array

• 2-wire serial interface bus, I

• 100kHz (2.5V) and 400kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 3.5 ms typical write cycle time for page-write

• 10,000,000 erase/write cycles guaranteed

• ESD protection >4,000V

• Data retention > 200 years

• 8-pin DIP, SOIC or TSSOP packages

• Available for extended temperature ranges

- Commercial (C): 0 ° C to +70 ° C

- Industrial (I): -40 ° C to +85 ° C

2

compatible

DESCRIPTION

The Microchip Technology Inc. 24LCS52 is a 2K bit
Electrically Erasable PROM capable of operation
across a broad voltage range (2.5V to 5.5V). This
device has a software write protect feature for the lower
half of the array, as well as an external pin that can be
used to write protect the entire array. The software write
protect feature is enabled by sending the device a spe­cial command, and once this feature has been enabled,
it cannot be reversed. In addition to the software pro­tect feature, there is a WP pin that can be used to write
protect the entire array, regardless of whether the soft­ware write protect register has been written or not. This
allows the system designer to protect none, half or all of
the array, depending on the application. The device is
organized as a single block of 256 x 8-bit memory with
a 2-wire serial interface. Low voltage design permits
operation down to 2.5 volts with typical standby and
active currents of only 5 µ A and 1 mA respectively. The
device has a page-write capability for up to 16 bytes of
data. The device is available in the standard 8-pin DIP,
8-pin SOIC and TSSOP packages.

PACKA GE TYPES

PDIP/SOIC

A0

1

A1

2

A2

3

Vss

4

TSSOP

1

A0

2

A1

3

A2

Vss

4

BLOCK DIAGRAM

A0 A1 A2

I/O
Control
Logic

SDA

Vcc

Vss

SCL

WP

Memory
Control

Logic

24LCS52

24LCS52

XDEC

Vcc

8

WP

7

SCL

6

SDA

5

Vcc

8

WP

7

SCL

6

SDA

5

HV Generator

Software write
protected area

(00h-7Fh)

Standard
Array

Write Protect
Circuitry

YDEC

SENSE AMP
R/W CONTROL

2

I

C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

Preliminary

DS21166B-page 1



24LCS52

µ

µ

µ

µ

1.0 ELECTRICAL

TABLE 1-1: PIN FUNCTION TABLE

CHARACTERISTICS

1.1 Maxim

CC

V

...................................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins............................................. ≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

SCL and SDA pins:

High level input voltage
Low level input voltage V
Hysteresis of Schmitt trigger inputs V
Low level output voltage V

Input leakage current

All I/O pins I

WP pin I
Output leakage current I
Pin capacitance (all inputs/outputs) C

Operating current I

Standby current I

Note: This parameter is periodically sampled and not 100% tested.

um Ratings*

SS

............... -0.6V to V

Parameter Symbol Min. Max. Units Conditions

CC

+1.0V

A0, A1, A2

V

= +2.5V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C

CC

V

IH

IL

HYS

OL

LI
LI

LO

IN

,

C

OUT

Write — 3 mA V

CC

I

CC

Read — 1 mA V

CCS

.7 V

CC

.05 V

CC

-10 10

-10 50

-10 10
—10pFV

—30

Name Function

SS

V
SDA
SCL

CC

V

Ground
Serial Address/Data I/O
Serial Clock
+2.5V to 5.5V Power Supply
Chip Selects

WP

Hardware Write Protect

Industrial (I): Tamb = -40˚C to +85˚C

V

CC

.3 V

V

— V (Note)

.40 V I

AV
A WP = V
AV

µ

AV

100

AV

OL

= 3.0 mA, V

= 0.1V to 5.5V, WP = Vss

IN

CC

= 0.1V to 5.5V

OUT
CC

= 5.0V (Note)

Tamb = 25˚C, F

= 5.5V, SCL = 400 kHz

CC
CC

= 5.5V, SCL = 400 kHz
= 3.0V, SDA = SCL = V

CC
CC

= 5.5V, SDA = SCL = V

CC

= 2.5V

CLK

= 1 MHz

CC
CC

FIGURE 1-1: BUS TIMING START/STOP

SCL

SU:STA

T

SDA

DS21166B-page 2

START STOP

THD:STA

Preliminary

VHYS

TSU:STO

1996 Microchip Technology Inc.

TABLE 1-3: AC CHARACTERISTICS



24LCS52

Parameter Symbol

Vcc = 2.5-5.5V

STD MODE

Vcc = 4.5 - 5.5V

FAST MODE

Units Remarks

Min. Max. Min. Max.

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

HIGH

HD

CLK

LOW

R
F

:

STA

— 100 — 400 kHz
4000 — 600 — ns
4700 — 1300 — ns

— 1000 — 300 ns

— 300 — 300 ns

(Note 1)
(Note 1)

4000 — 600 — ns After this period the first

clock pulse is generated

START condition setup time T

SU

STA

:

4700 — 600 — ns Only relevant for repeated

START condition
Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock T
Bus free time T

HD

SU

SU

:
:
:

AA

BUF

DAT
DAT
STO

0—0—ns

(Note 2)

250 — 100 — ns

4000 — 600 — ns

— 3500 — 900 ns

(Note 2)

4700 — 1300 — ns Time the bus must be free

before a new transmission

can start
Output fall time from V
minimum to V

IL

IH

maximum

Input filter spike suppression

T

OF

SP

T

— 250 20 +0.1 CB250 ns (Note 1), CB ≤ 100 pF

—50—50ns

(Note 3)
(SDA and SCL pins)

Write cycle time T

WR

Endurance 10M — 10M — cycles 25 ° C, V

— 10 — 10 ms Byte or Page mode

CC

= 5.0V, Block

Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP

and V

specifications are due to new Schmitt trigger inputs which provide improved

HYS

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

TF

TLOW

SCL

SDA

SDA

OUT

1996 Microchip Technology Inc.

SU:STA

T

IN

TSP

TAA

THD:STA

THD:STA

THIGH

THD:DAT TSU:DAT

TAA

Preliminary

TR

TSU:STO

TBUF

DS21166B-page 3

24LCS52

2.0 FUNCTIONAL DESCRIPTION

The 24LCS52 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LCS52
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter­mines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six­teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

Note: The 24LCS52 does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.

3.6 Device Addressing

A control byte is the first byte received following the
START condition from the master device. The first part
of the control byte consists of a 4-bit control code which
is set to 1010 for normal read and write operations and
0110 for writing to the write protect register. The control
byte is followed by three chip select bits (A2, A1, A0).
The chip select bits allow the use of up to eight
24LCS52 devices on the same bus and are used to
determine which device is accessed. The chip select
bits in the control byte must correspond to the logic lev­els on the corresponding A2, A1 and A0 pins for the
device to respond. The device will not acknowledge if
you attempt a read command with the control code set
to 0110.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS

(A) (B) (C) (D) (A)(C)

SCL

SDA

START

CONDITION

DS21166B-page 4 Preliminary  1996 Microchip Technology Inc.

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

24LCS52

The eighth bit of slave address determines if the master
device wants to read or write to the 24LCS52 (Figure 3-

2). When set to a one a read operation is selected and
when set to a zero a write operation is selected.

Operation

Read
Write

Set Write Protect

Control

Code

1010
1010

0110

Chip

Select

A2 A1 A0
A2 A1 A0
A2 A1 A0

R/W

1
0
0

Register

FIGURE 3-2: CONTROL BYTE

ALLOCATION

STAR T READ/WRITE

SLAVE ADDRESS R/W A

1 0 1 0 A2 A1 A0

OR

0 1 1 0 A2 A1 A0

4.0 WRITE OPERATIONS

4.1 Byte Write

Following the start signal from the master, the device
code (4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24LCS52. After receiving

another acknowledge signal from the 24LCS52 the
master device will transmit the data word to be written
into the addressed memory location. The 24LCS52
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur­ing this time the 24LCS52 will not generate acknowl­edge signals (Figure 4-1). If an attempt is made to write
to the array when the software or hardware write pro­tection has been enabled, the device will acknowledge
the command but no data will be written. The write
cycle time must be observed even if the write protection
is enabled.

4.2 Page Write

The write control byte, word address and the first data
byte are transmitted to the 24LCS52 in the same way
as in a byte write. But instead of generating a stop con­dition, the master transmits up to 15 additional data
bytes to the 24LCS52 which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a stop condi­tion. After the receipt of each word, the four lower order
address pointer bits are internally incremented by one.
The higher order four bits of the word address remains
constant. If the master should transmit more than 16
bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter­nal write cycle will begin (Figure 4-2). If an attempt is
made to write to the array when the hardware write pro­tection has been enabled, the device will acknowledge
the command but no data will be written. The write
cycle time must be observed even if the write protection
is enabled.

FIGURE 4-1: BYTE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S P

CONTROL

BYTE

WORD

ADDRESS

A
C
K

A
C
K

DATA

S
T
O
P

A
C
K

FIGURE 4-2: PAGE WRITE

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

 1996 Microchip Technology Inc. Preliminary DS21166B-page 5

T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n DATA n + 15

S P

A
C
K

A
C
K

A
C
K

A
C
K

S
T
O
P

A
C
K

24LCS52

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send­ing a start condition followed by the control byte for a
write command (R/W
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.

FIGURE 5-1: ACKNOWLEDGE POLLING

= 0). If the device is still busy with

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

6.0 WRITE PROTECTION

The 24LCS52 has a software write protect feature that
allows the lower half of the array (addresses 00h - 7Fh)
to be permanently write protected, as well as a WP pin
that can be used to protect the entire array.

6.1 Software Write Protect

The software write protect feature is invoked by writing
to the write protect register. This is done by sending a
command similar to a normal write command. As
shown in Figure 6-1, the write protect register is written
by sending a write command with the slave address set
to 0110 instead of 1010 and the address bits and data
bits are don’t cares. Once the software write protect
register has been written, the device will not acknowl­edge the 0110 control byte. Once the software write

protect register has been written, the write protec­tion is enabled and cannot be reversed, even if the
device is powered down.

6.2 Hardware Write Protect

The WP pin can be tied to Vcc, VSS, or left floating. If
tied to V
regardless of whether the software write protect regis­ter has been written or not. If the WP pin is set to V
it will prevent the software write protect register from
being written. If the WP is tied to V
then write protection is determined by the status of the
software write protect register.

CC, the entire array will be write protected,

CC,

SS or left floating,

Send Control Byte

with R/W = 0

Did Device

Acknowledge

NO

(ACK = 0)?

YES

Next

Operation

FIGURE 6-1: SETTING WRITE PROTECT REGISTER

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T
A
R
T

S P

CONTROL

BYTE

WORD

ADDRESS

A
C
K

S

DATA

A
C
K

T
O
P

A
C
K

DS21166B-page 6 Preliminary  1996 Microchip Technology Inc.

24LCS52

7.0 READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

7.1 Current Address Read

The 24LCS52 contains an address counter that main­tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W
the 24LCS52 issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24LCS52 discontinues transmission (Figure 7-1).

7.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the

bit of the

bit set to one,

24LCS52 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W

bit set to a one. The 24LCS52 will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LCS52 dis­continues transmission (Figure 7-2). After this com­mand, the internal address counter will point to the
address location following the one that was just read.

7.3 Sequential Read

Sequential reads are initiated in the same way as a ran­dom read except that after the 24LCS52 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LCS52 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).

To provide sequential reads the 24LCS52 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.

FIGURE 7-1: CURRENT ADDRESS READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

FIGURE 7-2: RANDOM READ

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T

CONTROL

A

BYTE

R
T

ADDRESS (n)

S P

A
C
K

FIGURE 7-3: SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

A
C
K

A
C
K

S
T
A
R
T

S

WORD

CONTROL

BYTE

A
C
K

S
T
A
R
T

S

A
C
K

A
C
K

CONTROL

BYTE

DATA

S
T
O
P

P

N
O

A
C
K

S
T
O
P

A
C

DATA (n)

K

N

O

A
C
K

S
T
O
P

P

A
C
K

N
O

A
C
K

 1996 Microchip Technology Inc. Preliminary DS21166B-page 7

24LCS52

7.4 Contiguous Addressing Across Multiple Devices

The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 16K bits by add­ing up to eight 24LCS52 devices on the same bus. In
this case, software can use A0 of the control byte
address bit A8, A1 as address bit A9, and A2 as
address bit A10. It is not possible to sequentially read
across device boundaries.

as

8.0 PIN DESCRIPTIONS

8.1 SDA Serial Address/Data Input/Output

This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
kHz).

For normal data transfer SDA is allowed to change only
during SCL low . Changes during SCL high are reserved
for indicating the START and STOP conditions.

8.2 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3 A0, A1, A2

The levels on these inputs are compared with the cor­responding bits in the slave address. The chip is
selected if the compare is true.

Up to eight 24LCS52 devices may be connected to the
same bus by using different chip select bit combina­tions. These inputs must be connected to either Vcc or
Vss.

CC (typical 10kΩ for 100 kHz, 1kΩ for 400

8.4 WP

This is the hardware write protect pin. It can be tied to
V

CC, VSS, or left floating. If tied to Vcc, the hardware

write protection is enabled. If the WP pin is tied to Vss
the hardware write protection is disabled. If the WP pin
is left floating, an internal pull down resistor will pull the
WP pin to Vss and the hardware write protection will be
disabled.

8.5 Noise Protection

The 24LCS52 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the V
is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

CC

DS21166B-page 8 Preliminary  1996 Microchip Technology Inc.

NOTES:

24LCS52

 1996 Microchip Technology Inc. Preliminary DS21166B-page 9

24LCS52

NOTES:

DS21166B-page 10 Preliminary  1996 Microchip Technology Inc.

24LCS52

24LCS52 Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

24LCS52 — /P

Package: P = Plastic DIP (300 mil Body), 8-lead

Temperature Blank = 0˚C to +70˚C
Range: I = –40˚C to +85˚C

Device: 24LCS52 2K I

24LCS52T 2K I

SN = Plastic SOIC (150 mil Body)
ST = TSSOP, 8-lead

2

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

 1996 Microchip Technology Inc. Preliminary DS21166B-page 11

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United Kingdom

Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: [phone] Fax: [phone]

France

Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: [phone] Fax: [phone]

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: [phone] Fax: [phone]

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: [phone] Fax: [phone]

JAPAN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Y okohama
Kanagawa 222 Japan
Tel: [phone] Fax: [phone]

9/3/96

All rights reserved.  1996, Microchip Technology Incorporated, USA. 9/96

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre­sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho­rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21166B-page 12 Preliminary  1996 Microchip Technology Inc.