Microchip Technology Inc 24LCS21T-I-SN, 24LCS21-I-SN, 24LCS21-I-P, 24LCS21-SN, 24LCS21-P Datasheet
...
C
24LCS21
2
1K 2.5V Dual Mode I
C
Serial EEPROM
FEATURES
• Completely implements DDC1 /DDC2
interface for monitor identification
• Hardware write-protect pin
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µ A standby current typical at 5.5V
• 2-wire serial interface bus, I
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
(SCL)
• 10,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
- Commercial (C): 0 ° C to +70 ° C
- Industrial (I) -40 ° C to +85 ° C
2
compatible (SCL)
DESCRIPTION
The Microchip Technology Inc. 24LCS21 is a
128 x 8-bit dual-mode Electrically Erasable PROM.
This device is designed for use in applications requiring
storage and serial transmission of configuration and
control information. Two modes of operation have been
implemented: Transmit Only Mode and bi-directional
Mode. Upon power-up, the device will be in the Transmit
Only Mode, sending a serial bit stream of the entire
memory array contents, clocked by the VCLK pin. A
valid high to low transition on the SCL pin will cause the
device to enter the bi-directional Mode, with byte selectable read/write capability of the memory array in stan-
2
dard I
C protocol.
The 24LCS21 also enables the user to write-protect the
entire memory contents using its write-protect pin. The
24LCS21 is available in a standard 8-pin PDIP and
SOIC package in both commercial and industrial
temperature ranges.
P ACKA GE TYPES
PDIP
NC
NC
WP
VSS
SOIC
NC
NC
WP
VSS
BLOCK DIAGRAM
WP
I/O
CONTROL
LOGIC
SDA SCL
VCLK
VCC
VSS
MEMORY
CONTROL
LOGIC
1
2
3
4
1
2
3
4
8
24LCS21
7
6
5
8
24LCS21
7
6
5
XDEC
CC
V
VCLK
SCL
SDA
CC
V
VCLK
SCL
SDA
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
DDC is a trademark of the Video Electronics Standards Association.
2
I
C is a trademark of Philips Corporation.
1996 Microchip Technology Inc. DS21127B-page 1
24LCS21
≥
µ
µ
µ A µ
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maxim
CC
V
...................................................................................7.0V
All inputs and outputs w.r.t. V
Storage temperature.....................................-65 ° C to +150 ° C
Ambient temp. with power applied................-65 ° C to +125 ° C
Soldering temperature of leads (10 seconds).............+300 ° C
ESD protection on all pins ..................................................≥ 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
um Ratings*
SS
............... -0.6V to V
CC
+1.0V
TABLE 1-1: PIN FUNCTION TABLE
TABLE 1-2: DC CHARACTERISTICS
CC
V
= +2.5V to 5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C
Industrial (I): Tamb = -40
Parameter Symbol Min Max Units Conditions
SCL and SDA pins:
High level input voltage
Low level input voltage
IH
V
V
IL
Input levels on VCLK pin:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs V
Low level output voltage V
Low level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance (all inputs/outputs) C
Operating current I
Standby current I
I
CC
CC
V
IH
IL
V
HYS
OL1
OL2
LI
LO
INT
Write
Read
CCS
Note:This parameter is periodically sampled and not 100% tested.
CC
0.7 V
0.3 V
2.0 0.8
0.2 V
.05 V
CC
-10 10
-10 10
—
—
—30
Name Function
WP
V
SS
Write Protect (active low)
Ground
SDA Serial Address/Data I/O
SCL Serial Clock (Bi-directional Mode)
VCLK Serial Clock (Transmit-Only Mode)
V
CC
+2.5V to 5.5V Power Supply
NC No Connection
°
C to +85 ° C
V
CC
CC
V
V
V
CC
V
2.7V (Note)
CC
V
< 2.7V (Note)
— V (Note)
0.4 V I
0.6 V I
AV
AV
10 pF V
3
mAmAV
OL
= 3 mA, V
= 6 mA, V
OL
IN
= 0.1V to V
= 0.1V to V
OUT
CC
= 5.0V (Note1),
Tamb = 25 ° C, F
= 5.5V, SCL = 400 kHz
CC
CC
= 2.5V (Note 1)
= 2.5V
CC
CC
CC
CLK
= 1 MHz
1
CC
V
= 3.0V, SDA = SCL = V
100
A
V
= 5.5V, SDA = SCL = V
CC
CC
CC
DS21127B-page 2
1996 Microchip Technology Inc.
TABLE 1-3: AC CHARACTERISTICS
24LCS21
≤
Parameter Symbol
Units Remarks
Min Max Min Max
Vcc= 2.5-5.5V Vcc= 4.5 - 5.5V
Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T
HIGH
LOW
HD
CLK
R
F
:
0 100 0 400 kHz
4000 — 600 — ns
4700 — 1300 — ns
— 1000 — 300 ns (Note 1)
— 300 — 300 ns (Note 1)
STA
4000 — 600 — ns After this period the first clock
pulse is generated
START condition setup time T
SU
:
STA
4700 — 600 — ns Only relevant for repeated
START condition
Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock T
Bus free time T
HD
SU
SU
:
:
:
AA
BUF
DAT
DAT
STO
0 — 0 — ns (Note 2)
250 — 100 — ns
4000 — 600 — ns
— 3500 — 900 ns (Note 2)
4700 — 1300 — ns Time the bus must be free
before a new transmission can
start
Output fall time from V
minimum to V
IL
IH
maximum
Input filter spike suppression
T
OF
T
SP
— 250 20 + 0.1
C
250 ns (Note 1), C
B
— 100 — 50 ns (Note 3)
B
100 pF
(SDA and SCL pins)
Write cycle time T
WR
— 10 — 10 ms Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK T
VCLK high time T
VCLK low time T
VCLK setup time T
VCLK hold time T
Mode transition time T
Transmit-Only power up time T
Input filter spike suppression
VAA
VHIGH
VLOW
VHST
SPVL
VHZ
VPU
T
SPV
— 2000 — 1000 ns
4000 — 600 — ns
4700 — 1300 — ns
0—0—ns
4000 — 600 — ns
— 500 — 500 ns
0—0—ns
— 100 — 100 ns
(VCLK pin)
Endurance — 10M — 10M — cycles 25
°C, VCC = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
suppression. This eliminates the need for a T
SP and VHYS specifications are due to Schmitt trigger inputs which provide noise and spike
I specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
1996 Microchip Technology Inc. DS21127B-page 3
24LCS21
2.0 FUNCTIONAL DESCRIPTION
The 24LCS21 operates in two modes, the
Transmit-Only Mode and the bi-directional Mode. There
is a separate two wire protocol to support each mode,
each having a separate clock input but sharing a common data line (SDA). The device enters the Transmit-Only Mode upon power-up. In this mode, the device
transmits data bits on the SDA pin in response to a
clock signal on the VCLK pin. The device will remain in
this mode until a valid high to low transition is placed on
the SCL input. When a valid transition on SCL is recognized, the device will switch into the bi-directional
Mode. The only way to switch the device back to the
Transmit-Only Mode is to remove power from the
device.
2.1 Transmit-Only Mode
The device will power up in the Transmit-Only Mode at
address 00H. This mode supports a unidirectional two
wire protocol for continuous transmission of the
contents of the memory array. This device requires that
it be initialized prior to valid data being sent in the Transmit-Only Mode (see Initialization Procedure, below). In
FIGURE 2-1: TRANSMIT ONLY MODE
this mode, data is transmitted on the SDA pin in 8-bit
bytes, with each byte followed by a ninth, null bit
(Figure 2-1). The clock source for the Transmit-Only
Mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each
byte are transmitted most significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the internal address pointers will wrap around to the
first memory location (00H) and continue. The bi-directional Mode Clock (SCL) pin must be held high for the
device to remain in the Transmit-Only Mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the
Transmit-Only Mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit in address
00h. (Figure 2-2).
SCL
TVAA TVAA
SDA
Bit 1 (LSB)
VCLK
TVLOWTVHIGH
FIGURE 2-2: DEVICE INITIALIZATION
Vcc
SCL
SDA
TVPU
Null Bit
Bit 1 (MSB) Bit 7
TVAA TVAA
Bit 8 Bit 7High Impedance for 9 clock cycles
VCLK
DS21127B-page 4 1996 Microchip Technology Inc.
12 891011
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