Microchip Technology Inc 24FC32T-I-P, 24FC32T-P, 24FC32-I-SM, 24FC32-I-P, 24FC32-SM Datasheet



1996 Microchip Technology Inc. DS21126B-page 3-1

FEATURES

• Voltage operating range: 4.5V to 5.5V

- Maximum write current 3 mA at 5.5V

- Maximum read current 150 µ A at 5.5V

- Standby current 1 µ A typical

• 1 MHz SE2.bus two wire protocol

• Self-timed write cycle (including auto-erase)

• Power on/off data protection circuitry

• Endurance:

- 10,000,000 Erase/Write cycles guaranteed
for a 4K block

- 1,000,000 E/W cycles guaranteed for a 28K
block

• 8-byte page, or byte modes available

• 1 page x 8 line input cache (64 bytes) for fast write
loads

• Schmitt trigger inputs for noise suppression

• 2 ms typical write cycle time, byte or page

• Up to 8 chips may be connected to the same bus
for up to 256K bits total memory

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP/SOIC packages

• Temperature ranges

DESCRIPTION

The Microchip T echnology Inc. 24FC32 is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM (EEPROM) with
a high-speed 1 MHz SE2.bus whose protocol is
functionally equivalent to the industry-standard I

2

C bus.
This device has been developed for advanced, low
power applications such as personal communications
or data acquisition. The 24FC32 features an input
cache for fast write loads with a capacity of eight 8-byte
pages, or 64 bytes. It also features a fixed 4K-bit block
of ultra-high endurance memory for data that changes
frequently. The 24FC32 is capable of both random and
sequential reads up to the 32K boundary. Functional
address lines allow up to 8 - 24FC32 devices on the
same bus, for up to 256K bits address space. The
24FC32 is available in the standard 8-pin plastic DIP
and 8-pin surface mount SOIC package.

- Commercial (C): 0˚C to +70˚C

- Industrial (I): -40˚C to +85˚C

P ACKA GE TYPES

BLOCK DIAGRAM

24FC32

SOIC

1
2
3
4

8
7
6
5

V

CC

NC
SCL
SDA

A0
A1
A2

V

SS

24FC32

PDIP

1
2
3
4

8
7
6
5

VCC
NC
SCL
SDA

A0
A1
A2

V

SS

I/O

CONTROL

LOGIC

EEPROM

ARRAY

PAGE LATCHES

HV GENERATOR

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

XDEC

YDEC

VCC

VSS

I/O

SCL

A0..A2

CACHE

SDA

24FC32

32K 5.0V 1 MHz I

2

C



Smart Serial



EEPROM

I

2

C is a trademark of Philips Corporation.

Smart Serial is a trademark of Microchip Technology Inc.

24FC32

DS21126B-page 3-2



1996 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

..................................................................................7.0V

All inputs and outputs w.r.t. V

SS

...............-0.6V to V

CC

+1.0V

Storage temperature..................................... -65˚C to +150˚C

Ambient temp. with power applied................ -65˚C to +125˚C

Soldering temperature of leads (10 seconds)............. +300˚C

ESD protection on all pins ..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

A0..A2 User Configurable Chip Selects

V

SS

Ground
SDA Serial Address/Data I/O
SCL Serial Clock

V

CC

+4.5V to 5.5V Power Supply

NC

No Internal Connection

TABLE 1-2: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

V

CC

= +4.5V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C

Parameter Symbol Min Max Units Conditions

A0, A1, A2, SCL and SDA pins:

High level input voltage V

IH

0.7 Vcc — V

Low level input voltage V

IL

— 0.3 Vcc V

Hysteresis of SCL and SDA V

HYS

0.05 Vcc — V (Note 1)

Low level output voltage of SDA V

OL

— 0.40 V I

OL

= 3.0 mA

Input leakage current I

LI

-10 10

µ

AV

IN

= 0.1V

TO

V

CC

Output leakage current I

LO

-10 10

µ

AV

OUT

= 0.1V to V

CC

Pin capacitance
(all inputs/outputs)

C

INT

—10pFV

CC

= 5.0V (Note 1)

Tamb = 25˚C, Fclk = 1 MHz

Operating current I

CC

W

RITE

I

CC

Read

—
—

3

150

mA

µ

A

V

CC

= 5.5V, SCL = 1 MHz

V

CC

= 5.5V, SCL = 1 MHz

Standby current I

CCS

—5

(1 typical)

µ

AV

CC

= 5.5V,

SCL = SDA = V

CC

(Note 1)

Note 1: This parameter is periodically sampled and not 100% tested.

TSU:STA

THD:STA

VHYS

TSU:STO

START STOP

SCL

SDA



1996 Microchip Technology Inc. DS21126B-page 3-3

24FC32

TABLE 1-3: AC CHARACTERISTICS

FIGURE 1-2: BUS TIMING DATA

Parameter Symbol

1 MHz Bus

Units Remarks

Min Max

Clock frequency F

CLK

0 1000 kHz

Clock high time T

HIGH

500 — ns

Clock low time T

LOW

500 — ns

SDA and SCL rise time T

R

— 300 ns (Note 1)

SDA and SCL fall time T

F

— 100 ns (Note 1)

START condition hold time T

HD

:

STA

250 — ns After this period the first clock pulse is generated

START condition setup time T

SU

:

STA

250 — ns Only relevant for repeated START condition

Data input hold time T

HD

:

DAT

0—ns

Data input setup time T

SU

:

DAT

100 — ns

STOP condition setup time T

SU

:

STO

250 — ns

Output valid from clock T

AA

— 350 ns (Note 2)

Bus free time T

BUF

500 — ns Time the bus must be free before a new trans-

mission can start

Write cycle time T

WR

— 5 ms/page Note 3

Endurance

High Endurance Block
Rest of Array

—
—

10M

1M

—
—

10M

1M

25

°

C, Vcc = 5.0V, Block Mode (Note 4)

Note 1: Not 100 percent tested.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 100 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write

cache for total time.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

SCL

SDA
IN

SDA
OUT

TSU:STA

TSP

TAA

TF

TLOW

THIGH

THD:STA

THD:DAT

TSU:DAT

TSU:STO

TBUF

TAA

TR

24FC32

DS21126B-page 3-4



1996 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

The 24FC32 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24FC32 works
as slave. Both master and slave can operate as
transmitter or receiver but the master device
determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Star

t Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.

3.3 Stop Data

Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4 Data

Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.

3.5 Ac

knowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.

A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account.
During reads, a master must signal an end of data to
the slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24FC32) will leave the data line HIGH
to enable the master to generate the STOP condition.

Note: The 24FC32 does not generate any

acknowledge bits if an internal
programming cycle is in progress.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A) (B) (D) (D) (C) (A)

START CONDITION ADDRESS

OR

ACKNOWLEDGE

VALID

DATA ALLOWED

TO CHANGE

STOP

CONDITION