Microchip Technology Inc 24C02SC-WF08, 24C02SC-WF, 24C02SC-W08, 24C02SC-W, 24C02SC-S08 Datasheet
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C
24C01SC/02SC
1K/2K 5.0V I
2
C Serial EEPROMs for Smart Cards
FEATURES
• ISO Standard 7816 pad locations
• Low power CMOS technology
- 1 mA active current typical
- 10 µ A standby current typical at 5.5V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)
• Two-wire serial interface bus, I
• 100 kHz and 400 kHz compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• ESD protection > 4 kV
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• Available for extended temperature ranges
- Commercial (C): 0 ° C to +70 ° C
2
compatible
DESCRIPTION
The Microchip Technology Inc. 24C01SC and
24C02SC are 1K-bit and 2K-bit Electrically Erasable
PROMs with bondpad positions optimized for smart
card applications. The devices are organized as a single block of 128 x 8-bit or 256 x 8-bit memory with a
two-wire serial interface. The 24C01SC and 24C02SC
also have page-write capability for up to 8 b ytes of data.
DIE LAYOUT
V
SS
SDA
DC
BLOCK DIAGRAM
I/O
CONTROL
LOGIC
SDA SCL
VCC
VSS
MEMORY
CONTROL
LOGIC
XDEC
CC
V
SCL
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
2
I
C is a trademark of Philips Corporation.
1996 Microchip Technology Inc.
Preliminary
DS21170A-page 1
24C01SC/02SC
µ
µ
µ
1.0 ELECTRICAL CHARACTERISTICS
Maximum Ratings*
CC
V
........................................................................7.0V
All inputs and outputs w.r.t. V
Storage temperature...........................-65˚C to +150˚C
Ambient temp. with power applied.......-65˚C to +125˚C
ESD protection on all pads .....................................≥ 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2: DC CHARACTERISTICS
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pads:
High level input voltage V
Low level input voltage V
Hysteresis of Schmidt trigger inputs V
Low level output voltage V
Input leakage current (SCL) I
Output leakage current (SDA) I
Pin capacitance (all inputs/outputs) C
Operating current I
Standby current I
......-0.6V to V
SS
+1.0V
CC
V
CC
= +4.5V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C
IH
IL
HYS
OL
LI
LO
IN
,
C
OUT
CC
Write — 3 mA V
CC
I
Read — 1 mA Vcc = 5.5V, SCL = 400 KHz
CCS
TABLE 1-1: PAD FUNCTION TABLE
Name Function
SS
V
SDA
SCL
CC
V
DC
.7 V
CC
— .3 V
.05 V
CC
——
CC
— V (Note)
— .40 V I
-10 10
-10 10
—10pFV
— 100
Ground
Serial Address/Data I/O
Serial Clock
+4.5V to 5.5V Power Supply
Don’t connect
V
= 3.0 mA, V
OL
AV
IN
= .1V to 5.5V
OUT
AV
= .1V to 5.5V
CC
= 5.0V (Note 1)
Tamb = 25˚C, F
CC
= 5.5V
CC
AV
= 5.5V, SDA = SCL = V
= 4.5V
CC
CLK
= 1 MHz
CC
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL
SU:STA
T
SDA
DS21170A-page 2
START STOP
THD:STA
Preliminary
TSU:STO
1996 Microchip Technology Inc.
TABLE 1-3: AC CHARACTERISTICS
Parameter Symbol Min. Max. Units Remarks
24C01SC/02SC
Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T
START condition setup time T
Data input hold time T
Data input setup time T
STOP condition setup time T
HD
SU
HD
SU
SU
Output valid from clock T
Bus free time T
Output fall time from V
minimum to V
IL
Input filter spike suppression
IH
maximum
T
T
(SDA and SCL pins)
CLK
HIGH
LOW
R
F
:
STA
:
STA
DAT
:
:
DAT
:
STO
AA
BUF
OF
SP
— 400 kHz
600 — ns
1300 — ns
— 300 ns (Note 1)
— 300 ns (Note 1)
600 — ns After this period the first clock
pulse is generated
600 — ns Only relevant for repeated
START condition
0 — ns (Note 2)
100 — ns
600 — ns
— 900 ns (Note 2)
1300 — ns Time the bus must be free
before a new transmission can
start
20 +0.1
250 ns (Note 1), CB ≤ 100 pF
CB
— 50 ns (Note 3)
Write cycle time T
Endurance —
WR
— 10 ms Byte or Page mode
10
6
— cycles 25 ° C, Vcc = 5V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed b y characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA
TR
TBUFTAA
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
T
HD:STA
THIGH
TSU:STOTSU:DATTHD:DAT
THD:STA
1996 Microchip Technology Inc.
Preliminary
DS21170A-page 3
24C01SC/02SC
2.0 FUNCTIONAL DESCRIPTION
The 24C01SC/02SC supports a bi-directional two-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the
24C01SC/02SC works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the b us is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 24C01SC/02SC does not generate
any acknowledge bits if an internal programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge cloc k pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the sla ve. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(
A) (B) (D) (D) (C) (A)
SCL
SDA
START
CONDITION
DS21170A-page 4
ADDRESS OR
ACKNOWLEDGE
VALID
Preliminary
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
1996 Microchip Technology Inc.
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