MICROCHIP PIC18F2450, PIC18F4450 DATA SHEET

PIC18F2450/4450

Data Sheet

28/40/44-Pin, High-Performance,

12 MIPS, Enhanced Flash,

USB Microcontrollers with

nanoWatt Technology

© 2006 Microchip Technology Inc. Advance Information DS39760A

Note the following details of the code protection feature on Microchip devices:

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• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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Information contained in this publication regarding device
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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

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PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
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© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEEL

®

OQ

code hopping

DS39760A-page ii Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash,

USB Microcontrollers with nanoWatt Technology

Universal Serial Bus Features:

• USB V2.0 Compliant

• Low speed (1.5 Mb/s) and full speed (12 Mb/s)

• Supports control, interrupt, isochronous and

bulk transfers

• Supports up to 32 endpoints (16 bidirectional)

• 256-byte dual access RAM for USB

• On-chip USB transceiver with on-chip voltage

regulator

• Interface for off-chip USB transceiver

Power-Managed Modes:

• Run: CPU on, peripherals on

• Idle: CPU off, peripherals on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 μA typical

• Sleep mode currents down to 0.1 μA typical

• Timer1 oscillator: 1.8 μA typical, 32 kHz, 2V

• Watchdog Timer: 2.1 μA typical

• Two-Speed Oscillator Start-up

Flexible Oscillator Structure:

• Four Crystal modes, including High-Precision PLL

for USB

• Two External Clock modes, up to 48 MHz

• Internal 31 kHz oscillator

• Secondary oscillator using Timer1 @ 32 kHz

• Dual oscillator options allow microcontroller and

USB module to run at different clock speeds

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if any clock stops

Peripheral Highlights:

• High-current sink/source: 25 mA/25 mA

• Three external interrupts

• Three Timer modules (Timer0 to Timer2)

• Capture/Compare/PWM (CCP) module:

- Capture is 16-bit, max. resolution 5.2 ns

- Compare is 16-bit, max. resolution 83.3 ns

- PWM output: PWM resolution is 1 to 10-bit

• Enhanced USART module:

- LIN bus support

• 10-bit, up to 13-channel Analog-to-Digital Converter
module (A/D):

- Up to 100 ksps sampling rate

- Programmable acquisition time

Special Microcontroller Features:

• C compiler optimized architecture with optional
extended instruction set

• Flash memory retention: > 40 years

• Self-programmable under software control

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Programmable Code Protection

• Single-Supply In-Circuit Serial Programming™
(ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Optional dedicated ICD/ICSP port
(44-pin TQFP devices only)

• Wide operating voltage range (2.0V to 5.5V)

Program Memory Data

Device

PIC18F2450 16K 8192 768* 23 10 1 1 1/2

PIC18F4450 16K 8192 768* 34 13 1 1 1/2

* Includes 256 bytes of dual access RAM used by USB module and shared with data memory.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 1

Flash

(bytes)

# Single-Word

Instructions

Memory

SRAM

(bytes)

I/O

10-Bit A/D

(ch)

CCP EUSART

Timers

8/16-Bit

PIC18F2450/4450

Pin Diagrams

28-Pin SDIP, SOIC

28-Pin QFN

MCLR/VPP/RE3

RA0/AN0
RA1/AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI/RCV

RA5/AN4/HLVDIN

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/UOE

REF-

REF+

V

OSC1/CLKI

RC2/CCP1

USB

V

1
2
3
4
5
6
7

SS

8
9
10
11
12
13
14

PIC18F2450

/VPP/RE3

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1
RB0/AN12/INT0
V

DD

VSS
RC7/RX/DT
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM

RA2/AN2/VREF-

RA3/AN3/V

RA4/T0CKI/RCV

RA5/AN4/HLVDIN

OSC2/CLKO/RA6

REF+

V

OSC1/CLKI

SS

Note: Pinouts are subject to change.

RA0/AN0

RA1/AN1

1
2
3

PIC18F2450

4
5
6
7

10 11

8

9

RC1/T1OSI/UOE

RC0/T1OSO/T1CKI

MCLR

RB7/KBI3/PGD

12 13 14

USB

V

RC2/CCP1

RB6/KBI2/PGC

RC4/D-/VM

RB5/KBI1/PGM

RB4/AN11/KBI0

22

232425262728

RC5/D+/VP

21
20
19
18
17
16
15

RC6/TX/CK

RB3/AN9/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1
RB0/AN12/INT0
V

DD

VSS
RC7/RX/DT

DS39760A-page 2 Advance Information © 2006 Microchip Technology Inc.

Pin Diagrams (Continued)

40-Pin PDIP

PIC18F2450/4450

44-Pin QFN

MCLR/VPP/RE3

RA0/AN0
RA1/AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI/RCV

RA5/AN4/HLVDIN

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/UOE

REF-

REF+

RE0/AN5
RE1/AN6
RE2/AN7

V
VSS

OSC1/CLKI

RC2/CCP1

V

USB

RD0
RD1

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PIC18F4450

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/VPO
RB2/AN8/INT2/VMO

RB1/AN10/INT1
RB0/AN12/INT0
V

DD

VSS
RD7
RD6

RD5
RD4
RC7/RX/DT
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3
RD2

RC7/RX/DT

RD4
RD5
RD6
RD7

V

SS

AVDD

RB0/AN12/INT0
RB1/AN10/INT1

RB2/AN8/INT2/VMO

VDD

Note: Pinouts are subject to change.

1
2
3
4
5
6
7
8
9
10
11

RC6/TX/CK

44

121314

RB3/AN9/VPO

RC5/D+/VP

RC4/D-/VM

RD3

RD2

RD1

RD0

414039

42

43

38

PIC18F4450

1819202122

15

16

17

NC

/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/AN11/KBI0

MCLR

USB

V

37

RA0/AN0

RC2/CCP1

RC1/T1OSI/UOE

363435

REF-

RA1/AN1

RA2/AN2/V

RC0/T1OSO/T1CKI

33
32
31
30
29
28
27
26
25
24
23

REF+

RA3/AN3/V

OSC2/CLKO/RA6
OSC1/CLKI
V

SS

AV SS
VDD
AV DD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/HLVDIN
RA4/T0CKI/RCV

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 3

PIC18F2450/4450

Pin Diagrams (Continued)

44-Pin TQFP

RC7/RX/DT

RD4
RD5
RD6
RD7

VSS

RB0/AN12/INT0
RB1/AN10/INT1

RB2/AN8/INT2/VMO

RB3/AN9/VPO

VDD

1
2
3
4
5
6
7
8
9
10
11

RC6/TX/CK

44

121314

RD0

RD1

RD2

RD3

RC4/D-/VM

RC5/D+/VP

414039

42

43

38

PIC18F4450

1819202122

15

16

17

USB

V

37

RC1/T1OSI/UOE

RC2/CCP1

363435

NC/ICPORTS*

33
32
31
30
29
28
27
26
25
24
23

NC/ICRST*/ICVPP*
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
V

SS

VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/HLVDIN
RA4/T0CKI/RCV

/VPP/RE3

RB6/KBI2/PGC

RB7/KBI3/PGD

RB5/KBI1/PGM

RB4/AN11/KBI0

NC/ICDT*/ICPGD*

NC/ICCK*/ICPGC*

MCLR

Note: Pinouts are subject to change.

* Assignment of this feature is dependent on device configuration.

RA0/AN0

RA1/AN1

REF-

RA2/AN2/V

RA3/AN3/VREF+

DS39760A-page 4 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Oscillator Configurations ............................................................................................................................................................ 23

3.0 Power-Managed Modes ............................................................................................................................................................. 33

4.0 Reset.......................................................................................................................................................................................... 41

5.0 Memory Organization ................................................................................................................................................................. 53

6.0 Flash Program Memory.............................................................................................................................................................. 73

7.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 83

8.0 Interrupts.................................................................................................................................................................................... 85

9.0 I/O Ports ..................................................................................................................................................................................... 99

10.0 Timer0 Module ......................................................................................................................................................................... 111

11.0 Timer1 Module ......................................................................................................................................................................... 115

12.0 Timer2 Module ......................................................................................................................................................................... 121

13.0 Capture/Compare/PWM (CCP) Module ................................................................................................................................... 123

14.0 Universal Serial Bus (USB) ...................................................................................................................................................... 129

15.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART) ....................................................................................... 153

16.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 173

17.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 183

18.0 Special Features of the CPU.................................................................................................................................................... 189

19.0 Instruction Set Summary .......................................................................................................................................................... 211

20.0 Development Support............................................................................................................................................................... 261

21.0 Electrical Characteristics .......................................................................................................................................................... 265

22.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 293

23.0 Packaging Information.............................................................................................................................................................. 295

Appendix A: Revision History............................................................................................................................................................. 303

Appendix B: Device Differences ........................................................................................................................................................ 303

Appendix C: Conversion Considerations ........................................................................................................................................... 304

Appendix D: Migration From Baseline to Enhanced Devices ............................................................................................................ 304

Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 305

Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 305

Index ................................................................................................................................................................................................. 307

The Microchip Web Site..................................................................................................................................................................... 315

Customer Change Notification Service .............................................................................................................................................. 315

Customer Support .............................................................................................................................................................................. 315

Reader Response .............................................................................................................................................................................. 316

PIC18F2450/4450 Product Identification System .............................................................................................................................. 317

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 5

PIC18F2450/4450

TO OUR VALUED CUSTOMERS

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DS39760A-page 6 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC18F2450 • PIC18F4450

This family of devices offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price – with the addition of
high endurance, Enhanced Flash program memory. In
addition to these features, the PIC18F2450/4450 family
introduces design enhancements that make these micro­controllers a logical choice for many high-performance,
power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2450/4450 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:

• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.

• On-the-Fly Mode Switching: The power­managed modes are invoked by user code during
operation, allowing the user to incorporate power­saving ideas into their application’s software
design.

• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 21.0 “Electrical Characteristics” for
values.

1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2450/4450 family offer
twelve different oscillator options, allowing users a wide
range of choices in developing application hardware.
These include:

• Four Crystal modes using crystals or ceramic

resonators.

• Four External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).

• An INTRC source (approximately 31 kHz, stable

over temperature and V
oscillator pin for use as an additional general
purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and
External Oscillator modes, which allows a wide
range of clock speeds from 4 MHz to 48 MHz.

• Asynchronous dual clock operation, allowing the

USB module to run from a high-frequency
oscillator while the rest of the microcontroller is
clocked from an internal low-power oscillator.

The internal oscillator provides a stable reference
source that gives the family additional features for
robust operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a
reference signal provided by the internal
oscillator. If a clock failure occurs, the controller is
switched to the internal oscillator, allowing for
continued low-speed operation or a safe
application shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.

DD). This option frees an

1.1.2 UNIVERSAL SERIAL BUS (USB)

Devices in the PIC18F2450/4450 family incorporate a
fully featured Universal Serial Bus communications
module that is compliant with the USB Specification
Revision 2.0. The module supports both low-speed and
full-speed communication for all supported data
transfer types. It also incorporates its own on-chip
transceiver and 3.3V regulator and supports the use of
external transceivers and voltage regulators.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 7

PIC18F2450/4450

1.2 Other Special Features

• Memory Endurance: The Enhanced Flash cells
for program memory are rated to last for many
thousands of erase/write cycles – up to 100,000.

• Self-Programmability: These devices can write
to their own program memory spaces under
internal software control. By using a bootloader
routine, located in the protected Boot Block at the
top of program memory, it becomes possible to
create an application that can update itself in the
field.

• Extended Instruction Set: The PIC18F2450/
4450 family introduces an optional extension to
the PIC18 instruction set, which adds 8 new
instructions and an Indexed
Literal Offset Addressing mode. This extension,
enabled as a device configuration option, has
been specifically designed to optimize re-entrant
application code originally developed in high-level
languages such as C.

• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
Automatic Baud Rate Detection and a 16-bit Baud
Rate Generator for improved resolution.

• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated, without waiting for a sampling period and
thus, reducing code overhead.

• Dedicated ICD/ICSP Port: These devices
introduce the use of debugger and programming
pins that are not multiplexed with other micro­controller features. Offered as an option in select
packages, this feature allows users to develop I/O
intensive applications while retaining the ability to
program and debug in the circuit.

1.3 Details on Individual Family Members

Devices in the PIC18F2450/4450 family are available
in 28-pin and 40/44-pin packages. Block diagrams for
the two groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in the
following two ways:

1. A/D channels (10 for 28-pin devices, 13 for

40/44-pin devices).

2. I/O ports (3 bidirectional ports and 1 input only

port on 28-pin devices, 5 bidirectional ports on
40/44-pin devices).

All other features for devices in this family are identical.
These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and
Table 1-3.

Like all Microchip PIC18 devices, members of the
PIC18F2450/4450 family are available as both standard
and low-voltage devices. Standard devices with
Enhanced Flash memory, designated with an “F” in the
part number (such as PIC18F2450), accommodate an
operating V
designated by “LF” (such as PIC18LF2450), function
over an extended VDD range of 2.0V to 5.5V.

DD range of 4.2V to 5.5V. Low-voltage parts,

DS39760A-page 8 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

TABLE 1-1: DEVICE FEATURES

Features PIC18F2450 PIC18F4450

Operating Frequency DC – 48 MHz DC – 48 MHz

Program Memory (Bytes) 16384 16384

Program Memory (Instructions) 8192 8192

Data Memory (Bytes) 768 768

Interrupt Sources 13 13

I/O Ports Ports A, B, C, (E) Ports A, B, C, D, E

Timers 3 3

Capture/Compare/PWM Modules 1 1

Enhanced USART 1 1

Universal Serial Bus (USB) Module 1 1

10-bit Analog-to-Digital Module 10 Input Channels 13 Input Channels

Resets (and Delays) POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow (PWRT, OST),

(optional),

MCLR

WDT

Programmable Low-Voltage Detect Yes Yes

Programmable Brown-out Reset Yes Yes

Instruction Set 75 Instructions;

83 with Extended Instruction Set

enabled

Packages 28-pin PDIP

28-pin SOIC

Stack Underflow (PWRT, OST),

83 with Extended Instruction Set

POR, BOR,

RESET Instruction,

Stack Full,

MCLR (optional),

WDT

75 Instructions;

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 9

PIC18F2450/4450

FIGURE 1-1: PIC18F2450 (28-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

Instruction Bus <16>

(2)

OSC1

(2)

OSC2

T1OSI

T1OSO

(1)

MCLR

VDD,

SS

V

USB

V

20

8

Table Latch

ROM Latch

Instruction

Internal

Oscillator

Block

INTRC

Oscillator

Single-Supply
Programming

In-Circuit

Debugger

PCLATH

PCLATU

PCH PCL

PCU

Program Counter

31 Level Stack

STKPTR

IR

Decode &

Control

Start-up Timer

Clock Monitor

USB Voltage

Regulator

Data Bus<8>

8

8

State Machine
Control Signals

Power-up

Time r

Oscillator

Power-on

Reset

Watchdog

Time r

Brown-out

Reset

Fail-Safe

Data Latch

Data Memory

(2 Kbytes)

Address Latch

12

Data Address<12>

44

12

FSR0
FSR1
FSR2

logic

8 x 8 Multiply

W

8

ALU<8>

Access

Bank

PRODLPRODH

8

8

12

8

BSR

3

BITOP

Band Gap

Reference

8

inc/dec

Address

Decode

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF­RA3/AN3/VREF+
RA4/T0CKI/RCV
RA5/AN4/HLVDIN
OSC2/CLKO/RA6

PORTB

RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2/VMO
RB3/AN9/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

PORTC

8

8

8

PORTE

RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT

MCLR/VPP/RE3

(1)

BOR

HLVD

CCP1

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer

to Section 2.0 “Oscillator Configurations” for additional information.

EUSART

Timer2Timer1Timer0

ADC

10-bit

USB

DS39760A-page 10 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

FIGURE 1-2: PIC18F4450 (40/44-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

20

8

PCLATH

PCLATU

PCU

Program Counter

31 Level Stack

STKPTR

Table Latch

Data Bus<8>

8

PCH PCL

8

Data Latch

Data Memory

(2 Kbytes)

Address Latch

12

Data Address<12>

BSR

FSR0
FSR1

Access

Bank

12

44

FSR2

inc/dec

logic

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF­RA3/AN3/VREF+
RA4/T0CKI/RCV
RA5/AN4/HLVDIN
OSC2/CLKO/RA6

PORTB

RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2/VMO
RB3/AN9/VPO

12

RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

Instruction Bus <16>

VDD,

VSS

(2)

OSC1

(2)

OSC2

T1OSI

T1OSO

(3)

ICPGC

(3)

ICPGD

(3)

ICPORTS

(3)

ICRST

(1)

MCLR

USB

V

ROM Latch

IR

Instruction

Decode &

Internal

Oscillator

Block

INTRC

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

Control

USB Voltage

Regulator

State Machine
Control Signals

Power-up

Time r

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Time r

Brown-out

Reset

Fail-Safe

Clock Monitor

3

BITOP

8

Band Gap
Reference

Address
Decode

8 x 8 Multiply

8

ALU<8>

PORTC

RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
RC2/CCP1
RC4/D-/VM

RC5/D+/VP

8

RC6/TX/CK
RC7/RX/DT

PRODLPRODH

PORTD

8

W

8

8

8

RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7

8

PORTE

RE0/AN5
RE1/AN6
RE2/AN7
MCLR/VPP/RE3

(1)

BOR

HLVD

CCP1

Note 1: RE3 is multiplexed with MCLR

EUSART

ADC

10-bit

and is only available when the MCLR Resets are disabled.

Timer2Timer1Timer0

USB

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer

to Section 2.0 “Oscillator Configurations” for additional information.

3: These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 18.9 “Special ICPORT Features (Designated

Packages Only)” for additional information.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 11

PIC18F2450/4450

TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

/Vpp/RE3

MCLR

MCLR

VPP
RE3

OSC1/CLKI

OSC1
CLKI

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

PDIP,

QFN

SOIC

1

96

10 7

26

Pin

Buffer

Typ e

I

P

I

IIAnalog

Analog

O

O

I/O

Type

ST

ST

—

—

TTL

Description

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.

DS39760A-page 12 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/VREF-

RA2
AN2

REF-

V

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI/RCV

RA4
T0CKI
RCV

RA5/AN4/HLVDIN

RA5
AN4
HLVDIN

RA6 — — — — See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

REF+

REF+

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

PDIP,
SOIC

227

328

41

52

63

74

QFN

Pin

Buffer

Typ e

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

TTL

I

Analog

I

Analog

I/O

TTL

I

Analog

I

Analog

I/O

I
I

TTL

I/O

TTL

I

Analog

I

Analog

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.

ST
ST

Digital I/O.
Timer0 external clock input.
External USB transceiver RCV input.

Digital I/O.
Analog input 4.
High/Low-Voltage Detect input.

Description

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 13

PIC18F2450/4450

TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/AN12/INT0

RB0
AN12
INT0

RB1/AN10/INT1

RB1
AN10
INT1

RB2/AN8/INT2/VMO

RB2
AN8
INT2
VMO

RB3/AN9/VPO

RB3
AN9
VPO

RB4/AN11/KBI0

RB4
AN11
KBI0

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

PDIP,
SOIC

21 18

22 19

23 20

24 21

25 22

26 23

27 24

28 25

QFN

Pin

Typ e

I/O

I
I

I/O

I
I

I/O

I
I

O

I/O

I

O

I/O

I
I

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

Buffer

Type

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

—

TTL

Analog

—

TTL

Analog

TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.
Analog input 12.
External interrupt 0.

Digital I/O.
Analog input 10.
External interrupt 1.

Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.

Digital I/O.
Analog input 9.
External USB transceiver VPO output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

DS39760A-page 14 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/UOE

RC1
T1OSI
UOE

RC2/CCP1

RC2
CCP1

RC4/D-/VM

RC4
D­VM

RC5/D+/VP

RC5
D+
VP

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

RE3 — — — — See MCLR

VUSB 14 11 O — Internal USB 3.3V voltage regulator.

VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.

DD 20 17 P — Positive supply for logic and I/O pins.

V

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

PDIP,
SOIC

11 8

12 9

13 10

15 12

16 13

17 14

18 15

QFN

Pin

Buffer

Typ e

Type

I/O

O

I

I/O

I

CMOS

—

I/O
I/OSTST

I

I/O

I

I

I/O

O

I/O

O

I/O

I/O

I

I/O

PORTC is a bidirectional I/O port.

ST

—

ST

ST

—

TTL

—

TTL

TTL

—

TTL

ST

—

ST

ST
ST
ST

Digital I/O.
Timer1 oscillator output.
Timer1external clock input.

Digital I/O.
Timer1 oscillator input.
External USB transceiver OE

Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.

Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.

Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).

/VPP/RE3 pin.

Description

output.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 15

PIC18F2450/4450

TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS

Pin Name

/Vpp/RE3

MCLR

MCLR

VPP
RE3

OSC1/CLKI

OSC1
CLKI

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

11818

13 32 30

14 33 31

Pin

Buffer

Typ e

I

P

I

IIAnalog

Analog

O

O

I/O

Type

Master Clear (input) or programming voltage (input).

ST

ST

—

—

TTL

Configuration bit is cleared.

Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.

Description

DS39760A-page 16 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/VREF-

RA2
AN2

REF-

V

RA3/AN3/VREF+

RA3
AN3

REF+

V

RA4/T0CKI/RCV

RA4
T0CKI
RCV

RA5/AN4/HLVDIN

RA5
AN4
HLVDIN

RA6 — — — — — See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

21919

32020

42121

52222

62323

72424

Pin

Buffer

Typ e

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

I

Analog

I

Analog

I/O

I

Analog

I

Analog

I/O

I
I

I/O

I

Analog

I

Analog

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

TTL

TTL

ST
ST

TTL

TTL

Configuration bit is cleared.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.

Digital I/O.
Timer0 external clock input.
External USB transceiver RCV input.

Digital I/O.
Analog input 4.
High/Low-Voltage Detect input.

Description

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 17

PIC18F2450/4450

TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/AN12/INT0

RB0
AN12
INT0

RB1/AN10/INT1

RB1
AN10
INT1

RB2/AN8/INT2/VMO

RB2
AN8
INT2
VMO

RB3/AN9/VPO

RB3
AN9
VPO

RB4/AN11/KBI0

RB4
AN11
KBI0

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

33 9 8

34 10 9

35 11 10

36 12 11

37 14 14

38 15 15

39 16 16

40 17 17

Pin

Typ e

I/O

I
I

I/O

I
I

I/O

I
I

O

I/O

I

O

I/O

I
I

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

Buffer

Type

PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

—

TTL

Analog

—

TTL

Analog

TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Configuration bit is cleared.

Digital I/O.
Analog input 12.
External interrupt 0.

Digital I/O.
Analog input 10.
External interrupt 1.

Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.

Digital I/O.
Analog input 9.
External USB transceiver VPO output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

Description

DS39760A-page 18 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/UOE

RC1
T1OSI
UOE

RC2/CCP1

RC2
CCP1

RC4/D-/VM

RC4
D­VM

RC5/D+/VP

RC5
D+
VP

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

15 34 32

16 35 35

17 36 36

23 42 42

24 43 43

25 44 44

26 1 1

Pin

Buffer

Typ e

I/O

O

I

I/O

I

CMOS

O

I/O
I/OSTST

I

I/O

I

I

I/O

I

I/O

O

I/O

I/O

I

I/O

Type

PORTC is a bidirectional I/O port.

ST

—

ST

ST

—

TTL

—

TTL

TTL

—

TTL

ST

—

ST

ST
ST
ST

Configuration bit is cleared.

Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.

Digital I/O.
Timer1 oscillator input.
External USB transceiver OE

Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.

Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.

Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).

Description

output.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 19

PIC18F2450/4450

TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0 19 38 38 I/O ST Digital I/O.

RD1 20 39 39 I/O ST Digital I/O.

RD2 21 40 40 I/O ST Digital I/O.

RD3 22 41 41 I/O ST Digital I/O.

RD4 27 2 2 I/O ST Digital I/O.

RD5 28 3 3 I/O ST Digital I/O.

RD6 29 4 4 I/O ST Digital I/O.

RD7 30 5 5 I/O ST Digital I/O.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

Pin

Typ e

Buffer

Type

PORTD is a bidirectional I/O port.

Configuration bit is cleared.

Description

DS39760A-page 20 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/AN5

RE0
AN5

RE1/AN6

RE1
AN6

RE2/AN7

RE2
AN7

RE3 — — — — — See MCLR

VSS 12, 31 6, 30, 316, 29 P — Ground reference for logic and I/O pins.

V

DD 11, 32 7, 8,

USB 18 37 37 O — Internal USB 3.3V voltage regulator output.

V

NC/ICCK/ICPGC

ICCK
ICPGC

NC/ICDT/ICPGD

ICDT
ICPGD

NC/ICRST

ICRST
ICVPP

NC/ICPORTS

ICPORTS

NC — 13 — — — No Connect.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

(1)

(1)

(1)

/ICVPP

(1)

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

82525

92626

10 27 27

7, 28 P — Positive supply for logic and I/O pins.

28, 29

——12

——13

——33

— — 34 P — No Connect or 28-pin device emulation.

Pin

Buffer

Typ e

I/OIST

Analog

I/OIST

Analog

I/OIST

Analog

I/O
I/OSTST

I/O
I/OSTST

I

P

Type

PORTE is a bidirectional I/O port.

Digital I/O.
Analog input 5.

Digital I/O.
Analog input 6.

Digital I/O.
Analog input 7.

/VPP/RE3 pin.

No Connect or dedicated ICD/ICSP™ port clock.

In-Circuit Debugger clock.
ICSP programming clock.

No Connect or dedicated ICD/ICSP port clock.

In-Circuit Debugger data.
ICSP programming data.

No Connect or dedicated ICD/ICSP port Reset.
—
—

Configuration bit is cleared.

Master Clear (Reset) input.
Programming voltage input.

Enable 28-pin device emulation when connected

SS.

to V

Description

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 21

PIC18F2450/4450

NOTES:

DS39760A-page 22 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

2.0 OSCILLATOR CONFIGURATIONS

2.1 Overview

Devices in the PIC18F2450/4450 family incorporate a
different oscillator and microcontroller clock system
than the non-USB PIC18F devices. The addition of the
USB module, with its unique requirements for a stable
clock source, make it necessary to provide a separate
clock source that is compliant with both USB low-speed
and full-speed specifications.

To accommodate these requirements, PIC18F2450/
4450 devices include a new clock branch to provide a
48 MHz clock for full-speed USB operation. Since it is
driven from the primary clock source, an additional
system of prescalers and postscalers has been added
to accommodate a wide range of oscillator frequencies.
An overview of the oscillator structure is shown in
Figure 2-1.

Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal RC oscillator and
clock switching, remain the same. They are discussed
later in this chapter.

2.1.1 OSCILLATOR CONTROL

The operation of the oscillator in PIC18F2450/4450
devices is controlled through two Configuration
registers and two control registers. Configuration
registers, CONFIG1L and CONFIG1H, select the
oscillator mode and USB prescaler/postscaler options.
As Configuration bits, these are set when the device is
programmed and left in that configuration until the
device is reprogrammed.

The OSCCON register (Register 2-1) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control

Register”.

2.2 Oscillator Types

PIC18F2450/4450 devices can be operated in twelve
distinct oscillator modes. In contrast with the non-USB
PIC18 enhanced microcontrollers, four of these modes
involve the use of two oscillator types at once. Users
can program the FOSC3:FOSC0 Configuration bits to
select one of these modes:

1. XT Crystal/Resonator

2. XTPLL Crystal/Resonator with PLL enabled

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator
with PLL enabled

5. EC External Clock with F

6. ECIO External Clock with I/O on RA6

7. ECPLL External Clock with PLL enabled
and F

OSC/4 output on RA6

8. ECPIO External Clock with PLL enabled,
I/O on RA6

9. INTHS Internal Oscillator used as
microcontroller clock source, HS
Oscillator used as USB clock source

10. INTXT Internal Oscillator used as
microcontroller clock source, XT
Oscillator used as USB clock source

11. INTIO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
digital I/O on RA6

12. INTCKO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
FOSC/4 output on RA6

OSC/4 output

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 23

PIC18F2450/4450

2.2.1 OSCILLATOR MODES AND USB OPERATION

Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
previous PICmicro
clocks were driven by a single oscillator source; the usual
sources were primary, secondary or the internal
oscillator. With PIC18F2450/4450 devices, the primary
oscillator becomes part of the USB module and cannot
be associated to any other clock source. Thus, the USB
module must be clocked from the primary clock source;

®

devices, all core and peripheral

however, the microcontroller core and other peripherals
can be separately clocked from the secondary or internal
oscillators as before.

Because of the timing requirements imposed by USB,
an internal clock of either 6 MHz or 48 MHz is required
while the USB module is enabled. Fortunately, the
microcontroller and other peripherals are not required
to run at this clock speed when using the primary
oscillator. There are numerous options to achieve the
USB module clock requirement and still provide
flexibility for clocking the rest of the device from the
primary oscillator source. These are detailed in

Section 2.3 “Oscillator Settings for USB”.

FIGURE 2-1: PIC18F2450/4450 CLOCK DIAGRAM

PIC18F2450/4450

PLLDIV

÷ 12

111

÷ 10

110

÷ 6

101

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

XT, HS, EC, ECIO

Secondary Oscillator

T1OSCEN
Enable
Oscillator

PLL Prescaler

Oscillator Postscaler

÷ 5
÷ 4
÷ 3

÷ 2
÷ 1

÷ 4

÷ 3

÷ 2
÷ 1

CPUDIV

11

10

01

00

100

011

010

001

000

MUX

HSPLL, ECPLL,

XTPLL, ECPIO

(4 MHz Input Only)

OSCCON<6:4>

96 MHz

PLL

PLL Postscaler

÷ 6
÷ 4

÷ 3
÷ 2

÷ 2

CPUDIV

11

10

01

00

FOSC3:FOSC0

USB Clock Source

USBDIV

0

1

÷ 4

1
0

Primary
Clock

T1OSC

Internal Oscillator

MUX

FSEN

1

0

IDLEN

USB

Peripheral

CPU

Peripherals

Clock

Internal RC Oscillator

31.25

kHz

FOSC3:FOSC0

Control

OSCCON<1:0>

Clock Source Option
for other Modules

WDT, PWRT, FSCM
and Two-Speed Start-up

DS39760A-page 24 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

2.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In HS, HSPLL, XT and XTPLL Oscillator modes, a
crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-2
shows the pin connections.

The oscillator design requires the use of a parallel cut
crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s
specifications.

FIGURE 2-2: CRYSTAL/CERAMIC

RESONATOR OPERATION
(XT, HS OR HSPLL
CONFIGURATION)

(1)

C1

(1)

C2

Note 1: See Table 2-1 and Table 2-2 for initial values of

C1 and C2.

2: A series resistor (R

strip cut crystals.

3: R

OSC1

To

Internal

XTAL

(2)

RS

OSC2

F varies with the oscillator mode chosen.

(3)

RF

PIC18FXXXX

S) may be required for AT

Logic

Sleep

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 4.0 MHz 33 pF 33 pF

HS 8.0 MHz

16.0 MHz

Capacitor values are for design guidance only.

These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.

Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V

See the notes following Table 2-2 for additional
information.

Resonators Used:

16.0 MHz

4.0 MHz

8.0 MHz

27 pF
22 pF

27 pF
22 pF

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc Type

Crystal

Freq

XT 4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed
below for basic start-up and operation. These values

are not optimized.

Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V

See the notes following this table for additional
information.

Crystals Used:

Note 1: Higher capacitance increases the stability

of oscillator but also increases the start­up time.

2: When operating below 3V V

using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.

5: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPUDIV Con­figuration bits. Users may select a clock frequency of
the oscillator frequency, or 1/2, 1/3 or 1/4 of the
frequency.

An external clock may also be used when the micro­controller is in HS Oscillator mode. In this case, the
OSC2/CLKO pin is left open (Figure 2-3).

Typical Capacitor Values

Test ed:

C1 C2

4 MHz

8 MHz

20 MHz

DD, or when

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 25

PIC18F2450/4450

FIGURE 2-3: EXTERNAL CLOCK INPUT

OPERATION (HS OSC
CONFIGURATION)

Clock from
Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.2.3 EXTERNAL CLOCK INPUT

The EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external clock source to be connected to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleep
mode.

In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK

INPUT OPERATION
(EC AND ECPLL
CONFIGURATION)

2.2.4 PLL FREQUENCY MULTIPLIER

PIC18F2450/4450 devices include a Phase Locked
Loop (PLL) circuit. This is provided specifically for USB
applications with lower speed oscillators and can also
be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there are
eight prescaling options to match the oscillator input
frequency to the PLL.

There is also a separate postscaler option for deriving
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds. In contrast to the postscaler for XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6
of the PLL output.

The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The prescaler divides the oscillator input by up to 12 to
produce the 4 MHz drive for the PLL. The XTPLL mode
can only use an input frequency of 4 MHz which drives
the PLL directly.

Clock from
Ext. System

OSC/4

F

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

The ECIO and ECPIO Oscillator modes function like the
EC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The I/O
pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows
the pin connections for the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK

INPUT OPERATION
(ECIO AND ECPIO
CONFIGURATION)

Clock from
Ext. System

RA6

The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

FIGURE 2-6: PLL BLOCK DIAGRAM

(HS MODE)

HS/EC/ECIO/XT Oscillator Enable

(from CONFIG1H Register)

OSC2

Oscillator

OSC1

and

Prescaler

PLL Enable

Phase

Comparator

IN

F

FOUT

÷24

Loop
Filter

VCO

SYSCLK

MUX

DS39760A-page 26 Advance Information © 2006 Microchip Technology Inc.

PIC18F2450/4450

2.2.5 INTERNAL OSCILLATOR

The PIC18F2450/4450 devices include an internal RC
oscillator (INTRC) which provides a nominal 31 kHz out­put. INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in
Section 18.0 “Special Features of the CPU”.

2.2.5.1 Internal Oscillator Modes

When the internal oscillator is used as the micro­controller clock source, one of the other oscillator
modes (External Clock or External Crystal/Resonator)
must be used as the USB clock source. The choice of
USB clock source is determined by the particular
internal oscillator mode.

There are four distinct modes available:

1. INTHS mode: The USB clock is provided by the

oscillator in HS mode.

2. INTXT mode: The USB clock is provided by the

oscillator in XT mode.

3. INTCKO mode: The USB clock is provided by an

external clock input on OSC1/CLKI; the OSC2/
CLKO pin outputs F

4. INTIO mode: The USB clock is provided by an

external clock input on OSC1/CLKI; the OSC2/
CLKO pin functions as a digital I/O (RA6).

Of these four modes, only INTIO mode frees up an
additional pin (OSC2/CLKO/RA6) for port I/O use.

OSC/4.

2.3 Oscillator Settings for USB

When the PIC18F2450/4450 is used for USB
connectivity, it must have either a 6 MHz or 48 MHz
clock for USB operation, depending on whether Low­Speed or Full-Speed mode is being used. This may
require some forethought in selecting an oscillator
frequency and programming the device.

The full range of possible oscillator configurations
compatible with USB operation is shown in Table 2-3.

2.3.1 LOW-SPEED OPERATION

The USB clock for Low-Speed mode is derived from
the primary oscillator chain and not directly from the
PLL. It is divided by 4 to produce the actual 6 MHz
clock. Because of this, the microcontroller can only use
a clock frequency of 24 MHz when the USB module is
active and the controller clock source is one of the
primary oscillator modes (XT, HS or EC, with or without
the PLL).

This restriction does not apply if the microcontroller
clock source is the secondary oscillator or internal
oscillator.

2.3.2 RUNNING DIFFERENT USB AND MICROCONTROLLER CLOCKS

The USB module, in either mode, can run
asynchronously with respect to the microcontroller core
and other peripherals. This means that applications can
use the primary oscillator for the USB clock while the
microcontroller runs from a separate clock source at a
lower speed. If it is necessary to run the entire
application from only one clock source, full-speed
operation provides a greater selection of microcontroller
clock frequencies.

© 2006 Microchip Technology Inc. Advance Information DS39760A-page 27

PIC18F2450/4450

TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION

Input Oscillator

Frequency

48 MHz N/A

48 MHz ÷12 (111) EC, ECIO None (00)48MHz

40 MHz ÷10 (110) EC, ECIO None (00)40MHz

24 MHz ÷6 (101) HS, EC, ECIO None (00) 24 MHz

20 MHz ÷5 (100) HS, EC, ECIO None (00)20MHz

16 MHz ÷4 (011) HS, EC, ECIO None (00)16MHz

Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).

Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,

USB clock of 6 MHz).

Note 1: Only valid when the USBDIV Configuration bit is cleared.

PLL Division

(PLLDIV2:PLLDIV0)

(1)

Clock Mode

(FOSC3:FOSC0)

EC, ECIO None (00)48MHz

ECPLL, ECPIO ÷2 (00)48MHz

ECPLL, ECPIO ÷2 (00)48MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

MCU Clock Division
(CPUDIV1:CPUDIV0)

÷2 (01) 24 MHz
÷3 (10)16MHz
÷4 (11)12MHz

÷2 (01) 24 MHz
÷3 (10)16MHz
÷4 (11)12MHz

÷3 (01)32MHz
÷4 (10) 24 MHz
÷6 (11)16MHz

÷2 (01)20MHz
÷3 (10) 13.33 MHz
÷4 (11)10MHz

÷3 (01)32MHz
÷4 (10) 24 MHz
÷6 (11)16MHz

01)12MHz

÷2 (
÷3 (10)8MHz
÷4 (11)6MHz

÷3 (01)32MHz
÷4 (10) 24 MHz
÷6 (11)16MHz

÷2 (01)10MHz
÷3 (10)6.67MHz
÷4 (11)5MHz

÷3 (01)32MHz
÷4 (10) 24 MHz
÷6 (11)16MHz

÷2 (01)8MHz
÷3 (10)5.33MHz
÷4 (11)4MHz

÷3 (01)32MHz
÷4 (10) 24 MHz

)16MHz

÷6 (11

Microcontroller

Clock Frequency

DS39760A-page 28 Advance Information © 2006 Microchip Technology Inc.