MICROCHIP PIC18F2XX0 Technical data

PIC18F2XX0/2X21/2XX5/

4XX0/4X21/4XX5

Flash Microcontroller Programming Specification

1.0 DEVICE OVERVIEW

This document includes the programming specifications
for the following devices:

• PIC18F2221 • PIC18F4221

• PIC18F2321 • PIC18F4321

• PIC18F2410 • PIC18F4410

• PIC18F2420 • PIC18F4420

• PIC18F2455 • PIC18F4455

• PIC18F2480 • PIC18F4480

• PIC18F2510 • PIC18F4510

• PIC18F2515 • PIC18F4515

• PIC18F2520 • PIC18F4520

• PIC18F2525 • PIC18F4525

• PIC18F2550 • PIC18F4550

• PIC18F2580 • PIC18F4580

• PIC18F2585 • PIC18F4585

• PIC18F2610 • PIC18F4610

• PIC18F2620 • PIC18F4620

• PIC18F2680 • PIC18F4680

2.0 PROGRAMMING OVERVIEW

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5 devices
can be programmed using either the high-voltage
In-Circuit Serial Programming™ (ICSP™) method or
the low-voltage ICSP method. Both methods can be
done with the device in the users’ system. The
low-voltage ICSP method is slightly different than the
high-voltage method and these differences are noted
where applicable. This programming specification
applies to PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5
devices in all package types.

2.1 Hardware Requirements

In High-Voltage ICSP mode, PIC18F2XX0/2X21/2XX5/
4XX0/4X21/4XX5 devices require two programmable
power supplies: one for VDD and one for MCLR/VPP/
RE3. Both supplies should have a minimum resolution
of 0.25V. Refer to Section 6.0 “AC/DC Characteris-

tics Timing Requirements for Program/Verify Test
Mode” for additional hardware parameters.

2.1.1 LOW-VOLTAGE ICSP PROGRAMMING

In Low-Voltage ICSP mode, PIC18F2XX0/2X21/2XX5/
4XX0/4X21/4XX5 devices can be programmed using a
VDD source in the operating range. The MCLR/VPP/
RE3 does not have to be brought to a different voltage,
but can instead be left at the normal operating voltage.
Refer to Section 6.0 “AC/DC Characteristics Timing
Requirements for Program/Verify Test Mode” for
additional hardware parameters.

2.2 Pin Diagrams

The pin diagrams for the PIC18F2XX0/2X21/2XX5/
4XX0/4X21/4XX5 family are shown in Figure 2-1 and
Figure 2-2.

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING):

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

Pin Name

MCLR

/VPP/RE3 VPP P Programming Enable

(2)

DD

V

(2)

V

SS

RB5 PGM I Low-Voltage ICSP™ Input when LVP

RB6 PGC I Serial Clock

RB7 PGD I/O Serial Data

Legend: I = Input, O = Output, P = Power
Note 1: See Figure 5-1

2: All power supply (V

© 2005 Microchip Technology Inc. DS39622E-page 1

Pin Name Pin Type Pin Description

VDD P Power Supply

VSS P Ground

for more information.

DD) and ground (VSS) pins must be connected.

During Programming

Configuration bit equals ‘1’

(1)

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

FIGURE 2-1: PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5 FAMILY PIN DIAGRAMS

28-Pin SDIP, SOIC (300 MIL)

RB7/PGD
RB6/PGC
RB5/PGM

RB4
RB3
RB2
RB1
RB0

V

DD

VSS

RC7
RC6
RC5
RC4

The following devices are included in
28-pin SDIP and SOIC parts:

• PIC18F2221 • PIC18F2520

• PIC18F2321 • PIC18F2525

• PIC18F2410 • PIC18F2550

• PIC18F2420 • PIC18F2580

• PIC18F2455 • PIC18F2585

• PIC18F2480 • PIC18F2610

• PIC18F2510 • PIC18F2620

• PIC18F2515 • PIC18F2680

MCLR/VPP/RE3

RA0
RA1
RA2
RA3
RA4
RA5

V

OSC1
OSC2

RC0
RC1
RC2
RC3

PIC18F2XXX

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6

SS

7
8
9

10
11

12
13
14

28-Pin QFN

The following devices are included in
28-pin QFN parts:

• PIC18F2221 • PIC18F2480

• PIC18F2321 • PIC18F2510

• PIC18F2410 • PIC18F2520

• PIC18F2420 • PIC18F2580

40-Pin PDIP (600 MIL)

The following devices are included in
40-pin PDIP parts:

• PIC18F4221 • PIC18F4520

• PIC18F4321 • PIC18F4525

• PIC18F4410 • PIC18F4550

• PIC18F4420 • PIC18F4580

• PIC18F4455 • PIC18F4585

• PIC18F4480 • PIC18F4610

• PIC18F4510 • PIC18F4620

• PIC18F4515 • PIC18F4680

RA2
RA3
RA4
RA5

V

OSC1
OSC2

MCLR/VPP/RE3

RA0
RA1

RA2
RA3
RA4
RA5
RE0
RE1
RE2

V

DD

VSS

OSC1
OSC2

RC0
RC1
RC2
RC3
RD0
RD1

/VPP/RE3

RB7/PGD

RB6/PGC

RB5/PGM

232425262728

12 13 14

RC4

RC3

PIC18F4XXX

22

RC5

RB4

21
20
19
18
17
16
15

RC6

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22
21

RB3
RB2
RB1
RB0

V

DD

VSS

RC7

RB7/PGD
RB6/PGC
RB5/PGM

RB4
RB3
RB2

RB1
RB0

V

DD

VSS

RD7
RD6
RD5
RD4
RC7
RC6
RC5

RC4
RD3

RD2

RA0

RA1

MCLR

1
2

PIC18F2X21

3

PIC18F24X0

SS

4
5

PIC18F25X0

6
7

10 11

8

9

RC0

RC1

1

2

3

4

5

6

7

8

9
10

11

12

13
14

15

16

17

18

19
20

RC2

DS39622E-page 2 © 2005 Microchip Technology Inc.

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

FIGURE 2-2: PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5 FAMILY PIN DIAGRAMS

/ICPORTS

44-Pin TQFP

The following devices are included in
40-pin TQFP parts:

• PIC18F4221 • PIC18F4515

• PIC18F4321 • PIC18F4525

• PIC18F4410 • PIC18F4550

• PIC18F4420 • PIC18F4580

• PIC18F4455 • PIC18F4585

• PIC18F4480 • PIC18F4610

• PIC18F4510 • PIC18F4620

• PIC18F4520 • PIC18F4680

RC7
RD4
RD5
RD6

RD7

V

SS

VDD

RB0
RB1
RB2
RB3

1
2
3
4
5
6
7
8
9
10
11

RC6

RC5

44

43

121314

RC4

RD3

RD2

RD1

414039

42

PIC18F4XXX

15

16

17

(1)

RD0

RC3

RC2

RC1

363435

37

38

1819202122

NC

33
32
31
30
29
28
27
26
25
24
23

(1)

NC

RC0
OSC2
OSC1

V

SS

VDD

RE2
RE1
RE0
RA5
RA4

/ICVPP

Note 1: These pins are NC (No Connect) for all devices listed

above with the exception of the PIC18F4221,
PIC18F4321, PIC18F4455 and the PIC18F4550
devices (see Section 2.8 “Dedicated ICSP/ICD
Port (44-Pin TQFP Only)” for more information on
programming these pins in these devices).

44-Pin QFN

The following devices are included in
44-pin QFN parts:

• PIC18F4221 • PIC18F4515

• PIC18F4321 • PIC18F4525

• PIC18F4410 • PIC18F4550

• PIC18F4420 • PIC18F4580

• PIC18F4455 • PIC18F4585

• PIC18F4480 • PIC18F4610

• PIC18F4510 • PIC18F4620

• PIC18F4520 • PIC18F4680

RC7
RD4
RD5
RD6
RD7

V

AVDD

VDD

RB0
RB1
RB2

SS

/ICPGC

/ICPGD

(1)

(1)

NC

NC

RC6

D+/VP

44

43

1
2
3
4
5

PIC18F4XXX

6
7
8
9
10
11

121314

RB4

RB5/PGM

D-/VM

RD3

414039

42

RB6/PGC

RD2

16

15

RA0

/VPP/RE3

RB7/PGD

MCLR

USB

RD1

RD0

V

37

38

17

1819202122

RA1

RC2

363435

RA2

RC1

RA3

RC0

33
32
31
30
29
28
27
26
25
24

23

OSC2
OSC1

V

SS

AVSS
VDD
AVDD

RE2
RE1
RE0
RA5

RA4

NC

RB3

RB4

RB5/PGM

RB6/PGC

RB7/PGD

RA0

RA3

RA2

RA1

/VPP/RE3

MCLR

© 2005 Microchip Technology Inc. DS39622E-page 3

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

2.3 Memory Maps

TABLE 2-2: IMPLEMENTATION OF CODE

For PIC18FX6X0 devices, the code memory space
extends from 0000h to 0FFFFh (64 Kbytes) in four
16-Kbyte blocks. For PIC18FX5X5 devices, the code
memory space extends from 0000h to 0BFFFFh
(48 Kbytes) in three 16-Kbyte blocks. Addresses
0000h through 07FFh, however, define a “Boot Block”
region that is treated separately from Block 0. All of
these blocks define code protection boundaries within
the code memory space.

The size of the Boot Block in PIC18F2585/2680/4585/
4680 devices can be configured as 1, 2 or 4K words
(see Table 5-1). This is done through the BBSIZ<1:0>
bits in the Configuration register, CONFIG4L. It is
important to note that increasing the size of the Boot
Block decreases the size of Block 0.

Device Code Memory Size (Bytes)

PIC18F2515

PIC18F2525

PIC18F2585

PIC18F4515

PIC18F4525

PIC18F4585

PIC18F2610

PIC18F2620

PIC18F2680

PIC18F4610

PIC18F4620

PIC18F4680

FIGURE 2-3: MEMORY MAP AND THE CODE MEMORY SPACE

FOR PIC18FX5X5/X6X0 DEVICES

000000h

01FFFFh

Code Memory

64 Kbytes

(PIC18FX6X0)

MEMORY SIZE/DEVICE

MEMORY

000000h-00BFFFh (48K)

000000h-00FFFFh (64K)

48 Kbytes

(PIC18FX5X5)

Address

Range

200000h

3FFFFFh

Unimplemented

Read as ‘0’

Configuration

and ID

Space

11/10 01 00

Boot

Block*

Block 0

Boot

Block*

Block 0

Boot

Block*

Block 0

Block 1

Block 1

Block 2

Block 3

Unimplemented

Reads all ‘0’s

BBSIZ<1:0>

11/10 01 00

Boot

Block*

Block 0

Unimplemented

Reads all ‘0’s

Boot

Block*

Block 0

Block 1

Block 2

Boot

Block*

Block 0

000000h

0007FFh
000800h

000FFFh
001000h

001FFFh
002000h

003FFFh
004000h

007FFFh
008000h

00BFFFh
00C000h

00FFFFh

01FFFFh

Note: Sizes of memory areas are not to scale.

* Boot Block size is determined by the BBSIZ1:BBSIZ0 bits in CONFIG4L.

DS39622E-page 4 © 2005 Microchip Technology Inc.

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

For PIC18FX5X0 devices, the code memory space

TABLE 2-3: IMPLEMENTATION OF CODE

extends from 000000h to 007FFFh (32 Kbytes) in four
8-Kbyte blocks. For PIC18FX4X5 devices, the code
memory space extends from 000000h to 005FFFh
(24 Kbytes) in three 8-Kbyte blocks. Addresses
000000h through 0007FFh, however, define a “Boot
Block” region that is treated separately from Block 0. All
of these blocks define code protection boundaries
within the code memory space.

Device Code Memory Size (Bytes)

PIC18F2455

PIC18F4455

PIC18F2510

PIC18F2520

PIC18F2550

PIC18F4510

PIC18F4520

PIC18F4550

FIGURE 2-4: MEMORY MAP AND THE CODE MEMORY SPACE

FOR PIC18FX4X5/X5X0 DEVICES

000000h

1FFFFFh

200000h

Code Memory

Unimplemented

Read as ‘0’

MEMORY SIZE/DEVICE

32 Kbytes

(PIC18FX5X0)

Boot Block Boot Block

Block 0 Block 0

Block 1 Block 1

Block 2 Block 2

Block 3

008000h

MEMORY

000000h-005FFFh (24K)

000000h-007FFFh (32K)

24 Kbytes

(PIC18FX4X5)

Address

Range

000000h
0007FFh

000800h
001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

Configuration

and ID

Space

3FFFFFh

Note: Sizes of memory areas are not to scale.

© 2005 Microchip Technology Inc. DS39622E-page 5

Unimplemented

Reads all ‘0’s

Unimplemented

Reads all ‘0’s

1FFFFFh

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

For PIC18FX4X0 devices, the code memory space

TABLE 2-4: IMPLEMENTATION OF CODE

extends from 000000h to 003FFFh (16 Kbytes) in two
8-Kbyte blocks. Addresses 000000h through 0003FFh,
however, define a “Boot Block” region that is treated
separately from Block 0. All of these blocks define code
protection boundaries within the code memory space.

Device Code Memory Size (Bytes)

PIC18F2410

PIC18F2420

PIC18F4410

PIC18F4420

FIGURE 2-5: MEMORY MAP AND THE CODE MEMORY SPACE

FOR PIC18FX4X0 DEVICES

000000h

1FFFFFh

Code Memory

Unimplemented

Read as ‘0’

MEMORY SIZE/DEVICE

16 Kbytes

(PIC18FX4X0)

Boot Block

Block 0

Block 1

MEMORY

000000h-003FFFh (16K)

Address

Range

000000h
0007FFh

000800h
001FFFh

002000h

003FFFh

004000h

200000h

Configuration

and ID

Space

3FFFFFh

Note: Sizes of memory areas are not to scale.

005FFFh

006000h

007FFFh

008000h

Unimplemented

Reads all ‘0’s

1FFFFFh

DS39622E-page 6 © 2005 Microchip Technology Inc.

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

For PIC18F2480/4480 devices, the code memory

TABLE 2-5: IMPLEMENTATION OF CODE

space extends from 0000h to 03FFFh (16 Kbytes) in
one 16-Kbyte block. For PIC18F2580/4580 devices,
the code memory space extends from 0000h to
07FFFh (32 Kbytes) in two 16-Kbyte blocks.
Addresses 0000h through 07FFh, however, define a
“Boot Block” region that is treated separately from
Block 0. All of these blocks define code protection
boundaries within the code memory space.

Device Code Memory Size (Bytes)

PIC18F2480

PIC18F4480

PIC18F2580

PIC18F4580

The size of the Boot Block in PIC18F2480/2580/4480/
4580 devices can be configured as 1 or 2K words (see
Table 5-1). This is done through the BBSIZ bit in the
Configuration register, CONFIG4L. It is important to
note that increasing the size of the Boot Block
decreases the size of Block 0.

FIGURE 2-6: MEMORY MAP AND THE CODE MEMORY SPACE

FOR PIC18F2480/2580/4480/4580 DEVICES

000000h

01FFFFh

Code Memory

Unimplemented

Read as ‘0’

32 Kbytes

(PIC18FX580)

10 1 0

Boot Block*

MEMORY SIZE/DEVICE

BBSIZ<0>

Boot Block*

Boot Block*

MEMORY

000000h-003FFFh (16K)

000000h-007FFFh (32K)

16 Kbytes

(PIC18FX480)

Boot Block*

Address

Range

000000h

0007FFh
000800h

000FFFh
001000h

Block 0 Block 0

200000h

Configuration

and ID

Space

3FFFFFh

Unimplemented

Reads all ‘0’s

Note: Sizes of memory areas are not to scale.

* Boot Block size is determined by the BBSIZ bit in CONFIG4L.

Block 2

Block 3

Block 0 Block 0

001FFFh
002000h

Block 1

003FFFh
004000h

005FFFh
006000h

Unimplemented

Reads all ‘0’s

007FFFh

01FFFFh

© 2005 Microchip Technology Inc. DS39622E-page 7

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

For PIC18F2221/4221 devices, the code memory

TABLE 2-6: IMPLEMENTATION OF CODE

space extends from 0000h to 00FFFh (4 Kbytes) in one
4-Kbyte block. For PIC18F2321/4321 devices, the
code memory space extends from 0000h to 01FFFh
(8 Kbytes) in two 4-Kbyte blocks. Addresses 0000h
through 07FFh, however, define a variable “Boot Block”
region that is treated separately from Block 0. All of
these blocks define code protection boundaries within
the code memory space.

Device Code Memory Size (Bytes)

PIC18F2221

PIC18F4221

PIC18F2321

PIC18F4321

The size of the Boot Block in PIC18F2221/2321/4221/
4321 devices can be configured as 256, 512 or
1024 words (see Figure 2-7). This is done through the
BBSIZ<1:0> bits in the Configuration register,
CONFIG4L (see Table 5-1). It is important to note that
increasing the size of the Boot Block decreases the
size of Block 0.

FIGURE 2-7: MEMORY MAP AND THE CODE MEMORY SPACE

FOR PIC18F2221/2321/4221/4321 DEVICES

MEMORY SIZE/DEVICE

000000h

01FFFFh

200000h

Code Memory

Unimplemented

Read as ‘0’

11/10 01 00 11/10/01 00

Boot Block*

1K word

Block 0

1K word

8Kbytes

(PIC18FX321)

Boot Block*

512 words

Block 0

1.5K words

BBSIZ<1:0>

Boot Block*

256 words

Block 0

1.75K words

MEMORY

4Kbytes

(PIC18FX221)

Boot Block*

512 words

Block 0

0.5K words

000000h-000FFFh (4K)

000000h-001FFFh (8K)

Address

Range

Boot Block*

256 words

Block 0

0.75K words

Block 1

1K word

000000h

0001FFh
000200h

0003FFh
000400h

0007FFh
000800h

000FFFh
001000h

Configuration

and ID

Space

3FFFFFh

Note: Sizes of memory areas are not to scale.

* Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L.

DS39622E-page 8 © 2005 Microchip Technology Inc.

Block 1

2K words

Unimplemented

Reads all ‘0’s

Unimplemented

Reads all ‘0’s

001FFFh
002000h

1FFFFFh

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

In addition to the code memory space, there are three
blocks that are accessible to the user through table
reads and table writes. Their locations in the memory
map are shown in Figure 2-8.

Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.

2.3.1 MEMORY ADDRESS POINTER

Memory in the address space, 0000000h to 3FFFFFh,
is addressed via the Table Pointer register, which is
comprised of three Pointer registers:

• TBLPTRU, at RAM address 0FF8h

• TBLPTRH, at RAM address 0FF7h

• TBLPTRL, at RAM address 0FF6h

Locations 300000h through 30000Dh are reserved for
the configuration bits. These bits select various device
options and are described in Section 5.0 “Configura-

TBLPTRU TBLPTRH TBLPTRL

Addr[21:16] Addr[15:8] Addr[7:0]

tion Word”. These configuration bits read out normally,
even after code protection.

Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits may be used by the program-

The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.

mer to identify what device type is being programmed
and are described in Section 5.0 “Configuration
Word”. These device ID bits read out normally, even
after code protection.

FIGURE 2-8: CONFIGURATION AND ID LOCATIONS FOR PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

DEVICES

000000h

01FFFFh

Code Memory

Unimplemented

Read as ‘0’

ID Location 1 200000h

ID Location 2 200001h

ID Location 3 200002h

ID Location 4 200003h

ID Location 5 200004h

ID Location 6 200005h

ID Location 7 200006h

ID Location 8 200007h

CONFIG1L 300000h

CONFIG1H 300001h

CONFIG2L 300002h

1FFFFFh

Configuration

and ID

Space

2FFFFFh

3FFFFFh

Note: Sizes of memory areas are not to scale.

© 2005 Microchip Technology Inc. DS39622E-page 9

CONFIG2H 300003h

CONFIG3L 300004h

CONFIG3H 300005h

CONFIG4L 300006h

CONFIG4H 300007h

CONFIG5L 300008h

CONFIG5H 300009h

CONFIG6L 30000Ah

CONFIG6H 30000Bh

CONFIG7L 30000Ch

CONFIG7H 30000Dh

Device ID1 3FFFFEh

Device ID2 3FFFFFh

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

2.4 High-Level Overview of the Programming Process

Figure 2-9 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the code memory, ID locations and data EEPROM
are programmed (selected devices only, see Section 3.3
“Data EEPROM Programming”). These memories are
then verified to ensure that programming was successful.
If no errors are detected, the configuration bits are then
programmed and verified.

FIGURE 2-9: HIGH-LEVEL

PROGRAMMING FLOW

Start

Perform Bulk

Erase

Program Memory

Program IDs

2.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode

As shown in Figure 2-10, the High-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low and then raising MCLR/VPP/RE3 to VIHH
(high voltage). Once in this mode, the code memory,
data EEPROM (selected devices only, see Section 3.3
“Data EEPROM Programming”), ID locations and
configuration bits can be accessed and programmed in
serial fashion. Figure 2-11 shows the exit sequence.

The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.

FIGURE 2-10: ENTERING HIGH-VOLTAGE

PROGRAM/VERIFY MODE

P13

P1

D110

MCLR/VPP/RE3

VDD

P12

Program Data EE

Verify Program

Verify IDs

Verify Data

Program

Configuration Bits

Verify

Configuration Bits

Done

Note 1: Selected devices only, see Section 3.3

“Data EEPROM Programming”.

(1)

PGD

PGC

PGD = Input

FIGURE 2-11: EXITING HIGH-VOLTAGE

PROGRAM/VERIFY MODE

P16

MCLR/VPP/RE3

D110

VDD

PGD

PGC

PGD = Input

P17

P1

DS39622E-page 10 © 2005 Microchip Technology Inc.

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

2.6 Entering and Exiting Low-Voltage ICSP Program/Verify Mode

When the LVP configuration bit is ‘1’ (see Section 5.3
“Single-Supply ICSP Programming”), the

Low-Voltage ICSP mode is enabled. As shown in
Figure 2-12, Low-Voltage ICSP Program/Verify mode
is entered by holding PGC and PGD low, placing a logic
high on PGM and then raising MCLR
In this mode, the RB5/PGM pin is dedicated to the
programming function and ceases to be a general
purpose I/O pin. Figure 2-13 shows the exit sequence.

The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.

FIGURE 2-12: ENTERING LOW-VOLTAGE

PROGRAM/VERIFY MODE

P15

MCLR/VPP/RE3

VDD

VIH

PGM

PGD

PGC

VIH

PGD = Input

FIGURE 2-13: EXITING LOW-VOLTAGE

PROGRAM/VERIFY MODE

P16

MCLR/VPP/RE3

VDD

PGM

PGD

PGC

VIH

PGD = Input

/VPP/RE3 to VIH.

P12

P18

VIH

2.7 Serial Program/Verify Operation

The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data input/
output during serial operation. Commands and data are
transmitted on the rising edge of PGC, latched on the
falling edge of PGC and are Least Significant bit (LSb)
first.

2.7.1 4-BIT COMMANDS

All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, PGC is cycled four times. The commands
needed for programming and verification are shown in
Ta bl e 2 -7 .

Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.

Throughout this specification, commands and data are
presented as illustrated in Table 2-8. The 4-bit
command is shown Most Significant bit (MSb) first. The
command operand, or “Data Payload”, is shown
<MSB><LSB>. Figure 2-14 demonstrates how to
serially present a 20-bit command/operand to the
device.

2.7.2 CORE INSTRUCTION

The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
registers as appropriate for use with other commands.

TABLE 2-7: COMMANDS FOR

PROGRAMMING

Description

Core Instruction
(Shift in16-bit instruction)

Shift out TABLAT register 0010

Table Read 1000

Table Read, post-increment 1001

Table Read, post-decrement 1010

Table Read, pre-increment 1011

Table Write 1100

Table Write, post-increment by 2 1101

Table Write, start programming,
post-increment by 2

Table Write, start programming 1111

TABLE 2-8: SAMPLE COMMAND

SEQUENCE

4-Bit

Command

1101 3C 40 Table Write,

Data

Payload

Core Instruction

post-increment by 2

4-Bit

Command

0000

1110

© 2005 Microchip Technology Inc. DS39622E-page 11

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

FIGURE 2-14: TABLE WRITE, POST-INCREMENT TIMING (1101)

PGC

PGD

P2

1234

P4

P3

1011

4-Bit Command 16-Bit Data Payload

P2A

P2B

1234

P5

000 000 01000111 1 0

04C3

5678

PGD = Input

2.8 Dedicated ICSP/ICD Port (44-Pin TQFP Only)

The PIC18F4221/4321 and PIC18F4455/4550 44-pin
TQFP devices are designed to support an alternate
programming input, the dedicated ICSP/ICD port. The
primary purpose of this port is to provide an alternate
In-Circuit Debugging (ICD) option and free the pins
(RB6, RB7 and MCLR
debugging the application. In conjunction with ICD
capability, however, the dedicated ICSP/ICD port also
provides an alternate port for ICSP.

Setting the ICPORT configuration bit enables the
dedicated ICSP/ICD port. The dedicated ICSP/ICD
port functions the same as the default ICSP/ICD port;
however, alternate pins are used instead of the default
pins. Table 2-9 identifies the functionally equivalent
pins for ICSP purposes:

The dedicated ICSP/ICD port is an alternate port. Thus,
ICSP is still available through the default port even
though the ICPORT configuration bit is set. When the

) that would normally be used for

10 11 13 15 161412

9

P5A

IH is seen on the MCLR/VPP/RE3 pin prior to applying

V

IH to the ICRST/ICVPP pin, then the state of the

V
ICRST/ICV
seen on ICRST/ICV

PP/RE3, then the state of the MCLR/VPP/RE3 pin is

V

PP pin is ignored. Likewise, when the VIH is

PP prior to applying VIH to MCLR/

234

1

nnnn

Fetch Next 4-Bit Command

ignored.

Note: The ICPORT configuration bit can only be

programmed through the default ICSP
port. Chip Erase functions through the
dedicated ICSP/ICD port do not affect this
bit.

When the ICPORT configuration bit is set
(dedicated ICSP/ICD port enabled), the
NC/ICPORTS pin must be tied to either

DD or VSS.

V

The ICPORT configuration bit must be
maintained clear for all 28-pin and 40-pin
devices; otherwise, unexpected operation
may occur.

TABLE 2-9: ICSP™ EQUIVALENT PINS

Pin Name

Pin Name Pin Type Dedicated Pin Pin Description

MCLR/VPP/RE3 VPP P NC/ICRST/ICVPP Programming Enable

RB6 PGC I NC/ICCK/ICPGC Serial Clock

RB7 PGD I/O NC/ICDT/ICPGD Serial Data

Legend: I = Input, O = Output, P = Power

DS39622E-page 12 © 2005 Microchip Technology Inc.

During Programming

PIC18F2XX0/2X21/2XX5/4XX0/4X21/4XX5

3.0 DEVICE PROGRAMMING

Programming includes the ability to erase or write the
various memory regions within the device.

In all cases except high-voltage ICSP Bulk Erase, the
EECON1 register must be configured in order to
operate on a particular memory region.

When using the EECON1 register to act on code
memory, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases) and this must be
done prior to initiating a write sequence. The FREE bit
must be set (EECON1<4> = 1) in order to erase the
program space being pointed to by the Table Pointer.
The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit only be set immediately prior to a
program erase.

3.1 ICSP Erase

3.1.1 HIGH-VOLTAGE ICSP BULK ERASE

Erasing code or data EEPROM is accomplished by
configuring two Bulk Erase Control registers located at
3C0004h and 3C0005h. Code memory may be erased
portions at a time, or the user may erase the entire
device in one action. Bulk Erase operations will also
clear any code-protect settings associated with the
memory block erased. Erase options are detailed in
Table 3-1. If data EEPROM is code-protected
(CPD = 0), the user must request an erase of data
EEPROM (e.g., 0084h as shown in Table 3-1).

The code sequence to erase the entire device is shown
in Table 3-2 and the flowchart is shown in Figure 3-1.

Note: A Bulk Erase is the only way to reprogram

code-protect bits from an ON state to an
OFF state.

TABLE 3-2: BULK ERASE COMMAND

SEQUENCE

4-Bit

Command

0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1100

0000
0000

Data

Payload

0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
0F 0F
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
87 87

00 00
00 00

Core Instruction

MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 0Fh to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 8787h TO 3C0004h
to erase entire
device.
NOP
Hold PGD low until
erase completes.

FIGURE 3-1: BULK ERASE FLOW

TABLE 3-1: BULK ERASE OPTIONS

Description

Chip Erase 0F87h

Erase Data EEPROM

Erase Boot Block 0081h

Erase Config Bits 0082h

Erase Code EEPROM Block 0 0180h

Erase Code EEPROM Block 1 0280h

Erase Code EEPROM Block 2 0480h

Erase Code EEPROM Block 3 0880h

Note 1: Selected devices only, see Section 3.3

“Data EEPROM Programming”.

The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PGC after the NOP command), serial execution
will cease until the erase completes (parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.

(1)

(3C0005h:3C0004h)

Data

0084h

Start

Write 0F0Fh

to 3C0005h

Write 8787h to

3C0004h to Erase

Entire Device

Delay P11 + P10

Time

Done

© 2005 Microchip Technology Inc. DS39622E-page 13