MICROCHIP PIC18F2682, PIC18F2685, PIC18F4682, PIC18F4685 DATA SHEET

PIC18F2682/2685/4682/4685

Data Sheet

28/40/44-Pin

Enhanced Flash Microcontrollers

with ECAN™ Technology, 10-Bit A/D

and nanoWatt Technology

© 2007 Microchip Technology Inc. Preliminary DS39761B

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

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dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
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© 2007, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC
MCUs and dsPIC® DSCs, KEEL
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

®

OQ

code hopping devices, Serial

DS39761B-page ii Preliminary © 2007 Microchip Technology Inc.

®

PIC18F2682/2685/4682/4685

28/40/44-Pin Enhanced Flash Microcontrollers with

ECAN™ Technology, 10-Bit A/D and nanoWatt Technology

Power-Managed Modes:

• Run: CPU on, peripherals on

• Idle: CPU off, peripherals on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 μA typical

• Sleep mode currents down to 0.1 μA typical

• Timer1 Oscillator: 1.1 μA, 32 kHz, 2V

• Watchdog Timer: 2.1 μA

• Two-Speed Oscillator Start-up

Flexible Oscillator Structure:

• Four Crystal modes, up to 40 MHz

• 4x Phase Lock Loop (PLL) – available for crystal

and internal oscillators

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal Oscillator Block:

- 8 user-selectable frequencies, from 31 kHz to 8 MHz

- Provides a complete range of clock speeds,
from 31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor

- Allows for safe shutdown if peripheral clock stops

Special Microcontroller Features:

• C compiler Optimized Architecture with optional
Extended Instruction Set

• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory typical

• 1,000,000 Erase/Write Cycle Data EEPROM
Memory typical

• Flash/Data EEPROM Retention: > 40 years

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

• Single-Supply 5V In-Circuit Serial
Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Wide operating voltage range: 2.0V to 5.5V

Peripheral Highlights:

• High-Current Sink/source 25 mA/25 mA

• Three External Interrupts

• One Capture/Compare/PWM (CCP1) module

• Enhanced Capture/Compare/PWM (ECCP1) module
(40/44-pin devices only):

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

• Master Synchronous Serial Port (MSSP) module
supporting 3-Wire SPI (all 4 modes) and I2C™
Master and Slave modes

• Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN 1.3

- RS-232 operation using internal oscillator

block (no external crystal required)

- Auto-wake-up on Start bit

- Auto-Baud Detect

• 10-Bit, up to 11-Channel Analog-to-Digital
Converter module (A/D), up to 100 ksps:

- Auto-acquisition capability

- Conversion available during Sleep

• Dual Analog Comparators with Input Multiplexing

ECAN Module Features:

• Message bit rates up to 1 Mbps

• Conforms to CAN 2.0B ACTIVE Specification

• Fully Backward Compatible with PIC18XXX8 CAN
modules

• Three Modes of Operation:

- Legacy, Enhanced Legacy, FIFO

• Three Dedicated Transmit Buffers with Prioritization

• Two Dedicated Receive Buffers

• Six Programmable Receive/Transmit Buffers

• Three Full, 29-Bit Acceptance Masks

• 16 Full, 29-Bit Acceptance Filters w/Dynamic
Association

• DeviceNet™ Data Byte Filter Support

• Automatic Remote Frame Handling

• Advanced Error Management Features

Program Memory Data Memory

Device

PIC18F2682 80K 40960 3328 1024 28 8 1/0 Y Y 1 0 1/3

PIC18F2685 96K 49152 3328 1024 28 8 1/0 Y Y 1 0 1/3

PIC18F4682 80K 40960 3328 1024 40/44 11 1/1 Y Y 1 2 1/3

PIC18F4685 96K 49152 3328 1024 40/44 11 1/1 Y Y 1 2 1/3

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 1

Flash

(bytes)

# Single-Word

Instructions

SRAM
(bytes)

EEPROM

(bytes)

I/O

10-Bit

A/D (ch)

CCP1/

ECCP1

(PWM)

SPI

MSSP

Master

I

2

C™

EUSART

Comp.

Timers

8/16-bit

PIC18F2682/2685/4682/4685

Pin Diagrams

28-Pin PDIP, SOIC

40-Pin PDIP

MCLR/VPP/RE3

RA0/AN0
RA1/AN1

RA2/AN2/V

RA3/AN3/V

RA5/AN4/SS

RA5/AN4/SS

RE1/WR

RE2/CS

RC0/T1OSO/T13CKI

RA4/T0CKI

/HLVDIN

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

MCLR/VPP/RE3

RA0/AN0/CV

RA1/AN1

RA2/AN2/V

RA3/AN3/V

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC3/SCK/SCL

RD0/PSP0/C1IN+

RD1/PSP1/C1IN-

REF+

RA4/T0CKI

/HLVDIN

RE0/RD

/AN5
/AN6/C1OUT
/AN7/C2OUT

RC1/T1OSI

RC2/CCP1

REF+

REF

REF-

V

DD

VSS

REF-

V

PIC18F4685

PIC18F2685

28
27
26
25
24
23
22
21
20
19
18
17
16
15

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN9
RB3/CANRX
RB2/INT2/CANTX
RB1/INT1/AN8
RB0/INT0/AN10
V

DD

VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN9
RB3/CANRX
RB2/INT2/CANTX

RB1/INT1/AN8
RB0/INT0/FLT0/AN10
V

DD

VSS
RD7/PSP7/P1D
RD6/PSP6/P1C

RD5/PSP5/P1B
RD4/PSP4/ECCP1/P1A
RC7/RX/DT
RC6/TX/CK
RC5/SDO

RC4/SDI/SDA
RD3/PSP3/C2IN-

RD2/PSP2/C2IN+

1
2
3
4
5
6

7

SS

8
9
10
11
12
13
14

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PIC18F2682

PIC18F4682

Note: Pinouts are subject to change.

DS39761B-page 2 Preliminary © 2007 Microchip Technology Inc.

Pin Diagrams (Continued)

44-Pin TQFP

PIC18F2682/2685/4682/4685

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3/C2IN-

RD2/PSP2/C2IN+

RD1/PSP1/C1IN-

RD0/PSP0/C1IN+

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI

NC

44-Pin QFN

RD4/PSP4/ECCP1/P1A

RB0/INT0/FLT0/AN10

RC7/RX/DT

RD5/PSP5/P1B
RD6/PSP6/P1C

RD7/PSP7/P1D

RB1/INT1/AN8

RB2/INT2/CANTX

V
VDD

RB3/CANRX

SS

4443424140

1
2
3

4
5
6
7
8
9
10
11

121314

NC

RC6/TX/CK

RC5/SDO

38

39

PIC18F4682
PIC18F4685

1819202122

15

16

17

NC

RB4/KBI0/AN9

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

MCLR/VPP/RE3

RC4/SDI/SDA

RD3/PSP3/C2IN-

RD2/PSP2/C2IN+

RD1/PSP1/C1IN-

RD0/PSP0/C1IN+

363435

37

REF

REF-

RA1/AN1

RA2/AN2/V

RA0/AN0/CV

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI

33
32
31
30
29
28
27
26
25
24
23

RA3/AN3/VREF+

RC0/T1OSO/T13CKI

NC
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7

SS

V
VDD
RE2/CS/AN7/C2OUT

/AN6/C1OUT

RE1/WR
RE0/RD

/AN5
RA5/AN4/SS
RA4/T0CKI

/HLVDIN

RD4/PSP4/ECCP1/P1A

RB0/INT0/FLT0/AN10

RC7/RX/DT

RD5/PSP5/P1B
RD6/PSP6/P1C

RD7/PSP7/P1D

RB1/INT1/AN8

RB2/INT2/CANTX

V

AVDD

VDD

4443424140

1
2
3
4

SS

5
6
7
8
9
10
11

121314

NC

RB3/CANRX

39

38

PIC18F4682
PIC18F4685

16

17

1819202122

15

RB4/KBI0/AN9

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

MCLR/VPP/RE3

37

REF

RA0/AN0/CV

363435

REF-

RA1/AN1

RA2/AN2/V

33
32
31
30
29
28
27
26
25
24
23

RA3/AN3/VREF+

OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

SS

AVSS
VDD

AVDD
RE2/CS/AN7/C2OUT

/AN6/C1OUT

RE1/WR
RE0/RD

/AN5
RA5/AN4/SS
RA4/T0CKI

/HLVDIN

Note: Pinouts are subject to change.

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 3

PIC18F2682/2685/4682/4685

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Oscillator Configurations ............................................................................................................................................................ 23

3.0 Power-Managed Modes ............................................................................................................................................................. 33

4.0 Reset .......................................................................................................................................................................................... 41

5.0 Memory Organization ................................................................................................................................................................. 61

6.0 Flash Program Memory.............................................................................................................................................................. 95

7.0 Data EEPROM Memory ........................................................................................................................................................... 105

8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 111

9.0 Interrupts .................................................................................................................................................................................. 113

10.0 I/O Ports ................................................................................................................................................................................... 129

11.0 Timer0 Module ......................................................................................................................................................................... 147

12.0 Timer1 Module ......................................................................................................................................................................... 151

13.0 Timer2 Module ......................................................................................................................................................................... 157

14.0 Timer3 Module ......................................................................................................................................................................... 159

15.0 Capture/Compare/PWM (CCP1) Modules ............................................................................................................................... 163

16.0 Enhanced Capture/Compare/PWM (ECCP1) Module .............................................................................................................. 173

17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 187

18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART) ....................................................................................... 227

19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 247

20.0 Comparator Module.................................................................................................................................................................. 257

21.0 Comparator Voltage Reference Module ................................................................................................................................... 263

22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 267

23.0 ECAN™ Technology ................................................................................................................................................................ 273

24.0 Special Features of the CPU.................................................................................................................................................... 343

25.0 Instruction Set Summary.......................................................................................................................................................... 363

26.0 Development Support............................................................................................................................................................... 413

27.0 Electrical Characteristics .......................................................................................................................................................... 417

28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 453

29.0 Packaging Information.............................................................................................................................................................. 455

Appendix A: Revision History............................................................................................................................................................. 463

Appendix B: Device Differences......................................................................................................................................................... 463

Appendix C: Conversion Considerations ........................................................................................................................................... 464

Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 464

Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 465

Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 465

Index .................................................................................................................................................................................................. 467

The Microchip Web Site..................................................................................................................................................................... 479

Customer Change Notification Service .............................................................................................................................................. 479

Customer Support .............................................................................................................................................................................. 479

Reader Response .............................................................................................................................................................................. 480

PIC18F2682/2685/4682/4685 Product Identification System ............................................................................................................ 481

DS39761B-page 4 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

TO OUR VALUED CUSTOMERS

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© 2007 Microchip Technology Inc. Preliminary DS39761B-page 5

PIC18F2682/2685/4682/4685

NOTES:

DS39761B-page 6 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC18F2682

• PIC18F2685

• PIC18F4682

• PIC18F4685

This family of devices offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price – with the addition
of high-endurance, Enhanced Flash program memory.
In addition to these features, the PIC18F2682/2685/
4682/4685 family introduces design enhancements that
make these microcontrollers a logical choice for many
high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2682/2685/4682/4685
family incorporate a range of features that can signifi­cantly reduce power consumption during operation.
Key items include:

• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.

• On-the-Fly Mode Switching: The power-
managed modes are invoked by user code during
operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.

• Lower Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer have been reduced by up to
80%, with typical values of 1.1 and 2.1 μA,
respectively.

• Extended Instruction Set: In addition to the
standard 75 instructions of the PIC18 instruction
set, PIC18F2682/2685/4682/4685 devices also
provide an optional extension to the core CPU
functionality. The added features include eight
additional instructions that augment indirect and
indexed addressing operations and the
implementation of Indexed Literal Offset
Addressing mode for many of the standard PIC18
instructions.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2682/2685/4682/4685
family offer ten different oscillator options, allowing
users a wide range of choices in developing application
hardware. These options include:

• Four Crystal modes, using crystals or ceramic

resonators

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)

• Two External RC Oscillator modes with the same

pin options as the External Clock modes

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC
source (approximately 31 kHz, stable over
temperature and V
6 user selectable clock frequencies, between
125 kHz to 4 MHz, for a total of 8 clock
frequencies. This option frees the two oscillator
pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and
Internal Oscillator modes, which allows clock
speeds of up to 40 MHz. Used with the internal
oscillator, the PLL gives users a complete
selection of clock speeds, from 31 kHz to
32 MHz – all without using an external crystal or
clock circuit.

Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a refer­ence signal provided by the internal oscillator. If a
clock failure occurs, the controller is switched to
the internal oscillator block, allowing for continued
low-speed operation or a safe application
shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.

DD), as well as a range of

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 7

PIC18F2682/2685/4682/4685

1.2 Other Special Features

• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.

• Self-Programmability: These devices can write
to their own program memory spaces under inter­nal software control. By using a bootloader rou­tine located in the protected Boot Block at the top
of program memory, it becomes possible to create
an application that can update itself in the field.

• Extended Instruction Set: The PIC18F2682/
2685/4682/4685 family introduces an optional
extension to the PIC18 instruction set, which adds
8 new instructions and an Indexed Addressing
mode. This extension, enabled as a device con­figuration option, has been specifically designed
to optimize re-entrant application code originally
developed in high-level languages, such as C.

• Enhanced CCP1 Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include auto-shutdown, for
disabling PWM outputs on interrupt or other select
conditions, and auto-restart to reactivate outputs
once the condition has cleared.

• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
Auto-Baud Rate Detection and a 16-bit Baud Rate
Generator for improved resolution. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).

• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.

• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing a time-out range from 4 ms to over
131 seconds, that is stable across operating
voltage and temperature.

1.3 Details on Individual Family Members

Devices in the PIC18F2682/2685/4682/4685 family are
available in 28-pin (PIC18F2682/2685) and 40/44-pin
(PIC18F4682/4685) packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in six
ways:

1. Flash program memory (80 Kbytes for

PIC18F2682/4682 devices, 96 Kbytes for
PIC18F2685/4685 devices).

2. A/D channels (8 for PIC18F2682/2685 devices,

11 for PIC18F4682/4685 devices).

3. I/O ports (3 bidirectional ports and 1 input only

port on PIC18F2682/2685 devices,
5 bidirectional ports on PIC18F4682/4685
devices).

4. CCP1 and Enhanced CCP1 implementation

(PIC18F2682/2685 devices have 1 standard
CCP1 module, PIC18F4682/4685 devices have
one standard CCP1 module and one ECCP1
module).

5. Parallel Slave Port (present only on

PIC18F4682/4685 devices).

6. PIC18F4682/4685 devices provide two

comparators.

All other features for devices in this family are identical.
These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and
Table 1-3.

Like all Microchip PIC18 devices, members of the
PIC18F2682/2685/4682/4685 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2685),
accommodate an operating V
Low-voltage parts, designated by “LF” (such as
PIC18LF2685), function over an extended V
of 2.0V to 5.5V.

DD range of 4.2V to 5.5V.

DD range

DS39761B-page 8 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

TABLE 1-1: DEVICE FEATURES

Features PIC18F2682 PIC18F2685 PIC18F4682 PIC18F4685

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz

Program Memory (Bytes) 80K 96K 80K 96K

Program Memory (Instructions) 40960 49152 40960 49152

Data Memory (Bytes) 3328 3328 3328 3328

Data EEPROM Memory (Bytes) 1024 1024 1024 1024

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM Modules 1 1 1 1

Enhanced Capture/
Compare/PWM Modules

ECAN Module 1 1 1 1

Serial Communications MSSP,

Enhanced USART

Parallel Slave Port
Communications (PSP)

10-bit Analog-to-Digital Module 8 Input Channels 8 Input Channels 11 Input Channels 11 Input Channels

Comparators 0 0 2 2

Resets (and Delays) POR, BOR,

RESET Instruction,

MCLR

Programmable High/Low-Voltage
Detect

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions;

83 with Extended

Packages 28-pin PDIP

0011

MSSP,

Enhanced USART

No No Yes Yes

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

WDT

Yes Ye s Yes Yes

Instruction Set

Enabled

28-pin SOIC

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

Enabled

28-pin PDIP
28-pin SOIC

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

Enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

Enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 9

PIC18F2682/2685/4682/4685

FIGURE 1-1: PIC18F2682/2685 (28-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(80/96 Kbytes)

Data Latch

Instruction Bus <16>

(2)

OSC1

(2)

OSC2

T1OSI

T1OSO

(1)

MCLR

VDD,

SS

V

20

8

Table Latch

ROM Latch

Instruction

Decode &

Control

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply
Programming

In-Circuit

Debugger

8

PCLATH

PCLATU

PCH PCL

PCU

Program Counter

31 Level Stack

STKPTR

IR

State Machine
Control Signals

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

Brown-out

Fail-Safe

Clock Monitor

Data Bus<8>

8

Timer

Reset

Timer

Reset

Data Latch

Data Memory

(3.3 Kbytes)

Address Latch

12

Data Address<12>

44

12

FSR0
FSR1
FSR2

inc/dec

logic

Decode

8 x 8 Multiply

W

8

ALU<8>

Access

Bank

PRODLPRODH

8

8

12

8

8

8

8

BSR

Address

3

BITOP

8

Band Gap
Reference

PORTA

PORTB

PORTC

PORTE

RA0/AN0
RA1/AN1
RA2/AN2/VREF­RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
OSC2/CLKO/RA6
OSC1/CLKI/RA7

RB0/INT0/AN10
RB1/INT1/AN8
RB2/INT2/CANTX
RB3/CANRX
RB4/KBI0/AN9
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

MCLR/VPP/RE3

/HLVDIN

(1)

BOR

HLVD

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Data

EEPROM

CCP1

Refer to Section 2.0 “Oscillator Configurations” for additional information.

ECCP1

MSSP

Timer2Timer1 Timer3Timer0

EUSART

ADC

10-bit

ECAN™

DS39761B-page 10 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

FIGURE 1-2: PIC18F4682/4685 (40/44-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(80/96 Kbytes)

Data Latch

Instruction Bus <16>

(2)

OSC1

(2)

OSC2

T1OSI

T1OSO

(1)

MCLR

VDD,

SS

V

20

8

Table Latch

ROM Latch

Instruction
Decode &

Control

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

8

PCLATH

PCLATU

PCH PCL

PCU

Program Counter

31 Level Stack

STKPTR

IR

State Machine
Control Signals

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

Brown-out

Fail-Safe

Clock Monitor

Data Bus<8>

8

Timer

Reset

Timer

Reset

Data Latch

Data Memory

(3.3 Kbytes)

Address Latch

12

Data Address<12>

12

44

BSR

3

BITOP

8

Band Gap
Reference

FSR0
FSR1
FSR2

inc/dec

logic

Address

Decode

8 x 8 Multiply

8

ALU<8>

W

Access

Bank

8

8

12

8

PRODLPRODH

8

8

PORTA

PORTB

PORTC

PORTD

8

PORTE

RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREF­RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
OSC2/CLKO/RA6
OSC1/CLKI/RA7

RB0/INT0/FLT0/AN10
RB1/INT1/AN8
RB2/INT2/CANTX
RB3/CANRX
RB4/KBI0/AN9
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

RD0/PSP0
RD1/PSP1/C1IN­RD2/PSP2/C2IN+
RD3/PSP3/C2IN-

RD4/PSP4/ECCP1/P1A

RD5/PSP5/P1B

RD6/PSP6/P1C

RD7/PSP7/P1D

RE0/RD/AN5
RE1/WR/AN6/C1OUT
RE2/CS/AN7/C2OUT
MCLR/VPP/RE3

/HLVDIN

/C1IN+

(1)

BOR

HLVD

Note 1: RE3 is multiplexed with MCLR

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Data

EEPROM

CCP1

Refer to Section 2.0 “Oscillator Configurations” for additional information.

ECCP1

MSSP

and is only available when the MCLR Resets are disabled.

Timer2Timer1 Timer3Timer0

EUSARTComparator

ADC

10-bit

ECAN™

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 11

PIC18F2682/2685/4682/4685

TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS

Pin

Pin Name

/VPP/RE3

MCLR

MCLR

VPP
RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Number

PDIP,
SOIC

10

Pin

Buffer

Type

1

9

P

I/O

O

O

I/O

Type

Master Clear (input) or programming voltage (input).

ST

I

I

ST

I

ST

I

CMOS

TTL

—

—

TTL

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
External clock source input. Always associated with pin
function OSC1. (See related OSC2/CLKO pin.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

Description

DS39761B-page 12 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
V

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI

RA4
T0CKI

RA5/AN4/SS

RA5
AN4
SS
HLVDIN

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

REF-

REF-

REF+

REF+

/HLVDIN

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Number

PDIP,
SOIC

2

3

4

5

6

7

Pin

Buffer

Typ e

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

I/O

I/OITTL

I/O

TTL

I

Analog

I

Analog

TTL

I

Analog

I

Analog

TTL

I

Analog

I

TTL

I

Analog

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.

Digital I/O.

ST

Timer0 external clock input.

Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.

Description

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 13

PIC18F2682/2685/4682/4685

TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RB0/INT0/AN10

RB0
INT0
AN10

RB1/INT1/AN8

RB1
INT1
AN8

RB2/INT2/CANTX

RB2
INT2
CANTX

RB3/CANRX

RB3
CANRX

RB4/KBI0/AN9

RB4
KBI0
AN9

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Number

PDIP,
SOIC

21

22

23

24

25

26

27

28

Pin

Buffer

Type

Type

I/O

I/O

I/O

I/OITTL

I/O

I/O

I/O

I/O

I/O

I/O

I/O

TTL
I
I

Analog

TTL
I
I

Analog

TTL
I

O

TTL

TTL

TTL
I

TTL
I

Analog

TTL
I

TTL

TTL
I

TTL

TTL
I

TTL

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.

ST

ST

ST

ST

ST

ST

External interrupt 0.
Analog input 10.

Digital I/O.
External interrupt 1.
Analog input 8.

Digital I/O.
External interrupt 2.
CAN bus TX.

Digital I/O.
CAN bus RX.

Digital I/O.
Interrupt-on-change pin.
Analog input 9.

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

DS39761B-page 14 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI

RC1
T1OSI

RC2/CCP1

RC2
CCP1

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

RE3 — — — See MCLR

VSS 8, 19 P — Ground reference for logic and I/O pins.

DD 20 P — Positive supply for logic and I/O pins.

V

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Number

PDIP,
SOIC

11

12

13

14

15

16

17

18

Pin

Buffer

Typ e

I/O

O

I

I/O

ISTCMOS

I/O
I/O

I/O
I/O
I/O

I/O

I

I/O

I/O

O

I/O

O

I/O

I/O

I

I/O

Type

ST

—

ST

ST
ST

ST
ST
ST

ST
ST
ST

ST

—

ST

—

ST

ST
ST
ST

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
SPI data in.

2

C data I/O.

I

Digital I/O.
SPI data out.

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).

/VPP/RE3 pin.

2

C™ mode.

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 15

PIC18F2682/2685/4682/4685

TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS

Pin Name

/VPP/RE3

MCLR

MCLR

VPP
RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Pin Number

PDIP QFN TQFP

11818

13 32 30

14 33 31

Pin

Typ e

I

P

I

I

I

I/O

O

O

I/O

Buffer

Type

ST

ST

ST

CMOS

TTL

—

—

TTL

Description

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode;
CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC2/CLKO pin.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.

DS39761B-page 16 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0/CVREF

RA0
AN0
CVREF

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
V

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI

RA4
T0CKI

RA5/AN4/SS

RA5
AN4
SS
HLVDIN

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

REF-

REF-

REF+

REF+

/HLVDIN

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Pin Number

PDIP QFN TQFP

21919

32020

42121

52222

62323

72424

Pin

Buffer

Typ e

Type

I/O

I

Analog

O

Analog

I/OITTL

Analog

I/O

I

Analog

I

Analog

I/O

I

Analog

I

Analog

I/OITTL

I/O

I

Analog
I
I

Analog

PORTA is a bidirectional I/O port.

TTL

TTL

TTL

ST

TTL

TTL

Digital I/O.
Analog input 0.
Analog comparator reference output.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.

Digital I/O.
Timer0 external clock input.

Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.

Description

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 17

PIC18F2682/2685/4682/4685

TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/FLT0/AN10

RB0
INT0
FLT0
AN10

RB1/INT1/AN8

RB1
INT1
AN8

RB2/INT2/CANTX

RB2
INT2
CANTX

RB3/CANRX

RB3
CANRX

RB4/KBI0/AN9

RB4
KBI0
AN9

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Pin Number

PDIP QFN TQFP

33 9 8

34 10 9

35 11 10

36 12 11

37 14 14

38 15 15

39 16 16

40 17 17

Pin

Buffer

Typ e

Type

I/O

I
I
I

Analog

I/O

I
I

Analog

I/O

I

O

I/OITTL

I/O

I
I

Analog

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

Description

PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.

TTL

ST
ST

TTL

ST

TTL

ST

TTL

TTL

TTL
TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Digital I/O.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
Analog input 10.

Digital I/O.
External interrupt 1.
Analog input 8.

Digital I/O.
External interrupt 2.
CAN bus TX.

Digital I/O.
CAN bus RX.

Digital I/O.
Interrupt-on-change pin.
Analog input 9.

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.

DS39761B-page 18 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI

RC1
T1OSI

RC2/CCP1

RC2
CCP1

RC3/SCK/SCL

RC3
SCK

SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Pin Number

PDIP QFN TQFP

15 34 32

16 35 35

17 36 36

18 37 37

23 42 42

24 43 43

25 44 44

26 1 1

Pin

Buffer

Typ e

Type

I/O

O

I

I/OIST

CMOS

I/O
I/OSTST

I/O
I/O

I/O

I/O

I

I/O

I/OOST

I/O

O

I/O

I/O

I

I/O

PORTC is a bidirectional I/O port.

ST
—
ST

ST
ST

ST

ST
ST
ST

—

ST
—
ST

ST
ST
ST

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.

Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for

2

C™ mode.

I

Digital I/O.
SPI data in.

2

C data I/O.

I

Digital I/O.
SPI data out.

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT
pin).

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK
pin).

Description

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 19

PIC18F2682/2685/4682/4685

TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/PSP0/C1IN+

RD0
PSP0
C1IN+

RD1/PSP1/C1IN-

RD1
PSP1
C1IN-

RD2/PSP2/C2IN+

RD2
PSP2
C2IN+

RD3/PSP3/C2IN-

RD3
PSP3
C2IN-

RD4/PSP4/ECCP1/
P1A

RD4
PSP4
ECCP1
P1A

RD5/PSP5/P1B

RD5
PSP5
P1B

RD6/PSP6/P1C

RD6
PSP6
P1C

RD7/PSP7/P1D

RD7
PSP7
P1D

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Pin Number

PDIP QFN TQFP

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Pin

Typ e

I/O
I/O

I

I/O
I/O

I

I/O
I/O

I

I/O
I/O

I

I/O
I/O
I/O

O

I/O
I/O

O

I/O
I/O

O

I/O
I/O

O

Buffer

Type

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

ST

TTL

ST
TTL
TTL

ST
TTL
TTL

ST
TTL
TTL

Description

PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.

Digital I/O.
Parallel Slave Port data.
Comparator 1 input (+).

Digital I/O.
Parallel Slave Port data.
Comparator 1 input (-)

Digital I/O.
Parallel Slave Port data.
Comparator 2 input (+).

Digital I/O.
Parallel Slave Port data.
Comparator 2 input (-).

Digital I/O.
Parallel Slave Port data.
Capture2 input/Compare2 output/PWM2 output.
ECCP1 PWM output A.

Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output B.

Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output C.

Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output D.

DS39761B-page 20 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/RD

RE1/WR

RE2/CS

RE3 — — — — — See MCLR

V

V

NC — 13 12, 13,

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

/AN5
RE0
RD

AN5

/AN6/C1OUT
RE1
WR

AN6
C1OUT

/AN7/C2OUT
RE2
CS

AN7
C2OUT

SS 12,

DD 11, 32 7, 8,

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Pin Number

PDIP QFN TQFP

82525

92626

10 27 27

6, 30, 316, 29 P — Ground reference for logic and I/O pins.

31

7, 28 P — Positive supply for logic and I/O pins.

28, 29

33, 34

Pin

Buffer

Typ e

Type

PORTE is a bidirectional I/O port.

I/O

I/O

I/O

— — No connect.

ST

I

TTL

I

Analog

ST

TTL

I

Analog

I

TTL

O

ST

I

TTL

I

Analog

O

TTL

Digital I/O.
Read control for Parallel Slave Port
(see also W
Analog input 5.

Digital I/O.
Write control for Parallel Slave Port
(see C
Analog input 6.
Comparator 1 output.

Digital I/O.
Chip select control for Parallel Slave Port
(see related RD
Analog input 7.
Comparator 2 output.

Description

R and CS pins).

S and RD pins).

and WR pins).

/VPP/RE3 pin.

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 21

PIC18F2682/2685/4682/4685

NOTES:

DS39761B-page 22 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

PIC18F2682/2685/4682/4685 devices can be operated
in ten different oscillator modes. The user can program
the Configuration bits, FOSC3:FOSC0, in Configuration
Register 1H to select one of these ten modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL enabled

5. RC External Resistor/Capacitor with

F

OSC/4 output on RA6

6. RCIO External Resistor/Capacitor with I/O

on RA6

7. INTIO1 Internal Oscillator with F

on RA6 and I/O on RA7

8. INTIO2 Internal Oscillator with I/O on RA6

and RA7

9. EC External Clock with F

10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.

The oscillator design requires the use of a parallel cut
crystal.

Note: Use of a series cut crystal may give a

frequency out of the crystal manufacturer’s
specifications.

OSC/4 output

OSC/4 output

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)

(1)

C1

(1)

C2

Note 1:See Table 2-1 and Table 2-2 for initial values of

2: A series resistor (R

3: R

OSC1

XTAL

(2)

RS

OSC2

C1 and C2.

strip cut crystals.

F varies with the oscillator mode chosen.

(3)

RF

Sleep

PIC18FXXXX

S) may be required for AT

To

Internal
Logic

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz

Capacitor values are for design guidance only.

These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.

Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V

See the notes on page 24 for additional information.

Resonators Used:

56 pF
47 pF
33 pF

27 pF
22 pF

56 pF
47 pF
33 pF

27 pF
22 pF

455 kHz 4.0 MHz

2.0 MHz 8.0 MHz

16.0 MHz

Note: When using resonators with frequencies

above 3.5 MHz, the use of HS mode,
rather than XT mode, is recommended.
HS mode may be used at any V

DD for

which the controller is rated. If HS is
selected, it is possible that the gain of the
oscillator will overdrive the resonator.
Therefore, a series resistor should be
placed between the OSC2 pin and the
resonator. As a good starting point, the
recommended value of R

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 23

S is 330Ω.

PIC18F2682/2685/4682/4685

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc Type

LP 32 kHz 33 pF 33 pF

XT 1 MHz 33 pF 33 pF

HS 4 MHz 27 pF 27 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed
below for basic start-up and operation. These values

are not optimized.

Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V

See the notes following this table for additional
information.

Note 1: Higher capacitance increases the stability

Crystal

Freq

200 kHz 15 pF 15 pF

4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

32 kHz 4 MHz

200 kHz 8 MHz

1 MHz 20 MHz

of the oscillator but also increases the
start-up time.

2: When operating below 3V V

using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

4: Rs may be required to avoid overdriving

crystals with low drive level specifications.

5: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

Typical Capacitor Values

Tested:

C1 C2

Crystals Used:

DD, or when

An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK

INPUT OPERATION
(HS OSCILLATOR
CONFIGURATION)

Clock from
Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.3 External Clock Input

The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.

FIGURE 2-3: EXTERNAL CLOCK

INPUT OPERATION
(EC CONFIGURATION)

Clock from
Ext. System

F

OSC/4

The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-4 shows the pin connections
for the ECIO Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK

Clock from
Ext. System

RA6

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

INPUT OPERATION
(ECIO CONFIGURATION)

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

DS39761B-page 24 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

2.4 RC Oscillator

For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The actual oscillator frequency is a function of several
factors:

• supply voltage

• values of the external resistor (R

capacitor (C

EXT)

• operating temperature

Given the same device, operating voltage and tempera­ture and component values, there will also be unit-to-unit
frequency variations. These are due to factors such as:

• normal manufacturing variation

• difference in lead frame capacitance between

package types (especially for low C

• variations within the tolerance of limits of R

EXT

and C

In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-5 shows how the R/C combination is
connected.

FIGURE 2-5: RC OSCILLATOR MODE

VDD

REXT

OSC1

CEXT

VSS

F

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

OSC/4

OSC2/CLKO

EXT > 20 pF

C

EXT) and

EXT values)

EXT

Internal

Clock

PIC18FXXXX

2.5 PLL Frequency Multiplier

A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.

2.5.1 HSPLL OSCILLATOR MODE

The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.

The PLL is only available to the crystal oscillator when
the FOSC3:FOSC0 Configuration bits are programmed
for HSPLL mode (= 0110).

FIGURE 2-7: PLL BLOCK DIAGRAM

(HS MODE)

HS Osc Enable

PLL Enable

(from Configuration Register 1H)

OSC2

OSC1

HS Mode

Crystal

Osc

IN

F

FOUT

÷4

Phase

Comparator

Loop
Filter

VCO

SYSCLK

MUX

The RCIO Oscillator mode (Figure 2-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).

2.5.2 PLL AND INTOSC

The PLL is also available to the internal oscillator block
in selected oscillator modes. In this configuration, the

FIGURE 2-6: RCIO OSCILLATOR MODE

VDD

PLL is enabled in software and generates a clock
output of up to 32 MHz. The operation of INTOSC with
the PLL is described in Section 2.6.4 “PLL in INTOSC

REXT

OSC1

CEXT

VSS

RA6

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 25

I/O (OSC2)

C

EXT > 20 pF

Internal

Clock

PIC18FXXXX

Modes”.

PIC18F2682/2685/4682/4685

2.6 Internal Oscillator Block

The PIC18F2682/2685/4682/4685 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s
clock source. This may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock frequency from 125 kHz
to 8 MHz is selected.

The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in
Section 24.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register 2-2).

2.6.1 INTIO MODES

Using the internal oscillator as the clock source
eliminates the need for up to two external oscillator
pins, which can then be used for digital I/O. Two distinct
configurations are available:

• In INTIO1 mode, the OSC2 pin outputs F
while OSC1 functions as RA7 for digital input and
output.

• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.

2.6.2 INTOSC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.

The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC and vice versa.

2.6.3 OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s applica­tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.

OSC/4,

When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately
8*32μs = 256 μs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred.

The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.
This is covered in greater detail in Section 2.7.1
“Oscillator Control Register”.

The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes.

2.6.4 PLL IN INTOSC MODES

The 4x frequency multiplier can be used with the inter­nal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.

Unlike HSPLL mode, the PLL is controlled through soft­ware. The control bit, PLLEN (OSCTUNE<6>), is used
to enable or disable its operation.

The PLL is available when the device is configured to use
the internal oscillator block as its primary clock source
(FOSC3:FOSC0 = 1001 or 1000). Additionally, the PLL
will only function when the selected output frequency is
either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110). If
both of these conditions are not met, the PLL is disabled.

The PLLEN control bit is only functional in those internal
oscillator modes where the PLL is available. In all other
modes, it is forced to ‘0’ and is effectively unavailable.

2.6.5 INTOSC FREQUENCY DRIFT

The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as V
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are
discussed in Section 2.6.5.1 “Compensating with

the EUSART”, Section 2.6.5.2 “Compensating with
the Timers” and Section 2.6.5.3 “Compensating
with the CCP1 Module in Capture Mode”, but other

techniques may be used.

DD or temperature changes, which can

DS39761B-page 26 Preliminary © 2007 Microchip Technology Inc.

PIC18F2682/2685/4682/4685

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 R/W-0

INTSRC PLLEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit

1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)
0 = PLL disabled

bit 5 Unimplemented: Read as ‘0

bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency

• •

• •

00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111

• •

• •
10000 = Minimum frequency

(1)

(1)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TUN4 TUN3 TUN2 TUN1 TUN0

(1)

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See

text for details.

2.6.5.1 Compensating with the EUSART

An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.

2.6.5.2 Compensating with the Timers

This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.

Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast. To adjust for this, decrement
the OSCTUNE register.

2.6.5.3 Compensating with the CCP1
Module in Capture Mode

The CCP1 module can use free running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.

If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.

© 2007 Microchip Technology Inc. Preliminary DS39761B-page 27

PIC18F2682/2685/4682/4685

2.7 Clock Sources and Oscillator Switching

Like previous PIC18 devices, the PIC18F2682/2685/
4682/4685 family includes a feature that allows the
device clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
PIC18F2682/2685/4682/4685 devices offer two alter­nate clock sources. When an alternate clock source is
enabled, the various power-managed operating modes
are available.

Essentially, there are three clock sources for these
devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined by the FOSC3:FOSC0
Configuration bits. The details of these modes are
covered earlier in this chapter.

The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.

PIC18F2682/2685/4682/4685 devices offer the Timer1
oscillator as a secondary oscillator. In all power­managed modes, this oscillator is often the time base
for functions such as a Real-Time Clock.

Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI
pins. Like the LP mode oscillator circuit, loading
capacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in
Section 12.3 “Timer1 Oscillator”.

In addition to being a primary clock source, the internal
oscillator block is available as a power-managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2682/2685/4682/4685
devices are shown in Figure 2-8. See Section 24.0
“Special Features of the CPU” for Configuration

register details.

FIGURE 2-8: PIC18F2682/2685/4682/4685 CLOCK DIAGRAM

PIC18F2682/2685/4682/4685

4 x PLL

OSCCON<6:4>

8 MHz

111

4 MHz

110

2 MHz

101

1 MHz

31 kHz

100

011

010

001

000

OSCTUNE<7>

500 kHz

Postscaler

250 kHz

125 kHz

1
0

HSPLL, INTOSC/PLL

MUX

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

Secondary Oscillator

T1OSCEN
Enable
Oscillator

OSCCON<6:4>

Internal

Oscillator

Block

8 MHz

Source

INTRC
Source

31 kHz (INTRC)

OSCTUNE<6>

8 MHz

(INTOSC)

LP, XT, HS, RC, EC

T1OSC

Internal Oscillator

FOSC3:FOSC0

Peripherals

MUX

Clock

Control

Clock Source Option
for other Modules

WDT, PWRT, FSCM
and Two-Speed Startup

IDLEN

OSCCON<1:0>

CPU

DS39761B-page 28 Preliminary © 2007 Microchip Technology Inc.