MICROCHIP PIC18F2455, PIC18F2550, PIC18F4455, PIC18F4550 DATA SHEET

PIC18F2455/2550/4455/4550

Data Sheet

28/40/44-Pin, High-Performance,

Enhanced Flash, USB Microcontrollers

with nanoWatt Technology

© 2006 Microchip Technology Inc. Preliminary DS39632C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR­RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
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RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
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Microchip disclaims all liability arising from this information and
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any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and Zena are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEEL

®

OQ

code hopping

DS39632C-page ii Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

28/40/44-Pin, High-Performance, Enhanced Flash,

USB Microcontrollers with nanoWatt Technology

Universal Serial Bus Features:

• USB V2.0 Compliant

• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)

• Supports Control, Interrupt, Isochronous and Bulk

Transfers

• Supports up to 32 Endpoints (16 bidirectional)

• 1-Kbyte Dual Access RAM for USB

• On-Chip USB Transceiver with On-Chip Voltage

Regulator

• Interface for Off-Chip USB Transceiver

• Streaming Parallel Port (SPP) for USB streaming

transfers (40/44-pin devices only)

Power-Managed Modes:

• Run: CPU on, peripherals on

• Idle: CPU off, peripherals on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 μA typical

• Sleep mode currents down to 0.1 μA typical

• Timer1 Oscillator: 1.1 μA typical, 32 kHz, 2V

• Watchdog Timer: 2.1 μA typical

• Two-Speed Oscillator Start-up

Flexible Oscillator Structure:

• Four Crystal modes, including High Precision PLL

for USB

• Two External Clock modes, up to 48 MHz

• Internal Oscillator Block:

- 8 user-selectable frequencies, from 31 kHz
to 8 MHz

- User-tunable to compensate for frequency drift

• Secondary Oscillator using Timer1 @ 32 kHz

• Dual Oscillator options allow microcontroller and
USB module to run at different clock speeds

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if any clock stops

Peripheral Highlights:

• High-Current Sink/Source: 25 mA/25 mA

• Three External Interrupts

• Four Timer modules (Timer0 to Timer3)

• Up to 2 Capture/Compare/PWM (CCP) modules:

2

C™

CY/16)

CY)

- Capture is 16-bit, max. resolution 5.2 ns (T

- Compare is 16-bit, max. resolution 83.3 ns (T

- PWM output: PWM resolution is 1 to 10-bit

• Enhanced Capture/Compare/PWM (ECCP) module:

- Multiple output modes

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

• Enhanced USART module:

- LIN bus support

• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I
Master and Slave modes

• 10-bit, up to 13-channel Analog-to-Digital Converter
module (A/D) with Programmable Acquisition Time

• Dual Analog Comparators with Input Multiplexing

Special Microcontroller Features:

• C Compiler Optimized Architecture with optional
Extended Instruction Set

• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory typical

• 1,000,000 Erase/Write Cycle Data EEPROM
Memory typical

• Flash/Data EEPROM Retention: > 40 years

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

• Programmable Code Protection

• Single-Supply 5V In-Circuit Serial
Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Optional dedicated ICD/ICSP port (44-pin devices only)

• Wide Operating Voltage Range (2.0V to 5.5V)

SPI

MSSP

Master

I

2

C™

EAUSART

Timers

8/16-Bit

Comparators

Program Memory Data Memory

Device

PIC18F2455 24K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3

PIC18F2550 32K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3

PIC18F4455 24K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3

PIC18F4550 32K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 1

Flash

(bytes)

# Single-Word

Instructions

SRAM

(bytes)

EEPROM

(bytes)

I/O

10-Bit

A/D (ch)

CCP/ECCP

(PWM)

SPP

PIC18F2455/2550/4455/4550

Pin Diagrams

28-Pin PDIP, SOIC

RA5/AN4/SS

40-Pin PDIP

MCLR/VPP/RE3

RA0/AN0

RA2/AN2/V

RA4/T0CKI/C1OUT/RCV

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

/HLVDIN/C2OUT

OSC1/CLKI

OSC2/CLKO/RA6

(1)

/UOE

RC2/CCP1

V

V

USB

1
2
3
4
5
6
7

SS

8
9
10
11
12
13
14

PIC18F2455

PIC18F2550

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
V

DD

VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM

(1)

/VPO

MCLR/VPP/RE3

RA0/AN0

RA2/AN2/V

RA4/T0CKI/C1OUT/RCV

RA5/AN4/SS

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP

RE2/AN7/OESPP

OSC2/CLKO/RA6

RC2/CCP1/P1A

V
VSS

OSC1/CLKI

(1)

/UOE

V

USB

RD0/SPP0
RD1/SPP1

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PIC18F4455

PIC18F4550

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
V

DD

VSS
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2

(1)

/VPO

DS39632C-page 2 Preliminary © 2006 Microchip Technology Inc.

Pin Diagrams (Continued)

44-Pin TQFP

PIC18F2455/2550/4455/4550

/UOE

(1)

(2)

RC7/RX/DT/SDO

RD4/SPP4

RD5/SPP5/P1B

RD6/SPP6/P1C

RD7/SPP7/P1D

RB0/AN12/INT0/FLT0/SDI/SDA

RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMO

RB3/AN9/CCP2

(1)

V

VDD

/VPO

44-Pin QFN

RC6/TX/CK

RC5/D+/VP

RC4/D-/VM

RD3/SPP3

4443424140

1
2
3
4
5

PIC18F4455

SS

6
7
8
9
10
11

121314

(2)

(2)

/ICPGC

(2)

(2)

NC/ICCK

PIC18F4550

15

/ICPGD

RB5/KBI1/PGM

NC/ICDT

RB4/AN11/KBI0/CSSPP

RD2/SPP2

RD1/SPP1

RD0/SPP0

39

38

16

17

1819202122

/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

MCLR

USB

V

37

RA0/AN0

RC2/CCP1/P1A

363435

RA1/AN1

RC1/T1OSI/CCP2

NC/ICPORTS

(2)

33
32
31
30
29
28
27
26
25
24
23

REF-/CVREF

RA3/AN3/VREF+

RA2/AN2/V

NC/ICRST
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
V

SS

VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS
RA4/T0CKI/C1OUT/RCV

/UOE

(1)

(2)

/ICVPP

/HLVDIN/C2OUT

RC6/TX/CK

RC5/D+/VP

RC4/D-/VM

RD3/SPP3

RC7/RX/DT/SDO

RD4/SPP4

RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D

RB0/AN12/INT0/FLT0/SDI/SDA

RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMO

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: Special ICPORTS features available in select circumstances. See Section 25.9 “Special ICPORT Features (Designated

Packages Only)” for more information.

V
VDD
VDD

SS

1
2
3
4
5
6
7
8
9
10
11

(1)

4443424140

121314

PIC18F4455
PIC18F4550

15

NC

/VPO

RB5/KBI1/PGM

RB3/AN9/CCP2

RB4/AN11/KBI0/CSSPP

RD2/SPP2

RD1/SPP1

RD0/SPP0

39

38

1819202122

16

17

/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

MCLR

USB

V

37

RA0/AN0

RC2/CCP1/P1A

363435

RA1/AN1

RC1/T1OSI/CCP2

RC0/T1OSO/T13CKI

33
32
31
30
29
28
27
26
25
24
23

REF+

REF-/CVREF

RA3/AN3/V

RA2/AN2/V

OSC2/CLKO/RA6
OSC1/CLKI

SS

V
VSS
VDD
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 3

PIC18F2455/2550/4455/4550

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Oscillator Configurations ............................................................................................................................................................ 23

3.0 Power-Managed Modes ............................................................................................................................................................. 35

4.0 Reset .......................................................................................................................................................................................... 43

5.0 Memory Organization ................................................................................................................................................................. 57

6.0 Flash Program Memory.............................................................................................................................................................. 79

7.0 Data EEPROM Memory ............................................................................................................................................................. 89

8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 95

9.0 Interrupts .................................................................................................................................................................................... 97

10.0 I/O Ports ................................................................................................................................................................................... 111

11.0 Timer0 Module ......................................................................................................................................................................... 125

12.0 Timer1 Module ......................................................................................................................................................................... 129

13.0 Timer2 Module ......................................................................................................................................................................... 135

14.0 Timer3 Module ......................................................................................................................................................................... 137

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 141

16.0 Enhanced Capture/Compare/PWM (ECCP) Module ................................................................................................................ 149

17.0 Universal Serial Bus (USB) ...................................................................................................................................................... 163

18.0 Streaming Parallel Port ............................................................................................................................................................ 187

19.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 193

20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 237

21.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 259

22.0 Comparator Module.................................................................................................................................................................. 269

23.0 Comparator Voltage Reference Module ................................................................................................................................... 275

24.0 High/Low-Voltage Detect (HLVD) ............................................................................................................................................. 279

25.0 Special Features of the CPU.................................................................................................................................................... 285

26.0 Instruction Set Summary .......................................................................................................................................................... 307

27.0 Development Support............................................................................................................................................................... 357

28.0 Electrical Characteristics .......................................................................................................................................................... 361

29.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 399

30.0 Packaging Information.............................................................................................................................................................. 401

Appendix A: Revision History............................................................................................................................................................. 409

Appendix B: Device Differences......................................................................................................................................................... 409

Appendix C: Conversion Considerations ........................................................................................................................................... 410

Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 410

Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 411

Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 411

Index .................................................................................................................................................................................................. 413

The Microchip Web Site..................................................................................................................................................................... 425

Customer Change Notification Service .............................................................................................................................................. 425

Customer Support .............................................................................................................................................................................. 425

Reader Response .............................................................................................................................................................................. 426

PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 427

DS39632C-page 4 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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welcome your feedback.

Most Current Data Sheet

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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© 2006 Microchip Technology Inc. Preliminary DS39632C-page 5

PIC18F2455/2550/4455/4550

NOTES:

DS39632C-page 6 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC18F2455 • PIC18LF2455

• PIC18F2550 • PIC18LF2550

• PIC18F4455 • PIC18LF4455

• PIC18F4550 • PIC18LF4550

This family of devices offers the advantages of all
PIC18 microcontrollers – namely, high computational
performance at an economical price – with the addition
of high endurance, Enhanced Flash program mem­ory. In addition to these features, the
PIC18F2455/2550/4455/4550 family introduces design
enhancements that make these microcontrollers a log­ical choice for many high-performance, power sensitive
applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2455/2550/4455/4550
family incorporate a range of features that can signifi­cantly reduce power consumption during operation.
Key items include:

• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.

• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.

• Low Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer are minimized. See Section 28.0
“Electrical Characteristics” for values.

1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2455/2550/4455/4550
family offer twelve different oscillator options, allowing
users a wide range of choices in developing application
hardware. These include:

• Four Crystal modes using crystals or ceramic

resonators.

• Four External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC
source (approximately 31 kHz, stable over
temperature and V
6 user-selectable clock frequencies, between
125 kHz to 4 MHz, for a total of 8 clock
frequencies. This option frees an oscillator pin for
use as an additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and
External Oscillator modes, which allows a wide
range of clock speeds from 4 MHz to 48 MHz.

• Asynchronous dual clock operation, allowing the

USB module to run from a high-frequency
oscillator while the rest of the microcontroller is
clocked from an internal low-power oscillator.

Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a
reference signal provided by the internal
oscillator. If a clock failure occurs, the controller is
switched to the internal oscillator block, allowing
for continued low-speed operation or a safe
application shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.

DD), as well as a range of

1.1.2 UNIVERSAL SERIAL BUS (USB)

Devices in the PIC18F2455/2550/4455/4550 family
incorporate a fully featured Universal Serial Bus
communications module that is compliant with the USB
Specification Revision 2.0. The module supports both
low-speed and full-speed communication for all sup­ported data transfer types. It also incorporates its own
on-chip transceiver and 3.3V regulator and supports
the use of external transceivers and voltage regulators.

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 7

PIC18F2455/2550/4455/4550

1.2 Other Special Features

• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.

• Self-Programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine,
located in the protected Boot Block at the top of
program memory, it becomes possible to create an
application that can update itself in the field.

• Extended Instruction Set: The
PIC18F2455/2550/4455/4550 family introduces
an optional extension to the PIC18 instruction set,
which adds 8 new instructions and an Indexed
Literal Offset Addressing mode. This extension,
enabled as a device configuration option, has
been specifically designed to optimize re-entrant
application code originally developed in high-level
languages such as C.

• Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include auto-shutdown for
disabling PWM outputs on interrupt or other select
conditions and auto-restart to reactivate outputs
once the condition has cleared.

• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
Automatic Baud Rate Detection and a 16-bit Baud
Rate Generator for improved resolution. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).

• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated, without waiting for a sampling period and
thus, reducing code overhead.

• Dedicated ICD/ICSP Port: These devices
introduce the use of debugger and programming
pins that are not multiplexed with other micro­controller features. Offered as an option in select
packages, this feature allows users to develop I/O
intensive applications while retaining the ability to
program and debug in the circuit.

1.3 Details on Individual Family Members

Devices in the PIC18F2455/2550/4455/4550 family are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.

The devices are differentiated from each other in six
ways:

1. Flash program memory (24 Kbytes for

PIC18FX455 devices, 32 Kbytes for
PIC18FX550).

2. A/D channels (10 for 28-pin devices, 13 for

40/44-pin devices).

3. I/O ports (3 bidirectional ports and 1 input only

port on 28-pin devices, 5 bidirectional ports on
40/44-pin devices).

4. CCP and Enhanced CCP implementation

(28-pin devices have two standard CCP
modules, 40/44-pin devices have one standard
CCP module and one ECCP module).

5. Streaming Parallel Port (present only on

40/44-pin devices).

All other features for devices in this family are identical.
These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and
Table 1-3.

Like all Microchip PIC18 devices, members of the
PIC18F2455/2550/4455/4550 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2550),
accommodate an operating V
Low-voltage parts, designated by “LF” (such as
PIC18LF2550), function over an extended V
of 2.0V to 5.5V.

DD range of 4.2V to 5.5V.

DD range

DS39632C-page 8 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 1-1: DEVICE FEATURES

Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550

Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz

Program Memory (Bytes) 24576 32768 24576 32768

Program Memory (Instructions) 12288 16384 12288 16384

Data Memory (Bytes) 2048 2048 2048 2048

Data EEPROM Memory (Bytes) 256 256 256 256

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM Modules 2 2 1 1

Enhanced Capture/
Compare/PWM Modules

Serial Communications MSSP,

Enhanced USART

Universal Serial Bus (USB)
Module

Streaming Parallel Port (SPP) No No Yes Yes

10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels

Comparators 2 2 2 2

Resets (and Delays) POR, BOR,

RESET Instruction,

Stack Underflow

MCLR

Programmable Low-Voltage
Detect

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions;

83 with Extended

Packages 28-pin PDIP

0011

MSSP,

Enhanced USART

1111

POR, BOR,

RESET Instruction,

Stack Full,

(PWRT, OST),

(optional),

WDT

Yes Yes Yes Yes

Instruction Set

enabled

28-pin SOIC

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

28-pin PDIP
28-pin SOIC

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 9

PIC18F2455/2550/4455/4550

FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

Instruction Bus <16>

(2)

OSC1

(2)

OSC2

T1OSI

T1OSO

(1)

MCLR

VDD,

SS

V

USB

V

20

8

Table Latch

ROM Latch

Instruction

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply
Programming

In-Circuit

Debugger

USB Voltage

PCLATH

PCLATU

PCH PCL

PCU

Program Counter

31 Level Stack

STKPTR

IR

Decode &

Control

Start-up Timer

Clock Monitor

Regulator

Data Bus<8>

8

8

State Machine
Control Signals

Power-up

Time r

Oscillator

Power-on

Reset

Watchdog

Time r

Brown-out

Reset

Fail-Safe

Data Latch

Data Memory

(2 Kbytes)

Address Latch

12

Data Address<12>

44

12

FSR0
FSR1
FSR2

logic

8 x 8 Multiply

W

8

ALU<8>

Access

Bank

PRODLPRODH

8

8

12

8

BSR

3

BITOP

Band Gap

Reference

8

inc/dec

Address

Decode

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6

PORTB

RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

PORTC

8

8

8

PORTE

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO

MCLR/VPP/RE3

(3)

/VPO

(3)

(1)

/UOE

BOR

HLVD

Comparator

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer

to Section 2.0 “Oscillator Configurations” for additional information.

3: RB3 is the alternate pin for CCP2 multiplexing.

Data

EEPROM

CCP1

CCP2

MSSP

Timer2Timer1 Timer3Timer0

EUSART

ADC

10-Bit

USB

DS39632C-page 10 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

20

8

PCLATH

PCLATU

PCU

Program Counter

31 Level Stack

STKPTR

Table Latch

Data Bus<8>

8

PCH PCL

8

Data Latch

Data Memory

(2 Kbytes)

Address Latch

12

Data Address<12>

12

44

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Access

Bank

12

PORTA

PORTB

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6

RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2

(4)

/VPO
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

Instruction Bus <16>

VDD, VSS

(2)

OSC1

(2)

OSC2

T1OSI

T1OSO

(3)

ICPGC

(3)

ICPGD

(3)

ICPORTS

(3)

ICRST

(1)

MCLR

USB

V

ROM Latch

IR

Instruction

Decode &

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply
Programming

In-Circuit

Debugger

Control

USB Voltage

Regulator

State Machine
Control Signals

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Clock Monitor

3

BITOP

8

Band Gap
Reference

Address
Decode

8 x 8 Multiply

W

8

ALU<8>

PORTC

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2

(4)

/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP

8

RC6/TX/CK
RC7/RX/DT/SDO

PRODLPRODH

PORTD

8

RD0/SPP0:RD4/SPP4

8

8

RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D

8

8

PORTE

RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
MCLR/VPP/RE3

(1)

BOR

HLVD

Comparator

Note 1: RE3 is multiplexed with MCLR

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer

Data

EEPROM

ECCP1

CCP2

MSSP

Timer2Timer1 Timer3Timer0

EUSART

10-Bit

and is only available when the MCLR Resets are disabled.

to Section 2.0 “Oscillator Configurations” for additional information.

ADC

USB

3: These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features

(Designated Packages Only)” for additional information.

4: RB3 is the alternate pin for CCP2 multiplexing.

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 11

PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS

Pin

Pin Name

MCLR

/VPP/RE3

MCLR

VPP
RE3

OSC1/CLKI

OSC1
CLKI

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

Number

PDIP,
SOIC

10

Pin

Buffer

Type

1

9

Type

I

ST

P

I

ST

IIAnalog

Analog

O

O

I/O

—

—

TTL

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

Description

DS39632C-page 12 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
V
CV

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI/C1OUT/RCV

RA4
T0CKI
C1OUT
RCV

RA5/AN4/SS
HLVDIN/C2OUT

RA5
AN4
SS
HLVDIN
C2OUT

RA6 — — — See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

REF-/CVREF

REF-

REF

REF+

REF+

/

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

Number

PDIP,

SOIC

Pin

Buffer

Type

2

3

4

5

6

7

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

I/O

I/O

I/O

TTL

I

Analog

I

Analog

O

Analog

TTL

I

Analog

I

Analog

ST

I

ST

O

I

I
I
I

O

—

TTL

TTL

Analog

TTL

Analog

—

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.

Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.

Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.

Description

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 13

PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RB0/AN12/INT0/FLT0/
SDI/SDA

RB0
AN12
INT0
FLT0
SDI
SDA

RB1/AN10/INT1/SCK/
SCL

RB1
AN10
INT1
SCK
SCL

RB2/AN8/INT2/VMO

RB2
AN8
INT2
VMO

RB3/AN9/CCP2/VPO

RB3
AN9

(1)

CCP2
VPO

RB4/AN11/KBI0

RB4
AN11
KBI0

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

Number

PDIP,
SOIC

21

22

23

24

25

26

27

28

Pin

Type

I/O

I
I
I
I

I/O

I/O

I

I
I/O
I/O

I/O

I

I

O

I/O

I
I/O

O

I/O

I

I

I/O

I
I/O

I/O

I
I/O

I/O

I
I/O

Buffer

Type

TTL

Analog

ST
ST
ST
ST

TTL

Analog

ST
ST
ST

TTL

Analog

ST

—

TTL

Analog

ST

—

TTL

Analog

TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.

2

C™ data I/O.

I

Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.

Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

2

C mode.

DS39632C-page 14 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2/UOE

RC1
T1OSI

(2)

CCP2
UOE

RC2/CCP1

RC2
CCP1

RC4/D-/VM

RC4
D­VM

RC5/D+/VP

RC5
D+
VP

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT/SDO

RC7
RX
DT
SDO

RE3 — — — See MCLR

VUSB 14 O — Internal USB 3.3V voltage regulator.

SS 8, 19 P — Ground reference for logic and I/O pins.

V

DD 20 P — Positive supply for logic and I/O pins.

V

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

Number

PDIP,

SOIC

11

12

13

15

16

17

18

Pin

Type

I/O

O

I

I/O

I

I/O

—

I/O
I/O

I

I/O

I

I

I/O

O

I/O

O

I/O

I/O

I

I/O

O

Buffer

Type

ST

—

ST

ST

CMOS

ST

—

ST
ST

TTL

—

TTL

TTL

—

TTL

ST

—

ST

ST
ST
ST

—

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver OE

Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.

Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.

Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.

/VPP/RE3 pin.

output.

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 15

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

PDIP QFN TQFP

Pin

Typ e

Buffer

Type

Description

/VPP/RE3

MCLR

MCLR

VPP
RE3

OSC1/CLKI

OSC1
CLKI

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

11818

13 32 30

14 33 31

I

ST

P

I

ST

IIAnalog

Analog

O

—

O

—

I/O

TTL

Configuration bit is cleared.

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.

DS39632C-page 16 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

REF

CV

RA3/AN3/V

RA4/T0CKI/C1OUT/
RCV

RA5/AN4/SS
HLVDIN/C2OUT

RA6 — — — — — See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

REF-/

RA2
AN2

REF-

V
CV

REF

REF+

RA3
AN3

REF+

V

RA4
T0CKI
C1OUT
RCV

/

RA5
AN4
SS
HLVDIN
C2OUT

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

21919

32020

42121

52222

62323

72424

Pin

Buffer

Typ e

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

I

Analog

I

Analog

O

Analog

I/O

I

Analog

I

Analog

I/O

I

O

I

I/O

I

Analog
I
I

Analog

O

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

TTL

TTL

ST
ST

—

TTL

TTL

TTL

—

Configuration bit is cleared.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.

Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.

Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.

Description

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 17

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/AN12/INT0/
FLT0/SDI/SDA

RB0
AN12
INT0
FLT0
SDI
SDA

RB1/AN10/INT1/SCK/
SCL

RB1
AN10
INT1
SCK
SCL

RB2/AN8/INT2/VMO

RB2
AN8
INT2
VMO

RB3/AN9/CCP2/VPO

RB3
AN9

(1)

CCP2
VPO

RB4/AN11/KBI0/CSSPP

RB4
AN11
KBI0
CSSPP

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

33 9 8

34 10 9

35 11 10

36 12 11

37 14 14

38 15 15

39 16 16

40 17 17

Pin

Typ e

I/O

I
I
I
I

I/O

I/O

I

I
I/O
I/O

I/O

I

I

O

I/O

I
I/O

O

I/O

I

I

O

I/O

I
I/O

I/O

I
I/O

I/O

I
I/O

Buffer

Type

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

TTL

Analog

ST
ST
ST
ST

TTL

Analog

ST
ST
ST

TTL

Analog

ST

—

TTL

Analog

ST

—

TTL

Analog

TTL

—

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Configuration bit is cleared.

Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI data in.

2

C™ data I/O.

I

Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.

Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

Description

2

C mode.

DS39632C-page 18 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2/
UOE

RC1
T1OSI

(2)

CCP2
UOE

RC2/CCP1/P1A

RC2
CCP1
P1A

RC4/D-/VM

RC4
D­VM

RC5/D+/VP

RC5
D+
VP

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT/SDO

RC7
RX
DT
SDO

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

15 34 32

16 35 35

17 36 36

23 42 42

24 43 43

25 44 44

26 1 1

Pin

Typ e

I/O

O

I

I/O

I

I/O

O

I/O
I/O

O

I

I/O

I

I

I/O

I

I/O

O

I/O

I/O

I

I/O

O

Buffer

Type

PORTC is a bidirectional I/O port.

ST

—

ST

ST

CMOS

ST

—

ST
ST

TTL

TTL

—

TTL

TTL

—

TTL

ST

—

ST

ST
ST
ST

—

Configuration bit is cleared.

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver OE output.

Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1 PWM output, channel A.

Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.

Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.

Description

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 19

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/SPP0

RD0
SPP0

RD1/SPP1

RD1
SPP1

RD2/SPP2

RD2
SPP2

RD3/SPP3

RD3
SPP3

RD4/SPP4

RD4
SPP4

RD5/SPP5/P1B

RD5
SPP5
P1B

RD6/SPP6/P1C

RD6
SPP6
P1C

RD7/SPP7/P1D

RD7
SPP7
P1D

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Pin

Buffer

Typ e

Type

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/O

O

I/O
I/O

O

I/O
I/O

O

Description

PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). These pins have TTL input buffers
when the SPP module is enabled.

Digital I/O.
Streaming Parallel Port data.

Digital I/O.
Streaming Parallel Port data.

Digital I/O.
Streaming Parallel Port data.

Digital I/O.
Streaming Parallel Port data.

Digital I/O.
Streaming Parallel Port data.

ST

TTL

—

ST

TTL

—

ST

TTL

—

Configuration bit is cleared.

Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel B.

Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel C.

Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel D.

DS39632C-page 20 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/AN5/CK1SPP

RE0
AN5
CK1SPP

RE1/AN6/CK2SPP

RE1
AN6
CK2SPP

RE2/AN7/OESPP

RE2
AN7
OESPP

RE3 — — — — — See MCLR

VSS 12, 31 6, 30, 316, 29 P — Ground reference for logic and I/O pins.

V

DD 11, 32 7, 8,

V

USB 18 37 37 O — Internal USB 3.3V voltage regulator output.

NC/ICCK/ICPGC

ICCK
ICPGC

NC/ICDT/ICPGD

ICDT
ICPGD

NC/ICRST/ICVPP

ICRST
ICVPP

NC/ICPORTS

ICPORTS

NC — 13 — — — No Connect.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

(3)

(3)

(3)

(3)

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

82525

92626

10 27 27

7, 28 P — Positive supply for logic and I/O pins.

28, 29

——12

——13

——33

— — 34 P — No Connect or 28-pin device emulation.

Pin

Buffer

Typ e

I/O

I

Analog

O

I/O

I

Analog

O

I/O

I

Analog

O

I/O
I/OSTST

I/O
I/OSTST

I

P

Type

PORTE is a bidirectional I/O port.

ST

—

ST

—

ST

—

—
—

Configuration bit is cleared.

Digital I/O.
Analog input 5.
SPP clock 1 output.

Digital I/O.
Analog input 6.
SPP clock 2 output.

Digital I/O.
Analog input 7.
SPP output enable output.

/VPP/RE3 pin.

No Connect or dedicated ICD/ICSP™ port clock.

In-Circuit Debugger clock.
ICSP programming clock.

No Connect or dedicated ICD/ICSP port clock.

In-Circuit Debugger data.
ICSP programming data.

No Connect or dedicated ICD/ICSP port Reset.

Master Clear (Reset) input.
Programming voltage input.

Enable 28-pin device emulation when connected

SS.

to V

Description

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 21

PIC18F2455/2550/4455/4550

NOTES:

DS39632C-page 22 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.0 OSCILLATOR CONFIGURATIONS

2.1 Overview

Devices in the PIC18F2455/2550/4455/4550 family
incorporate a different oscillator and microcontroller
clock system than previous PIC18F devices. The addi­tion of the USB module, with its unique requirements
for a stable clock source, make it necessary to provide
a separate clock source that is compliant with both
USB low-speed and full-speed specifications.

To accommodate these requirements, PIC18F2455/
2550/4455/4550 devices include a new clock branch to
provide a 48 MHz clock for full-speed USB operation.
Since it is driven from the primary clock source, an
additional system of prescalers and postscalers has
been added to accommodate a wide range of oscillator
frequencies. An overview of the oscillator structure is
shown in Figure 2-1.

Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.

2.1.1 OSCILLATOR CONTROL

The operation of the oscillator in PIC18F2455/2550/
4455/4550 devices is controlled through two Configu­ration registers and two control registers. Configuration
registers, CONFIG1L and CONFIG1H, select the
oscillator mode and USB prescaler/postscaler options.
As Configuration bits, these are set when the device is
programmed and left in that configuration until the
device is reprogrammed.

The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control
Register”.

The OSCTUNE register (Register 2-1) is used to trim
the INTRC frequency source, as well as select the
low-frequency clock source that drives several special
features. Its use is described in Section 2.2.5.2

“OSCTUNE Register”.

2.2 Oscillator Types

PIC18F2455/2550/4455/4550 devices can be operated
in twelve distinct oscillator modes. In contrast with pre­vious PIC18 enhanced microcontrollers, four of these
modes involve the use of two oscillator types at once.
Users can program the FOSC3:FOSC0 Configuration
bits to select one of these modes:

1. XT Crystal/Resonator

2. XTPLL Crystal/Resonator with PLL enabled

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator
with PLL enabled

5. EC External Clock with F

6. ECIO External Clock with I/O on RA6

7. ECPLL External Clock with PLL enabled
and F

OSC/4 output on RA6

8. ECPIO External Clock with PLL enabled,
I/O on RA6

9. INTHS Internal Oscillator used as
microcontroller clock source, HS
Oscillator used as USB clock source

10. INTXT Internal Oscillator used as
microcontroller clock source, XT
Oscillator used as USB clock source

11. INTIO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
digital I/O on RA6

12. INTCKO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,

OSC/4 output on RA6

F

OSC/4 output

2.2.1 OSCILLATOR MODES AND

USB OPERATION

Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
previous PICmicro
clocks were driven by a single oscillator source; the
usual sources were primary, secondary or the internal
oscillator. With PIC18F2455/2550/4455/4550 devices,
the primary oscillator becomes part of the USB module
and cannot be associated to any other clock source.
Thus, the USB module must be clocked from the primary
clock source; however, the microcontroller core and
other peripherals can be separately clocked from the
secondary or internal oscillators as before.

Because of the timing requirements imposed by USB,
an internal clock of either 6 MHz or 48 MHz is required
while the USB module is enabled. Fortunately, the
microcontroller and other peripherals are not required
to run at this clock speed when using the primary
oscillator. There are numerous options to achieve the
USB module clock requirement and still provide flexibil­ity for clocking the rest of the device from the primary
oscillator source. These are detailed in Section 2.3
“Oscillator Settings for USB”.

®

devices, all core and peripheral

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 23

PIC18F2455/2550/4455/4550

FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM

PIC18F2455/2550/4455/4550

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

XT, HS, EC, ECIO

Secondary Oscillator

T1OSCEN
Enable
Oscillator

OSCCON<6:4>

Internal

Oscillator

Block

8 MHz
Source

INTRC

Source

31 kHz (INTRC)

8 MHz

(INTOSC)

PLLDIV

÷ 12

111

÷ 10

110

÷ 6

101

100

011

010

001

000

1
0

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

250 kHz

125 kHz

31 kHz

MUX

HSPLL, ECPLL,

XTPLL, ECPIO

(4 MHz Input Only)

96 MHz

PLL

CPUDIV

÷ 6

11

÷ 4

10

÷ 3

01

÷ 2

PLL Postscaler

OSCCON<6:4>

111

110

101

100

011

010

001

000

OSCTUNE<7>

00

MUX

÷ 2

FOSC3:FOSC0

Internal Oscillator

÷ 5
÷ 4
÷ 3

PLL Prescaler

÷ 2
÷ 1

CPUDIV

÷ 4

11

÷ 3

10

÷ 2

01

÷ 1

00

Oscillator Postscaler

INTOSC Postscaler

USB Clock Source

USBDIV

0
1

÷ 4

1
0

Primary
Clock

T1OSC

FOSC3:FOSC0

Clock Source Option
for other Modules

MUX

Clock

Control

FSEN

1

0

IDLEN

Peripherals

OSCCON<1:0>

USB

Peripheral

CPU

WDT, PWRT, FSCM
and Two-Speed Start-up

DS39632C-page 24 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In HS, HSPLL, XT and XTPLL Oscillator modes, a
crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-2
shows the pin connections.

The oscillator design requires the use of a parallel cut
crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s
specifications.

FIGURE 2-2: CRYSTAL/CERAMIC

RESONATOR OPERATION
(XT, HS OR HSPLL
CONFIGURATION)

(1)

C1

(1)

C2

Note 1: See Table 2-1 and Table 2-2 for initial values of

2: A series resistor (R

3: R

OSC1

XTAL

(2)

RS

OSC2

C1 and C2.

strip cut crystals.

F varies with the oscillator mode chosen.

(3)

RF

Sleep

PIC18FXXXX

S) may be required for AT

To

Internal
Logic

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 4.0 MHz 33 pF 33 pF

HS 8.0 MHz

16.0 MHz

Capacitor values are for design guidance only.

These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.

Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V

See the notes following Table 2-2 for additional
information.

Resonators Used:

16.0 MHz

4.0 MHz

8.0 MHz

27 pF
22 pF

27 pF
22 pF

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc Type

Crystal

Freq

XT 4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed
below for basic start-up and operation. These values

are not optimized.

Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V

See the notes following this table for additional
information.

Crystals Used:

Note 1: Higher capacitance increases the stability

of oscillator but also increases the
start-up time.

2: When operating below 3V V

using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.

5: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPUDIV
Configuration bits. Users may select a clock frequency
of the oscillator frequency, or 1/2, 1/3 or 1/4 of the
frequency.

An external clock may also be used when the micro­controller is in HS Oscillator mode. In this case, the
OSC2/CLKO pin is left open (Figure 2-3).

Typical Capacitor Values

Test ed:

C1 C2

4 MHz

8 MHz

20 MHz

DD, or when

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 25

PIC18F2455/2550/4455/4550

FIGURE 2-3: EXTERNAL CLOCK INPUT

OPERATION (HS OSC
CONFIGURATION)

Clock from
Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.2.3 EXTERNAL CLOCK INPUT

The EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external clock source to be connected to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleep
mode.

In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK

INPUT OPERATION
(EC AND ECPLL
CONFIGURATION)

2.2.4 PLL FREQUENCY MULTIPLIER

PIC18F2455/2550/4255/4550 devices include a Phase
Locked Loop (PLL) circuit. This is provided specifically
for USB applications with lower speed oscillators and
can also be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there are
eight prescaling options to match the oscillator input
frequency to the PLL.

There is also a separate postscaler option for deriving
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds. In contrast to the postscaler for XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6
of the PLL output.

The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The prescaler divides the oscillator input by up to 12 to
produce the 4 MHz drive for the PLL. The XTPLL mode
can only use an input frequency of 4 MHz which drives
the PLL directly.

Clock from
Ext. System

OSC/4

F

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

The ECIO and ECPIO Oscillator modes function like the
EC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The I/O
pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows
the pin connections for the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK

INPUT OPERATION
(ECIO AND ECPIO
CONFIGURATION)

Clock from
Ext. System

RA6

The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

FIGURE 2-6: PLL BLOCK DIAGRAM

(HS MODE)

HS/EC/ECIO/XT Oscillator Enable

(from CONFIG1H Register)

OSC2

Oscillator

OSC1

and

Prescaler

PLL Enable

Phase

Comparator

IN

F

FOUT

÷24

Loop
Filter

VCO

SYSCLK

MUX

DS39632C-page 26 Preliminary © 2006 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.2.5 INTERNAL OSCILLATOR BLOCK

The PIC18F2455/2550/4455/4550 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s
clock source. If the USB peripheral is not used, the
internal oscillator may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives the INTOSC postscaler which can provide a
range of clock frequencies from 31 kHz to 4 MHz. The
INTOSC output is enabled when a clock frequency
from 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator
(INTRC) which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in
Section 25.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 32).

2.2.5.1 Internal Oscillator Modes

When the internal oscillator is used as the micro­controller clock source, one of the other oscillator
modes (External Clock or External Crystal/Resonator)
must be used as the USB clock source. The choice of
the USB clock source is determined by the particular
internal oscillator mode.

There are four distinct modes available:

1. INTHS mode: The USB clock is provided by the

oscillator in HS mode.

2. INTXT mode: The USB clock is provided by the

oscillator in XT mode.

3. INTCKO mode: The USB clock is provided by an

external clock input on OSC1/CLKI; the OSC2/
CLKO pin outputs F

4. INTIO mode: The USB clock is provided by an

external clock input on OSC1/CLKI; the OSC2/
CLKO pin functions as a digital I/O (RA6).

Of these four modes, only INTIO mode frees up an
additional pin (OSC2/CLKO/RA6) for port I/O use.

OSC/4.

2.2.5.2 OSCTUNE Register

The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s applica­tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.

When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately,
8*32μs = 256 μs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred.

The OSCTUNE register also contains the INTSRC bit.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in Section 2.4.1 “Oscillator Control Register”.

2.2.5.3 Internal Oscillator Output Frequency
and Drift

The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
However, this frequency may drift as VDD or tempera­ture changes, which can affect the controller operation
in a variety of ways.

The low-frequency INTRC oscillator operates indepen­dently of the INTOSC source. Any changes in INTOSC
across voltage and temperature are not necessarily
reflected by changes in INTRC and vice versa.

© 2006 Microchip Technology Inc. Preliminary DS39632C-page 27

PIC18F2455/2550/4455/4550

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INTSRC — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6-5 Unimplemented: Read as ‘0’

bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency

• •

• •

00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111

• •

• •
10000 = Minimum frequency

2.2.5.4 Compensating for INTOSC Drift

It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register. This has
no effect on the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. When using the EUSART, for example, an
adjustment may be required when it begins to generate
framing errors or receives data with errors while in
Asynchronous mode. Framing errors indicate that the
device clock frequency is too high; to adjust for this,
decrement the value in OSCTUNE to reduce the clock
frequency. On the other hand, errors in data may sug­gest that the clock speed is too low; to compensate,
increment OSCTUNE to increase the clock frequency.

It is also possible to verify device clock speed against
a reference clock. Two timers may be used: one timer
is clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator. Both timers are cleared but the timer
clocked by the reference generates interrupts. When

an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
timer value is greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.

Finally, a CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.

If the measured time is much greater than the calcu­lated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculated
time, the internal oscillator block is running too slow; to
compensate, increment the OSCTUNE register.

DS39632C-page 28 Preliminary © 2006 Microchip Technology Inc.