MICROCHIP PIC18F2458, PIC18F2553, PIC18F4458, PIC18F4553 DATA SHEET

PIC18F2458/2553/4458/4553

Data Sheet

28/40/44-Pin High-Performance,

Enhanced Flash, USB Microcontrollers

with 12-Bit A/D and nanoWatt Technology

© 2007 Microchip Technology Inc. Preliminary DS39887B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS39887B-page ii Preliminary © 2007 Microchip Technology Inc.

PIC18F2458/2553/4458/4553

28/40/44-Pin High-Performance, Enhanced Flash, USB

Microcontrollers with 12-Bit A/D and nanoWatt Technology

Universal Serial Bus Features:

• USB V2.0 Compliant

• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)

• Supports Control, Interrupt, Isochronous and Bulk

Transfers

• Supports up to 32 Endpoints (16 bidirectional)

• 1-Kbyte Dual Access RAM for USB

• On-Chip USB Transceiver with On-Chip Voltage

Regulator

• Interface for Off-Chip USB Transceiver

• Streaming Parallel Port (SPP) for USB Streaming

Transfers (40/44-pin devices only)

Power-Managed Modes:

• Run: CPU On, Peripherals On

• Idle: CPU Off, Peripherals On

• Sleep: CPU Off, Peripherals Off

• Idle mode Currents Down to 5.8 μA Typical

• Sleep mode Currents Down to 0.1 μA Typical

• Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V

• Watchdog Timer: 2.1 μA Typical

• Two-Speed Oscillator Start-up

Special Microcontroller Features:

• C Compiler Optimized Architecture with Optional

Extended Instruction Set

• 100,000 Erase/Write Cycle Enhanced Flash

Program Memory Typical

• 1,000,000 Erase/Write Cycle Data EEPROM

Memory Typical

• Flash/Data EEPROM Retention: > 40 Years

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

• Programmable Code Protection

• Single-Supply 5V In-Circuit Serial

Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins

• Optional Dedicated ICD/ICSP Port (44-pin TQFP

package only)

• Wide Operating Voltage Range (2.0V to 5.5V)

Program Memory Data Memory

Device

PIC18F2458 24K 12288

PIC18F2553 32K 16384

PIC18F4458 24K 12288

PIC18F4553 32K 16384

Flash

(bytes)

# Single-Word

Instructions

SRAM

(bytes)

EEPROM

(bytes)

2048 256

Flexible Oscillator Structure:

• Four Crystal modes, Including High-Precision PLL
for USB

• Two External Clock modes, up to 48 MHz

• Internal Oscillator Block:

- 8 user-selectable frequencies, from 31 kHz

to 8 MHz

- User-tunable to compensate for frequency drift

• Secondary Oscillator using Timer1 @ 32 kHz

• Dual Oscillator Options allow Microcontroller and
USB module to Run at Different Clock Speeds

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if any clock stops

Peripheral Highlights:

• High-Current Sink/Source: 25 mA/25 mA

• Three External Interrupts

• Four Timer modules (Timer0 to Timer3)

• Up to 2 Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution 5.2 ns (T

- Compare is 16-bit, max. resolution 83.3 ns (T

- PWM output: PWM resolution is 1 to 10-bits

• Enhanced Capture/Compare/PWM (ECCP) module:

- Multiple output modes

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

• Enhanced USART module:

- LIN bus support

• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I
Master and Slave modes

• 12-Bit, up to 13-Channel Analog-to-Digital Converter
module (A/D) with Programmable Acquisition Time

• Dual Analog Comparators with Input Multiplexing

Note: This document is supplemented by

the “PIC18F2455/2550/4455/4550 Data

Sheet” (DS39632). See Section 1.0
“Device Overview”.

12-Bit

I/O

A/D (ch)

24 10 2/0 No

35 13 1/1 Yes

CCP/ECCP

(PWM)

SPP

CY/16)

CY)

2

C™

MSSP

Master

SPI

2

C™

I

YY121/3

EUSART

Comp.

Timers

8/16-Bit

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 1

PIC18F2458/2553/4458/4553

Pin Diagrams

28-Pin SPDIP, SOIC

RA5/AN4/SS

40-Pin PDIP

MCLR/VPP/RE3

RA0/AN0

RA2/AN2/V

RA4/T0CKI/C1OUT/RCV

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

/HLVDIN/C2OUT

OSC1/CLKI

OSC2/CLKO/RA6

(1)

/UOE

RC2/CCP1

V

V

USB

1
2
3
4
5
6
7

SS

8
9
10
11
12
13
14

PIC18F2458

28
27
26
25
24
23
22
21
20

PIC18F2553

19
18
17
16
15

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
V

DD

VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM

(1)

/VPO

MCLR/VPP/RE3

RA0/AN0

RA2/AN2/V

RA4/T0CKI/C1OUT/RCV

RA5/AN4/SS

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP

RE2/AN7/OESPP

OSC2/CLKO/RA6

RC2/CCP1/P1A

V
VSS

OSC1/CLKI

(1)

/UOE

V

USB

RD0/SPP0
RD1/SPP1

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PIC18F4458

PIC18F4553

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
V

DD

VSS
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2

(1)

/VPO

DS39887B-page 2 Preliminary © 2007 Microchip Technology Inc.

Pin Diagrams (Continued)

44-Pin TQFP

PIC18F2458/2553/4458/4553

/UOE

(1)

(2)

RC7/RX/DT/SDO

RD5/SPP5/P1B

RD6/SPP6/P1C
RD7/SPP7/P1D

RB0/AN12/INT0/FLT0/SDI/SDA

RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMO

RB3/AN9/CCP2

44-Pin QFN

RD4/SPP4

V
VDD

(1)

/VPO

RC6/TX/CK

RC5/D+/VP

RC4/D-/VM

RD3/SPP3

4443424140

1
2
3
4
5

PIC18F4458

SS

6
7
8
9
10
11

121314

(2)

(2)

/ICPGC

(2)

(2)

NC/ICCK

PIC18F4553

15

/ICPGD

RB5/KBI1/PGM

NC/ICDT

RB4/AN11/KBI0/CSSPP

RD2/SPP2

RD1/SPP1

39

16

17

RB7/KBI3/PGD

RB6/KBI2/PGC

USB

RD0/SPP0

V

RC2/CCP1/P1A

RC1/T1OSI/CCP2

363435

37

38

1819202122

RA1/AN1

RA0/AN0

/VPP/RE3

REF-/CVREF

MCLR

RA2/AN2/V

NC/ICPORTS

(2)

33
32
31
30
29
28
27
26
25
24
23

RA3/AN3/VREF+

NC/ICRST
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
V

SS

VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS
RA4/T0CKI/C1OUT/RCV

/UOE

(1)

(2)

/ICVPP

/HLVDIN/C2OUT

15

RD2/SPP2

16

RB6/KBI2/PGC

USB

RD1/SPP1

RD0/SPP0

V

39

37

38

1819202122

17

RA0/AN0

/VPP/RE3

RB7/KBI3/PGD

MCLR

RC2/CCP1/P1A

363435

RA1/AN1

RC1/T1OSI/CCP2

REF-/CVREF

RA2/AN2/V

RC0/T1OSO/T13CKI

33
32
31
30
29
28
27
26
25
24
23

REF+

RA3/AN3/V

OSC2/CLKO/RA6
OSC1/CLKI

SS

V
VSS
VDD
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS
RA4/T0CKI/C1OUT/RCV

RC6/TX/CK

RC5/D+/VP

RC4/D-/VM

RD3/SPP3

RC7/RX/DT/SDO

RD4/SPP4

RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D

RB0/AN12/INT0/FLT0/SDI/SDA

RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMO

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: Special ICPORT features are available only in 44-pin TQFP packages. See Section 25.9 “Special ICPORT Features” in

the “PIC18F2455/2550/4455/4550 Data Sheet”’.

V
VDD
VDD

SS

4443424140

1
2
3
4
5
6
7
8
9
10
11

(1)

PIC18F4458
PIC18F4553

121314

NC

/VPO

RB5/KBI1/PGM

RB3/AN9/CCP2

RB4/AN11/KBI0/CSSPP

/HLVDIN/C2OUT

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 3

PIC18F2458/2553/4458/4553

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 5

2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 19

3.0 Special Features of the CPU...................................................................................................................................................... 29

4.0 Electrical Characteristics ............................................................................................................................................................ 31

5.0 Packaging Information................................................................................................................................................................ 35

Appendix A: Revision History............................................................................................................................................................... 37

Appendix B: Device Differences........................................................................................................................................................... 37

Appendix C: Migration From Mid-Range to Enhanced Devices........................................................................................................... 38

Appendix D: Migration From High-End to Enhanced Devices ............................................................................................................. 38

Index .................................................................................................................................................................................................... 39

The Microchip Web Site....................................................................................................................................................................... 41

Customer Change Notification Service ................................................................................................................................................ 41

Customer Support ................................................................................................................................................................................ 41

Reader Response ................................................................................................................................................................................ 42

Product Identification System............................................................................................................................................................... 43

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Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS39887B-page 4 Preliminary © 2007 Microchip Technology Inc.

PIC18F2458/2553/4458/4553

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC18F2458 • PIC18F4458

• PIC18F2553 • PIC18F4553

Note: This data sheet documents only the

devices’ features and specifications that are
in addition to the features and specifica­tions of the PIC18F2455/2550/4455/4550
devices. For information on the features
and specifications shared by
the PIC18F2458/2553/4458/4553 and
PIC18F2455/2550/4455/4550 devices,

see the “PIC18F2455/2550/4455/4550

Data Sheet” (DS39632).

The PIC18F4553 family of devices offers the advan­tages of all PIC18 microcontrollers – namely, high
computational performance at an economical price –
with the addition of high-endurance, Enhanced Flash
program memory. In addition to these features, the
PIC18F4553 family introduces design enhancements
that make these microcontrollers a logical choice for
many high-performance, power sensitive applications.

1.1 Special Features

• 12-Bit A/D Converter: The PIC18F4553 family
implements a 12-bit A/D Converter. The A/D
Converter incorporates programmable acquisi­tion time. This allows for a channel to be selected
and a conversion to be initiated, without waiting
for a sampling period and thus, reducing code
overhead.

1.2 Details on Individual Family Members

The PIC18F2458/2553/4458/4553 devices are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.

The devices are differentiated from each other in the
following ways:

1. Flash program memory (24 Kbytes for

PIC18FX458 devices, 32 Kbytes for
PIC18FX553).

2. A/D channels (10 for 28-pin devices, 13 for

40-pin and 44-pin devices).

3. I/O ports (3 bidirectional ports and 1 input only

port on 28-pin devices, 5 bidirectional ports on
40-pin and 44-pin devices).

4. CCP and Enhanced CCP implementation

(28-pin devices have two standard CCP
modules, 40-pin and 44-pin devices have one
standard CCP module and one ECCP module).

5. Streaming Parallel Port (present only on

40/44-pin devices).

All other features for devices in this family are identical.
These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and
Table 1-3.

Members of the PIC18F4553 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2458),
accommodate an operating V
Low-voltage parts, designated by “LF” (such as
PIC18LF2458), function over an extended VDD range
of 2.0V to 5.5V.

DD range of 4.2V to 5.5V.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 5

PIC18F2458/2553/4458/4553

TABLE 1-1: DEVICE FEATURES

Features PIC18F2458 PIC18F2553 PIC18F4458 PIC18F4553

Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz

Program Memory (Bytes) 24576 32768 24576 32768

Program Memory
(Instructions)

Data Memory (Bytes) 2048 2048 2048 2048

Data EEPROM Memory
(Bytes)

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM
Modules

Enhanced Capture/
Compare/PWM Modules

Serial Communications MSSP,

Universal Serial Bus (USB)
Module

Streaming Parallel Port (SPP) No No Yes Yes

12-Bit Analog-to-Digital
Converter Module

Comparators 2 2 2 2

Resets (and Delays) POR, BOR, WDT,

Programmable High/
Low-Voltage Detect

Programmable Brown-out
Reset

Instruction Set 75 Instructions;

Packages 28-Pin SPDIP

Corresponding Devices with
10-Bit A/D

12288 16384 12288 16384

256 256 256 256

2 2 1 1

0 0 1 1

MSSP,

Enhanced USART

1 1 1 1

10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels

RESET Instruction,

Stack Full, Stack

Underflow, MCLR

(optional),

(PWRT, OST)

Yes Ye s Yes Ye s

Yes Ye s Ye s Yes

83 with Extended

Instruction Set

Enabled

28-Pin SOIC

PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550

Enhanced USART

POR, BOR, WDT,

RESET Instruction,

Stack Full, Stack

Underflow, MCLR

(optional),

(PWRT, OST)

75 Instructions;

83 with Extended

Instruction Set

Enabled

28-Pin SPDIP

28-Pin SOIC

MSSP,

Enhanced USART

POR, BOR, WDT,

RESET Instruction,

Stack Full, Stack

Underflow, MCLR

(optional),

(PWRT, OST)

75 Instructions;

83 with Extended

Instruction Set

Enabled

40-Pin PDIP
44-Pin QFN

44-Pin TQFP

MSSP,

Enhanced USART

POR, BOR, WDT,

RESET Instruction,

Stack Ful l, Stack

Underflow, MCLR

(optional),

(PWRT, OST)

75 Instructions;

83 with Extended

Instruction Set

Enabled

40-Pin PDIP

44-Pin QFN

44-Pin TQFP

DS39887B-page 6 Preliminary © 2007 Microchip Technology Inc.

PIC18F2458/2553/4458/4553

FIGURE 1-1: PIC18F2458/2553 (28-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

Instruction Bus <16>

(2)

OSC1

(2)

OSC2

T1OSI

T1OSO

(1)

MCLR

VDD,

SS

V

USB

V

20

8

Tabl e L a t c h

Instruction

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

PCLATH

PCLATU

PCH PCL

PCU

Program Counter

31 Level Stack

STKPTR

ROM Latch

IR

Decode &

Control

Start-up Timer

Clock Monitor

USB Voltage

Regulator

Data Bus<8>

8

8

State Machine
Control Signals

Power-up

Timer

Oscillator

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Data Latch

Data Memory

(2 Kbytes)

Address Latch

12

Data Address<12>

44

12

FSR0
FSR1
FSR2

inc/dec

logic

Decode

8 x 8 Multiply

W

8

ALU<8>

Access

Bank

PRODLPRODH

8

8

12

8

BSR

Address

3

BITOP

8

Band Gap
Reference

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6

PORTB

RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

PORTC

8

8

8

PORTE

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO

MCLR/VPP/RE3

(3)

/VPO

(3)

(1)

/UOE

BOR

HLVD

Comparator

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: RB3 is the alternate pin for CCP2 multiplexing.

Data

EEPROM

CCP1

CCP2

MSSP

Timer2Timer1 Timer3Timer0

EUSART

ADC

12-Bit

USB

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 7

PIC18F2458/2553/4458/4553

FIGURE 1-2: PIC18F4458/4553(40/44-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

20

8

PCLATH

PCLATU

PCU

Program Counter

31 Level Stack

STKPTR

Table Latch

Data Bus<8>

8

PCH PCL

8

Data Latch

Data Memory

(2 Kbytes)

Address Latch

12

Data Address<12>

12

44

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Access

Bank

12

PORTA

PORTB

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6

RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2

(4)

/VPO
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

Instruction Bus <16>

VDD, VSS

(2)

OSC1

(2)

OSC2

T1OSI

T1OSO

(3)

ICPGC

(3)

ICPGD

(3)

ICPORTS

(3)

ICRST

(1)

MCLR

V

USB

ROM Latch

IR

Instruction

Decode &

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

Control

USB Voltage

Regulator

State Machine
Control Signals

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Clock Monitor

3

BITOP

8

Band Gap

Reference

Address
Decode

8 x 8 Multiply

8

ALU<8>

PORTC

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2

(4)

/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP

8

RC6/TX/CK
RC7/RX/DT/SDO

PRODLPRODH

PORTD

8

W

8

8

RD0/SPP0:RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D

8

8

PORTE

RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
MCLR/VPP/RE3

(1)

BOR

HLVD

Comparator

Note 1: RE3 is multiplexed with MCLR

Data

EEPROM

ECCP1

Timer2Timer1 Timer3Timer0

CCP2

MSSP

EUSART

ADC

12-Bit

and is only available when the MCLR Resets are disabled.

USB

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: These pins are only available on 44-pin TQFP packages under certain conditions.
4: RB3 is the alternate pin for CCP2 multiplexing.

DS39887B-page 8 Preliminary © 2007 Microchip Technology Inc.

PIC18F2458/2553/4458/4553

TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS

Pin

Pin Name

M

CLR/VPP/RE3

MCLR

VPP
RE3

OSC1/CLKI

OSC1
CLKI

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

Number

SPDIP,

SOIC

10

Pin

Buffer

Type

1

9

Type

I

ST

P

I

ST

IIAnalog

Analog

O

O

I/O

—

—

TTL

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

Description

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 9

PIC18F2458/2553/4458/4553

TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/VREF-/CVREF

RA2
AN2
VREF-

REF

CV

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI/C1OUT/RCV

RA4
T0CKI
C1OUT
RCV

RA5/AN4/SS
HLVDIN/C2OUT

RA5
AN4
SS
HLVDIN
C2OUT

RA6 — — — See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

REF+

REF+

/

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

Number

SPDIP,

SOIC

Pin

Buffer

Type

2

3

4

5

6

7

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

I/O

I/O

I/O

TTL

I

Analog

I

Analog

O

Analog

TTL

I

Analog

I

Analog

ST

I

ST

O

I

I
I
I

O

—

TTL

TTL

Analog

TTL

Analog

—

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.

Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.

Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.

Description

DS39887B-page 10 Preliminary © 2007 Microchip Technology Inc.

PIC18F2458/2553/4458/4553

TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RB0/AN12/INT0/FLT0/
SDI/SDA

RB0
AN12
INT0
FLT0
SDI
SDA

RB1/AN10/INT1/SCK/
SCL

RB1
AN10
INT1
SCK
SCL

RB2/AN8/INT2/VMO

RB2
AN8
INT2
VMO

RB3/AN9/CCP2/VPO

RB3
AN9

(1)

CCP2
VPO

RB4/AN11/KBI0

RB4
AN11
KBI0

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

Number

SPDIP,

SOIC

21

22

23

24

25

26

27

28

Pin

Type

I/O

I
I
I
I

I/O

I/O

I

I
I/O
I/O

I/O

I

I

O

I/O

I
I/O

O

I/O

I

I

I/O

I
I/O

I/O

I
I/O

I/O

I
I/O

Buffer

Type

TTL

Analog

ST
ST
ST
ST

TTL

Analog

ST
ST
ST

TTL

Analog

ST

—

TTL

Analog

ST

—

TTL

Analog

TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.

2

C™ data I/O.

I

Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.

Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

2

C mode.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 11

PIC18F2458/2553/4458/4553

TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2/UOE

RC1
T1OSI

(2)

CCP2
UOE

RC2/CCP1

RC2
CCP1

RC4/D-/VM

RC4
D­VM

RC5/D+/VP

RC5
D+
VP

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT/SDO

RC7
RX
DT
SDO

RE3 — — — See MCLR

V

USB 14

V

SS 8, 19 P — Ground reference for logic and I/O pins.

V

DD 20 P — Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

Number

SPDIP,

SOIC

11

12

13

15

16

17

18

Pin

Type

I/O

O

I

I/O

I

I/O

—

I/O
I/O

I

I/O

I

I

I/O

O

I/O

O

I/O

I/O

I

I/O

O

O

P

Buffer

Type

ST

—

ST

ST

CMOS

ST

—

ST
ST

TTL

—

TTL

TTL

—

TTL

ST

—

ST

ST
ST
ST

—

—

—

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE

Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.

Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.

Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.

/VPP/RE3 pin.

Internal USB transceiver power supply.

When the internal USB regulator is enabled, V
regulator output.
When the internal USB regulator is disabled, V
power input for the USB transceiver.

output.

USB is the

USB is the

DS39887B-page 12 Preliminary © 2007 Microchip Technology Inc.