MICROCHIP PIC18F2331, PIC18F2431, PIC18F4331, PIC18F4431 DATA SHEET

PIC18F2331/2431/4331/4431

Data Sheet

28/40/44-Pin Enhanced

Flash Microcontrollers

with nanoWatt Technology,

High Performance PWM and A/D

 2003 Microchip Technology Inc. Preliminary DS39616B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, MPLAB, PIC, PICmic ro, PI C START,

PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTE R ,
SEEVAL, SmartShunt and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net,
dsPICworks, ECAN, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC,
Select Mode, SmartSensor, SmartTel and Total Endurance
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip re cei v ed I S O/T S - 16 949 : 20 02 qu ality system c er ti f ic at io n f or
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in October
2003 . The Company’s quality system processes and procedures are
for its PICmicro
EEPROMs, microperipherals, non-volatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEELOQ

®

code hopping devices, Serial

DS39616B-page ii Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

28/40/44-Pin Enhanced Flash Microcontrollers with

nanoWatt Technology, High Performance PWM and A/D

14-bit Power Control PWM Module:

• Up to 4 channels with complementary outputs

• Edge- or center-aligned operation

• Flexible dead-band generator

• Hardware fault protection inputs

• Simultaneous update of duty cycle and period:

- Flexible special event trigger output

Motion Feedback Module:

• Three independent input capture channels:

- Flexible operating modes for period and pulse
width measuremen t

- Special Hall Sens or interface module

- Special event trigger output to other modules

• Quadrature Encoder Interface:

- 2 phase inputs and one index input from encoder

- High and low position tracking with directi on
status and change of direction interrupt

- Velocity measurement

High-Speed, 200 Ksps 10-bit A/D Converter:

• Up to 9 channels

• Simultaneous two-channel sampling

• Sequential sampling: 1, 2 or 4 selected channels

• Auto-conversion capability

• 4-word FIFO with selectable interrupt frequency

• Selectable extern al con ve rsi on trig gers

• Programmable acquisition time

Flexible Oscillator Struc ture:

• Four crystal modes up to 40 MHz

• Two external clock modes up to 40 MHz

• Internal oscillator block:

- 8 user selectable frequencies: 31 kHz to 8MHz

- OSCTUNE can compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown of device if clock fails

Power-Managed Modes:

• Run CPU on, peripherals on

• Idle CPU off, peripherals on

• Sleep CPU off, peripherals off

• Idle mode currents down to 5.8 µA typical

• Sleep current down to 0.1 µA typical

• Timer1 oscillator, 1.8 µA typical, 32 kHz, 2V

• Watchdog Timer (WDT), 2.1 µA typical

• Two-Speed oscillator start-up

Peripheral Highlight s:

• High current sink/source 25 mA/25 mA

• Three external interrupts

• Two Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resoluti on 6.25ns (T

- Compare is 16-bit, max. resolution 100 ns (T

- PWM output: PWM resolution is 1 to 10 bits

• Enhanced USART module:

- Supports RS-485, RS-232 and LIN 1.2

- Auto-Wake-up on Start bit

- Auto-Baud detect

• RS-232 operation using internal oscillator block
(no external crystal required)

CY/16)

Special Microcontroller Features:

• 100,000 erase/write cycle enhanced Flash
program memory typical

• 1,000,000 erase/write cycle data EEPROM
memory typical

• Flash/data EEPROM retention: 100 years

• Self-programmable under software control

• Priority levels for interrupts

• 8 X 8 Single-cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

• Single-supply In-Circuit Serial Programming™
(ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

- Drives PWM outputs safely when debugging

CY)

Program Memo ry Data Memory

Device

PIC18F2331 8192 4096 768 256 24 5 2 Y Y Y Y 6 1/3
PIC18F2431 16384 8192 768 256 24 5 2 Y Y Y Y 6 1/3
PIC18F4331 8192 4096 768 256 36 9 2 Y Y Y Y 8 1/3
PIC18F4431 16384 8192 768 256 36 9 2 Y Y Y Y 8 1/3

 2003 Microchip Technology Inc. Preliminary DS39616B-page 1

Flash

(bytes)

# Single- Word

Instructions

SRAM
(bytes)

EEPROM

(bytes)

I/O

10-bit

A/D
(ch)

CCP

SPI

SSP

Slave

2

I

C™

EUSART

14-bit

Timers

PWM

8/16-bit

(ch)

Encoder

Quadrature

PIC18F2331/2431/4331/4431

Pin Diagrams

28-Pin SDIP , SOIC

MCLR/VPP/RE3

RA0/AN0

RA1/AN1
RA2/AN2/V
RA3/AN3/V

REF-/CAP1/INDX
REF+/CAP2/QEA

RA4/AN4/CAP3/QEB

DD

AV

AVSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

RC3/T0CKI/T5CKI/INT0

Note 1: Low-voltage programming must be enabled.

40-Pin PDIP

• 1
2
3
4

5
6
7

8
9

10
11
12
13
14

PIC18F2331/2431

28
27
26
25

24
23
22

21
20

19
18
17
16
15

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PWM4/PGM
RB4/KBI0/PWM5
RB3/PWM3
RB2/PWM2
RB1/PWM1
RB0/PWM0

DD

V
VSS
RC7/RX/DT/SDO
RC6/TX/CK/SS
RC5/INT2/SCK/SCL
RC4/INT1/SDI/SDA

(1)

MCLR/VPP/RE3

RA2/AN2/V
RA3/AN3/V

REF-/CAP1/INDX
REF+/CAP2/QEA

RA4/AN4/CAP3/QEB

RA5/AN5/LVDIN

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

RC3/T0CKI

(1)

/T5CKI

RD0/T0CKI/T5CKI

RA0/AN0
RA1/AN1

RE0/AN6
RE1/AN7
RE2/AN8

DD

AV

AVSS

(1)

/INT0

RD1/SDO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30

PIC18F4331/4431

29
28

27
26
25
24
23
22
21

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PWM4/PGM
RB4/KBI0/PWM5
RB3/PWM3
RB2/PWM2

RB1/PWM1
RB0/PWM0

DD

V
VSS
RD7/PWM7
RD6/PWM6

RD5/PWM4
RD4/FLTA
RC7/RX/DT/SDO
RC6/TX/CK/SS
RC5/INT2/SCK
RC4/INT1/SDI

(4)

(3)

(1)

(1)

/SCL

(1)

/SDA

RD3/SCK/SCL
RD2/SDI/SDA

(2)

(1)

(1)

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: Low-voltage programming must be enabled.
3: RD4 is the alternate pin for FLTA

.

4: RD5 is the alternate pin for PWM4.

DS39616B-page 2 Preliminary  2003 Microchip Technology Inc.

Pin Diagrams (Continued)

44-Pin TQFP

PIC18F2331/2431/4331/4431

RC7/RX/DT/SDO

RD4/FLTA

RD5/PWM4

RD6/PWM6
RD7/PWM7

RB0/PWM0
RB1/PWM1
RB2/PWM2
RB3/PWM3

V
VDD

RD2/SDI/SDA

RD1/SDO

RD0/T0CKI/T5CKI

38

39

1819202122

16

17

/VPP/RE3

/INT0

(1)

/T5CKI

(1)

RC3/T0CKI

37

RA0/AN0

RC2/CCP1/FLTB

363435

RA1/AN1

RC1/T1OSI/CCP2/FLTA

NC

33
32
31
30
29
28
27
26
25
24

23

NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7

SS

AV
AVDD
RE2/AN8
RE1/AN7
RE0/AN6
RA5/AN5/LVDIN
RA4/AN4/CAP3/QEB

(1)

(1)

/SCL

/SDA

(1)

(1)

RC6/TX/CK/SS

RC5/INT2/SCK

RC4/INT1/SDI

RD3/SCK/SCL

(1)
(3)
(4)

SS

4443424140

1
2
3
4

PIC18F4331

5
6

PIC18F4431

7
8
9
10
11

121314

NC

NC

15

(2)

RB7/KBI3/PGD

RB6/KBI2/PGC

MCLR

RB4/KBI0/PWM5

RB5/KBI1/PWM4/PGM

REF-/CAP1/INDX

RA3/AN3/VREF+/CAP2/QEA

RA2/AN2/V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: Low-voltage programming must be enabled.
3: RD4 is the alternate pin for FLTA

.

4: RD5 is the alternate pin for PWM4.

 2003 Microchip Technology Inc. Preliminary DS39616B-page 3

PIC18F2331/2431/4331/4431

Pin Diagrams (Continued)

44-Pin QFN

RC7/RX/DT/SDO

RD4/FLTA

RD5/PWM4

RD6/PWM6
RD7/PWM7

AVDD
RB0/PWM0
RB1/PWM1
RB2/PWM2

V
VDD

(1)

(1)

/SCL

/SDA

(1)

(1)

RC6/TX/CK/SS

RC5/INT2/SCK

RC4/INT1/SDI

RD3/SCK/SCL

(1)
(3)
(4)

SS

4443424140

1
2
3
4

PIC18F4331

5
6

PIC18F4431

7
8
9
10
11

121314

NC

RB3/PWM3

15

(2)

RB4/KBI0/PWM5

(1)

(1)

RD2/SDI/SDA

RD1/SDO

RD0/T0CKI/T5CKI

38

39

1819202122

16

17

/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

MCLR

/INT0

/T5CKI

RC3/T0CKI

37

RA0/AN0

RC2/CCP1/FLTB

363435

RA1/AN1

RC1/T1OSI/CCP2/FLTA

REF-/CAP1/INDX

RC0/T1OSO/T1CKI

33
32
31
30
29
28
27
26
25
24

23

OSC2/CLKO/RA6
OSC1/CLKI/RA7

SS

V
AVSS

AVDD
VDD
RE2/AN8
RE1/AN7
RE0/AN6
RA5/AN5/LVDIN
RA4/AN4/CAP3/QEB

RB5/KBI1/PWM4/PGM

RA3/AN3/VREF+/CAP2/QEA

RA2/AN2/V

Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin

for SCK/SCL.

2: Low-voltage programming must be enabled.
3: RD4 is the alternate pin for FLTA

.

4: RD5 is the alternate pin for PWM4.

DS39616B-page 4 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

Table of Contents

1.0 Device Overview ..........................................................................................................................................................................7

2.0 Oscillator Configurations............................................................................................................................................................ 21

3.0 Power-Managed Modes........................................ .. .... .. .. ....... .... .. .. .... .. ....... .. .... .. .... .. ....... .. .... .................................................... 31

4.0 Reset.......................................................................................................................................................................................... 45

5.0 Memory Organization................................................................................................................................................................. 57

6.0 Flash Prog ram Memory.............................. .......................... ......................... ............ ................................................................. 75

7.0 Data EEPROM Mem o ry...................................... ......................... ......................... ..................................................................... 85

8.0 8 X 8 Hardware Multiplie r................. ............................................................................ ..............................................................89

9.0 Interrupts....................................................................................................................................................................................91

10.0 I/O Ports.................... ............ ............. ......................... ............. ......................... ....................................................................... 107

11.0 Timer0 Module .........................................................................................................................................................................133

12.0 Timer1 Module .........................................................................................................................................................................137

13.0 Timer2 Module .........................................................................................................................................................................143

14.0 Timer5 Module .........................................................................................................................................................................145

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 151

16.0 Motion Feedback Module........................................ .. .... .. ....... .. .... .. .... .. ....... .. .... .. .... .. ....... .. ......................................................159

17.0 Power Control PWM Module ................................................................ ....... .. .... .. .... ....... .... .. ....................................................181

18.0 Synchronous Serial Port (SSP) Module ...................................................................................................................................211

19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 221

20.0 10-bit High-Speed Analog-to-Digital Converter (A/D) Module.................................................................................................. 243

21.0 Low-Voltage Detect.................................................................................................................................................................. 261

22.0 Special Features of the CPU............................................................ ........................................................................................ 267

23.0 Instruction Set Summary.......................................................................................................................................................... 287

24.0 Development Support............................................................................................................................................................... 331

25.0 Electrical Characteristics.......................................................................................................................................................... 337

26.0 Preliminary DC and AC Characteristics Graphs and Tables.................................................................................................... 371

27.0 Packaging Information.............. ......................... ............ .......................... ......................... ........................................................ 373

Appendix A: Revision History.............................................................................................................................................................379

Appendix B: Device Differences ........................................................................................................................................................379

Appendix C: Conversion Considerations ...........................................................................................................................................380

Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 380

Appendix E: Migration from Mid-range to Enhanced Devices ...........................................................................................................381

Appendix F: Migration from High-end to Enhanced Devices ............................................................................................................. 381

INDEX................................................................................................................................................................................................ 383

On-Line Support................................................................................................................................................................................. 391

Systems Information and Upgrade Hot Line......................................................................................................................................391

Reader Response. .............................................................................................................................................................................392

PIC18F2331/2431/4331/4431 Product Identification System ............................................................................................................ 393

 2003 Microchip Technology Inc. Preliminary DS39616B-page 5

PIC18F2331/2431/4331/4431

TO OUR VALUED CUSTOMERS

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DS39616B-page 6 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:

• PIC18F2331 • PIC18F4331

• PIC18F2431 • PIC18F4431

This family offers the advantages of all PIC18 micro­controllers – namely, high computational performance
at an economical pr ice, with the addi tion of h igh end ur­ance enhanced Flash program memory and a high­speed 10-bit A/D converter. On top of these features,
the PIC18F2331/2431/4331/4431 family introduces
design enhancements that make these microcontrol­lers a logical choic e for m any hi gh perfo rmanc e, power
control and motor control applications. These special
peripherals include:

• 14-bit resolution Power Control PWM Module
(PCPWM) with programmable dead time insertion

• Motion Feedback Module (MFM), including a
3-channel Input Capture (IC) Module and
Quadrature Encoder Interface (QEI)

• High-speed 10-bit A/D Converter (HSADC)

The PCPWM can generate up to eight complementary
PWM outputs w ith dead-band time inse rtion. Overd rive
current is detected by off-chip analog comparators or
the digital fault inputs (FLTA

The MFM Quadrature Encoder Interface provides
precise rotor position feedback and/or velocity
measurement. The MFM 3 X input capture or external
interrupts can be used to detect the rotor state for
electrically commutated motor applications using Hall
Sensor feedback, such as BLDC motor drives.

PIC18F2331/2431/4331/4431 devices also feature
Flash program memory and an internal RC oscillator
with built-in LP modes.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2331/2431/4331/4431
family incorporate a range of features that can signifi­cantly reduce power consumption during operation.
Key items include:

• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run
with its CPU core disabled, bu t the peripheral s are
still active. In these states, power consumption
can be reduced even further, to as little as 4% of
normal operation requiremen t s.

, FLTB).

• On-the-fly Mode Switching: The power-man­aged modes are invoked by user code during
operation, allowing the user to incorporate power
saving ideas into their application’s software
design.

• Lower Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer have been reduced by up to
80%, with typical values of 1.1 and 2.1 µA,
respectively.

1.1.2 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F2331/2431/4331/4431
family offer nine different oscillator options, allowing
users a wide range o f choices i n develo ping applica tion
hardware. These include:

• Four crystal modes, using crystals or ceramic
resonators.

• Two external clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).

• Two external RC oscillator modes, with the same
pin options as the external clock modes.

• An internal oscillator block , which provides an
8 MHz clock and an INTRC source (approxi­mately 31 kHz, stable over temperature and V
as well as a range of 6 user-selectable clock fre­quencies (from 125 kHz to 4 MHz) for a total of 8
clock frequencies.

Besides its ava ilability as a cloc k source, the intern al
oscillator block pro vid es a s t ab le re fere nce source that
gives the family additional features for robust
operation:

• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a
reference signal provided by the internal
oscillator. If a clock failure occ urs, the con troller i s
switched to the internal oscillator block, allowing
for continued low speed operation or a safe
application shutdown.

• Two-Speed Start-up: This optio n allows the
internal oscillator to serve as the clock source
from Power-on Reset or wake-up from Sleep
mode, until the primary clock source is available.
This allows for code execution during what would
otherwise be the clock start-up interval, and can
even allow an application to perform routine
background activities and return to Sleep without
returning to full power operation.

DD),

 2003 Microchip Technology Inc. Preliminary DS39616B-page 7

PIC18F2331/2431/4331/4431

1.2 Other Special Features

• Memory Endurance: The enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 100 years.

• Self-programmability: These devices can write
to their own program memory spaces under inter­nal software control. By us ing a bootloader routi ne
located in the protected Boot Block at the top of
program memory, it becomes possible to create
an application that can update itself in the field.

• Power Control PWM Module: In PWM mode,
this module provides 1, 2 or 4 modulated outputs
for controlling half-bridge and full-bridge drivers.
Other features include Auto- Shutdown on fault
detection and Auto-Restart to reactivate outputs
once the condition has cleared.

• Enhanced USART: This serial communication
module is capable of standard RS-232 operation
using the internal oscillator block, removing the
need for an external crystal (and its accompany­ing power requirement) in applications that talk to
the outside worl d. This modul e al so incl udes au to­baud detect and LIN capability.

• High-speed 10-bit A/D Converter: This module
incorporates Programmable Acquisition Time,
allowing for a channel to be selected and a
conversion to be initiated without waiting for a
sampling period and thus, reducing code
overhead.

• Motion Feedback Module (MFM): This mod ule
features a Quadrature Encoder Interface (QEI)
and an Input Capture (IC) module. The QEI
accepts two phase inputs (QEA, QEB) and one
index input (INDX) from an incremental encoder.
The QEI supports high and low precision position
tracking, direction status and change of direction
interrupt, and velocity measurement. The input
capture features 3 channels of independent input
capture with Timer5 as the time base, a special
event trigger to other modules, and an adjustable
noise filter on each IC input.

• Extended Watchdog Timer (WDT): This
enhanced version in corpora tes a 16 -bit pre scale r,
allowing a time-out range from 4 ms to over 2
minutes, that is stable across ope rati ng vol tage
and temperature.

DS39616B-page 8 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

1.3 Details on Individual Family Members

Devices in the PIC18F 2331/2431/43 31/4431 famil y are
available in 28-pin (PIC18F2X31) and 40/44-pin
(PIC18F4X31) packages. The block diagram for the
two groups is shown in Figure 1-1.

The devices are differentiated from each other in three
ways:

1. Flash program memory (8 Kbytes for
PIC18F2X31 devices, 16 Kbytes for
PIC18F4X31).

2. A/D channels (5 for PIC18F2X31 devices, 9 for
PIC18F4X31 devices).

3. I/O ports (3 bidirectional ports on PIC18F2X31
devices, 5 bidirectional ports on PIC18F4X31
devices).

All other features fo r device s in this family are identi cal.
These are summarized in Table1-1.

The pinouts for all devices are listed in Table 1-2 and
Table 1-3.

TABLE 1-1: DEVICE FEATURES

Features PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431

Operating Frequency
Program Memory (Bytes) 8192 16384 8192 16384

Program Memory (Instruction s) 4096 8192 4096 8192
Data Memory (Bytes) 768 768 768 768
Data EEPROM Memory (Bytes) 256 256 256 256
Interrupt Sources 22 22 34 34
I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM modules 2 2 2 2
14-bit Power Control PWM (6 Channels) (6 Channels) (8 Channels) (8 Channels)
Motion Feedback module

(Input Capture/Quad rature Encoder
Interface)

Serial Communications SSP,

10-bit High-Speed
Analog-to-Digital Converter module

Resets (and Delays) POR, BOR,

Programmable Low-voltag e Det ect Y e s Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions
Packages

DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz

1 QEI

or

3x IC

Enhanced USART

5 Input Channels 5 Input Channels 9 Input Channels 9 Input Channels

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

28-pin SDIP
28-pin SOIC

1 QEI

or

3x IC

SSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stac k U nde rflo w

(PWRT, OST),

(optional),

MCLR

WDT

28-pin SDIP
28-pin SOIC

1 QEI

or

3x IC

SSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

40-pin DIP

44-pin TQFP

44-pin QFN

1 QEI

or

3x IC

SSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

40-pin DIP

44-pin TQFP

44-pin QFN

 2003 Microchip Technology Inc. Preliminary DS39616B-page 9

PIC18F2331/2431/4331/4431

FIGURE 1-1: PIC18F2331/2431 BLOCK DIAGRAM

Data Bus<8>

21

Address Latch

Program Memory

Data Latch

16

OSC2/CLKO
OSC1/CLKI

T1OSI
T1OSO

/VPP

MCLR

VDD, VSS

21

Table Pointer<21>

21

inc/dec logic

20

TABLELATCH

8

Instruction

Decode &

Control

Timing

Generation

4X PLL

Precision
Band Gap
Reference

PCLATH

PCLATU

PCH PCL

PCU
Program Counter

31 Level Stack

ROMLATCH

IR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Power

Managed

Mode Logic

INTRC

OSC

8

8

Decode

BITOP

4

BSR

3

8

Data Latch

Data RAM

(768 bytes)

Address Latch

12

Address<12>

12 4

Bank0, F

FSR0
FSR1
FSR2

inc/dec

logic

PRODLPRODH

8 x 8 Multiply

W

8

8

ALU<8>

8

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RA4/AN4/CAP3/QEB
OSC2/CLKO/RA6
OSC1/CLKI/RA7

PORTB

12

PORTC

8

8

8

PORTE

RB0/PWM0
RB1/PWM1
RB2/PWM2
RB3/PWM3
RB4/KBI0/PWM5
RB5/KBI1/PWM4/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB
RC3/T0CKI/T5CKI/INT0
RC4/INT1/SDI/SDA
RC5/INT2/SCK/SCL
RC6/TX/CK/SS
RC7/RX/DT/SDO

MCLR/VPP/RE3

(1, 2)

Timer0 Timer1 Timer2

Data EE

CCP1

CCP2

Synchronous

Serial Port

Timer5

EUSART

HS 10-bit

ADC

PCPWM

AVDD, AVSS

MFM

Note 1: RE3 input pin is only enabled when MCLRE fuse is programmed to ‘0’.

2: RE3 is available only when MCLR is disabled.

DS39616B-page 10 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

FIGURE 1-2: PIC18F4331/4431 BLOCK DIAGRAM

Data Bus<8>

21

Address Latch

Program Memory

Data Latch

16

OSC2/CLKO
OSC1/CLKI

T1OSI
T1OSO

/VPP

MCLR

VDD, VSS

21

Table Pointer<21>

21

inc/dec logic

20

TABLELAT CH

8

Instruction

Decode &

Control

Timing

Generation

4X PLL

Precision
Band Gap
Reference

PCLATH

PCLATU

PCH PCL

PCU
Program Counter

31 Level Stack

ROMLATCH

IR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Power

Managed

Mode Logic

INTRC

OSC

8

8

Decode

BITOP

4

BSR

3

8

Data Latch

Data RAM
(768 bytes)

Address Latch

Address<12>

12 4

FSR0
FSR1
FSR2

inc/dec

logic

8 x 8 Multiply

W

8

8

ALU<8>

12

Bank0, F

PRODLPRODH

8

PORTA

PORTB

12

PORTC

8

8

PORTD

8

PORTE

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RA4/AN4/CAP3/QEB
RA5/AN5/LVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7

RB0/PWM0
RB1/PWM1
RB2/PWM2
RB3/PWM3
RB4/KBI0/PWM5
RB5/KBI1/PWM4/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB
RC3/T0CKI/T5CKI/INT0
RC4/INT1/SDI/SDA
RC5/INT2/SCK/SCL
RC6/TX/CK/SS
RC7/RX/DT/SDO*

RD0/IT0CKI/T5CKI
RD1/SDO
RD2/SDI/SDA
RD3/SCK/SCL
RD4/FLTA
RD5/PWM4
RD6/PWM6
RD7/PWM7

RE0/AN6
RE1/AN7

RE2/AN8
MCLR/VPP/RE3

(2)

(4)

(2)

(3)

(3)

(3)

(4)

(1)

Timer0 Timer1 Timer2

Data EE

CCP1
CCP2

Synchronous

Serial Port

Timer5

EUSART

HS 10-bit

ADC

PCPWM

AVDD, AVSS

MFM

Note 1: RE3 is available only when MCLR is disabled.

2: RD4 is the alternate pin for FLTA.
3: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL

respectively.

4: RD5 is the alternate pin for PWM4.

 2003 Microchip Technology Inc. Preliminary DS39616B-page 11

PIC18F2331/2431/4331/4431

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS

Pin Name

Pin

Number

DIP SOIC

Pin

Type

Buffer

Type

Description

/VPP/RE3

MCLR

MCLR
VPP

RE3

OSC1/CLKI/RA7

OSC1
CLKI

RA7

OSC2/CLKO/RA6

OSC2
CLKO
RA6

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
V
CAP1
INDX

RA3/AN3/V

RA3
AN3
V
CAP2
QEA

RA4/AN4/CAP3/QEB

RA4
AN4
CAP3
QEB

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

REF-/CAP1/INDX

REF-

REF+/CAP2/QEA

REF+

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-Drain (no diode to V

11

99

10 10

22

33

44

55

66

I

ST

P

I

ST

I

ST

I

CMOS

I/O

TTL

O

—

O

—

I/O

TTL

I/OITTL

Analog

I/OITTL

Analog

I/O

TTL

I

Analog

I

Analog

I

ST

I

ST

I/O

TTL

I

Analog

I

Analog

I

ST

I

ST

I/O

TTL

I

Analog

I

ST

I

ST

DD)

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
High-voltage ICSP programming enable pin.
Digital input. Available only when MCLR

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and de notes the in struc tion cycl e rate.
General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
Input capture pin 1.
Quadrature Encoder Interface index input pin.

Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
Input capture pin 2.
Quadrature Encoder Interface channel A input pin.

Digital I/O.
Analog input 4.
Input capture pin 3.
Quadrature Encoder Interface channel B input pin.

is disabled.

DS39616B-page 12 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

T ABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RB0/PWM0

RB0
PWM0

RB1/PWM1

RB1
PWM1

RB2/PWM2

RB2
PWM2

RB3/PWM3

RB3
PWM3

RB4/KBI0/PWM5

RB4
KBI0
PWM5

RB5/KBI1/PWM4/PGM

RB5
KBI1
PWM4
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-Drain (no diode to V

Number

DIP SOIC

21 21

22 22

23 23

24 24

25 25

26 26

27 27

28 28

Pin

Buffer

Type

Type

I/OOTTL

I/OOTTL

I/OOTTL

I/OOTTL

I/O

I

O

I/O

I

O

I/O

I/O

I

I/O

I/O

I

I/O

DD)

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all in puts.

Digital I/O.

TTL

TTL

TTL

TTL

TTL
TTL
TTL

TTL
TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

PWM output 0.

Digital I/O.
PWM output 1.

Digital I/O.
PWM output 2.

Digital I/O.
PWM output 3.

Digital I/O.
Interrupt-on-change pin.
PWM output 5.

Digital I/O.
Interrupt-on-change pin.
PWM output 4.
Low-voltage ICSP programming entry pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

 2003 Microchip Technology Inc. Preliminary DS39616B-page 13

PIC18F2331/2431/4331/4431

TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/CCP2/FLTA

RC1
T1OSI
CCP2
FLTA

RC2/CCP1/FLTB

RC2
CCP1
FLTB

RC3/T0CKI/T5CKI/INT0

RC3
T0CKI
T5CKI
INT0

RC4/INT1/SDI/SDA

RC4
INT1
SDI
SDA

RC5/INT2/SCK/SCL

RC5
INT2
SCK
SCL

RC6/TX/CK/SS

RC6
TX
CK
SS

RC7/RX/DT/SDO

RC7
RX
DT
SDO

SS 8, 19 8, 19 P — Ground reference for logic and I/O pins.

V
VDD 7, 20 7, 20 P — Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-Drain (no diode to V

Number

DIP SOIC

11 11

12 12

13 13

14 14

15 15

16 16

17 17

18 18

Pin

Type

I/O

O

I

I/O

I

I/O

I

I/O
I/O

I

I/O

I
I
I

I/O

I
I

I/O

I/O

I
I/O
I/O

I/O

O

I/O

I

I/O

I
I/O

O

DD)

Buffer

Type

ST

—

ST

ST

CMOS

ST
ST

ST
ST
ST

ST
ST
ST
ST

ST
ST
ST
ST

ST
ST
ST
ST

ST

—

ST

TTL

ST
ST
ST

—

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
Fault interrupt input pin.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
Fault interrupt input pin,.

Digital I/O.
Timer0 alternate clock input.
Timer5 alternate clock input.
External interrupt 0.

Digital I/O.
External interrupt 1.
SPI™ data in.

2

C™ data I/O.

I

Digital I/O.
External interrupt 2.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock (see related RX/DT).
SPI Slave Select input.

Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data (see related TX/CK).
SPI data out.

2

C mode.

DS39616B-page 14 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

T ABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS

Pin Name

MCLR

/VPP/RE3

MCLR
VPP

RE3

OSC1/CLKI/RA7

OSC1
CLKI
RA7

OSC2/CLKO/RA6

OSC2
CLKO
RA6

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V
INDX

RA2
AN2
V
CAP1
INDX

RA3/AN3/V
CAP2/QEA

RA3
AN3
V
CAP2
QEA

RA4/AN4/CAP3/QEB

RA4
AN4
CAP3
QEB

RA5/AN5/LVDIN

RA5
AN5
LVDIN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

REF-/CAP1/

REF-

REF+/

REF+

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-Drain (no diode to V

Pin Number

DIP TQFP QFN

11818

13 30 32

14 31 33

21919

32020

42121

52222

62323

72424

Pin

Buffer

Type

Type

I

P

I

I

CMOS

I

I/O

O
O

I/O

I/OITTL

Analog

I/OITTL

Analog

I/O

Analog

I

Analog

I
I
I

I/O

Analog

I

Analog

I
I
I

I/O

I

Analog
I
I

I/O

I

Analog
I

Analog

DD)

Description

Master Clear (input) or programming voltage (input).

ST

ST

ST

TTL

—
—

TTL

TTL

ST
ST

TTL

ST
ST

TTL

ST
ST

TTL

Master Clear (Reset) input. This pin is an active-low.
Reset to the device.
Programming voltage inpu t.
Digital input. Available only when MCLR

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
Input capture pin 1.
Quadrature Encoder Interface index input pin.

Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
Input capture pin 2.
Quadrature Encoder Interface channel A input pin.

Digital I/O.
Analog input 4.
Input capture pin 3.
Quadrature Encoder Interface channel B input pin.

Digital I/O.
Analog input 5.
Low-voltage Detect input.

is disabled.

 2003 Microchip Technology Inc. Preliminary DS39616B-page 15

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/PWM0

RB0
PWM0

RB1/PWM1

RB1
PWM1

RB2/PWM2

RB2
PWM2

RB3/PWM3

RB3
PWM3

RB4/KBI0/PWM5

RB4
KBI0
PWM5

RB5/KBI1/PWM4/
PGM

RB5
KBI1
PWM4
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-Drain (no diode to V

Pin Number

DIP TQFP QFN

33 8 9

34 9 10

35 10 11

36 11 12

37 14 14

38 15 15

39 16 16

40 17 17

Pin

Buffer

Type

Type

I/OOTTL

I/OOTTL

I/OOTTL

I/OOTTL

I/O

I

O

I/O

I

O

I/O

I/O

I

I/O

I/O

I

I/O

DD)

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.

TTL

TTL

TTL

TTL

TTL
TTL
TTL

TTL
TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

PWM output 0.

Digital I/O.
PWM output 1.

Digital I/O.
PWM output 2.

Digital I/O.
PWM output 3.

Digital I/O.
Interrupt-on-change pin.
PWM output 5.

Digital I/O.
Interrupt-on-change pin.
PWM output 4.
Low-voltage ICSP programming entry pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

DS39616B-page 16 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

T ABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/CCP2/
FLTA

RC1
T1OSI
CCP2
FLTA

RC2/CCP1/FLTB

RC2
CCP1
FLTB

RC3/T0CKI/T5CKI/
INT0

RC3
T0CKI
T5CKI
INT0

RC4/INT1/SDI/SDA

RC4
INT1
SDI
SDA

RC5/INT2/SCK/SCL

RC5
INT2
SCK
SCL

RC6/TX/CK/SS

RC6
TX
CK
SS

RC7/RX/DT/SDO

RC7
RX
DT
SDO

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-Drain (no diode to V

Pin Number

DIP TQFP QFN

15 32 34

16 35 35

17 36 36

18 37 37

23 42 42

24 43 43

25 44 44

26 1 1

Pin

Type

I/O

O

I

I/O

I

I/O

I

I/O
I/O

I

I/O

I
I
I

I/O

I
I

I/O

I/O

I

I/O
I/O

I/O

O

I/O

I

I/O

I

I/O

O

DD)

Buffer

Type

ST

—

ST

ST

CMOS

ST
ST

ST
ST
ST

ST
ST
ST
ST

ST
ST
ST
ST

ST
ST
ST
ST

ST

—
ST
ST

ST
ST
ST

—

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
Fault interrupt input pin.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
Fault interrupt input pin.

Digital I/O.
Timer0 alternate clock input.
Timer5 alternate clock input.
External interrupt 0.

Digital I/O.
External interrupt 1.
SPI Data in.

2

C Data I/O.

I

Digital I/O.
External interrupt 2.
Synchronous serial clock input/output for SPI mode.
Synchron ous serial clock input/o utput for I

Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock (see related RX/DT).
SPI Slave Select input.

Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data (see related TX/CK).
SPI Data out.

2

C mode.

 2003 Microchip Technology Inc. Preliminary DS39616B-page 17

PIC18F2331/2431/4331/4431

TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/T0CKI/T5CKI

RD0
T0CKI
T5CKI

RD1/SDO

RD1
SDO

RD2/SDI/SDA

RD2
SDI
SDA

RD3/SCK/SCL

RD3
SCK
SCL

RD4/FLTA

RD4
FLTA

RD5/PWM4

RD5
PWM4

RD6/PWM6

RD6
PWM6

RD7/PWM7

RD7
PWM7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-Drain (no diode to V

Pin Number

DIP TQFP QFN

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Pin

Buffer

Type

I/O

I
I

I/OOST

I/O

I

I/O

I/O
I/O
I/O

I/OIST

I/OOST

I/OOST

I/OOST

DD)

Type

PORTD is a bidirectional I/O port, or a Parallel Slave Port
(PSP) for interfacing to a microprocessor port. These pins
have TTL input buffers when PSP module is enabled.

ST
ST
ST

—

ST
ST
ST

ST
ST
ST

ST

TTL

TTL

TTL

Digital I/O.
Timer0 external clock input.
Timer5 input clock.

Digital I/O.
SPI Data out.

Digital I/O.
SPI Data in.

2

C Data I/O.

I

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
Fault interrupt input pin.

Digital I/O.
PWM output 4.

Digital I/O.
PWM output 6.

Digital I/O.
PWM output 7.

Description

2

C mode.

DS39616B-page 18 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

T ABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/AN6

RE0
AN6

RE1/AN7

RE1
AN7

RE2/AN8

RE2
AN8

SS 12,

V

VDD 11, 32 7, 28 7, 8,

NC — 12,

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-Drain (no diode to V

Pin Number

DIP TQFP QFN

82525

92626

10 27 27

6, 29 6, 30, 31P — Ground reference for logic and I/O pins.

31

13,

33, 34

Pin

Buffer

Type

Type

PORTE is a bidirectional I/O port.

I/OIST

Analog

I/OIST

Analog

I/OIST

Analog

P — Positive supply for logic and I/O pins.

28,

29
13 NC NC No connect

DD)

Digital I/O.
Analog input 6.

Digital I/O.
Analog input 7.

Digital I/O.
Analog input 8.

Description

 2003 Microchip Technology Inc. Preliminary DS39616B-page 19

PIC18F2331/2431/4331/4431

NOTES:

DS39616B-page 20 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

The PIC18F2331/2431/4331/4431 devices can be
operated in 10 di fferent oscillator modes. The u ser ca n
program the configuratio n bit s FOSC3:FOSC0 in Confi g­uration register 1H to select one of these 10 modes:

1. LP Low-power Crystal

2. XT Crystal/Resonator

3. HS High-speed Crystal/Resonator

4. HSPLL High-speed Crystal/Resonator

with PLL enabled

5. RC External Resistor/Capacitor with

F

OSC/4 output on RA6

6. RCIO External Resist or/Capacitor with

I/O on RA6

7. INTIO1 Internal Oscillator with F

output on RA6 and I/O on RA7

8. INTIO2 Intern al Osc illat or with I/O on RA6

and RA7

9. EC External Clock with F

10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.

The oscillator design requires the use of a parallel cut
crystal.

Note: Use of a series cut crystal may give a

frequency out of the crystal
manufacturers’ specifications.

OSC/4

OSC/4 output

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)

(1)

C1

(1)

C2

Note 1: See T able 2-1 and T able 2-2 for initial values of

2: A series res istor (R

3: R

OSC1

XTAL

(2)

RS

OSC2

C1 and C2.

strip cut crystals.

F varies with the oscillator mode chosen.

(3)

RF

Sleep

PIC18FXXXX

S) may be required for AT

To

Internal
Logic

T ABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz
Capacitor values are for design guidance only.
These capacitors were tested with the resonators

listed below for basic start-up and operation. These
values are not optimized.

Different cap acitor values may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes on page 22 for additional information.

Resonators Used:

455 kHz 4.0 MHz

2.0 MHz 8.0 MHz

16.0 MHz

56 pF
47 pF
33 pF

27 pF
22 pF

56 pF
47 pF
33 pF

27 pF
22 pF

 2003 Microchip Technology Inc. Preliminary DS39616B-page 21

PIC18F2331/2431/4331/4431

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc T y pe

Crystal

Freq

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF

4 MHz 27 pF 27 pF

HS 4 MH z 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed

below for basic start-up and op erat ion . These values

are not optimized.

Different capa citor values may be required to produc e
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes following this table for additional

information.

Crystals Used:

32 kHz 4 MHz

200 kHz 8 MHz

1 MHz 20 MHz

Note 1: Higher capacit ance increa ses the st ability

of oscillator, but also increases the start­up time.

2: When operating below 3V V

using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

4: Rs may be requ ired to avoi d overdrivi ng

crystals with low driv e lev e l spe ci fic ati on.

5: Always verify oscilla tor pe rform an ce ov er

DD and temperature range that is

the V
expected for the application.

T ypical Cap acitor V alues

Tested:

C1 C2

DD, or when

An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS OSC
CONFIGURATION)

Clock from
Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.3 HSPLL

A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
crystal oscillator circuit, or to clock the device up to its
highest rated frequency from a crystal oscillator. This
may be useful for customers who are concerned with
EMI due to high-frequency crystals.

The HSPLL mode make s use of the HS mode osc illator
for frequencies up t o 10 MHz. A PLL then multipl ies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.

The PLL is enabled only when the oscillator configura­tion bits are programmed for HSPLL mode. If
programmed for any other mode, the PLL is not
enabled.

FIGURE 2-3: PLL BLOCK DIAGRAM

HS Osc Enable

PLL Enable

(from Configuration Register 1H)

OSC2

OSC1

HS Mode

Crystal

Osc

F

IN

FOUT

÷4

Phase

Comparator

Loop
Filter

VCO

SYSCLK

MUX

DS39616B-page 22 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

2.4 External Clock Input

The EC and ECIO os c ill ato r m ode s require an external
clock source to be conn ected to the OSC1 pi n. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.

FIGURE 2-4: EXTER NAL CLOCK INPUT

OPERATION
(EC CONFIGURATION)

Clock from
Ext. System

OSC/4

F

The ECIO Oscillator mode func ti ons li ke t he EC m od e,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.

FIGURE 2-5: EXTER NAL CLOCK INPUT

Clock from
Ext. System

RA6

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

OPERATION
(ECIO CONFIGURATION)

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

2.5 RC Oscillator

For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R
values and the operating temperature. In addition to
this, the oscillator frequency will vary from unit to unit
due to normal manufacturing variation. Furthermore,
the difference in lead frame capacitance between
package type s wi ll also affect the os cillation frequenc y,
especially for low C
take into account variation due to tolerance of external
R and C components used. Figure 2-6 shows how the
R/C combination is connected.

In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic.

FIGURE 2-6: RC OSCILLATOR MODE

VDD

REXT

CEXT

VSS

F

OSC/4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

The RCIO Oscillator mode (Figure 2-7) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).

EXT) and capacitor (CEXT)

EXT values. Th e user also needs to

OSC1

Internal

Clock

PIC18FXXXX

OSC2/CLKO

EXT > 20 pF

C

FIGURE 2-7: RCIO OSCILLATOR MODE

VDD

REXT

OSC1

CEXT

VSS

RA6

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

 2003 Microchip Technology Inc. Preliminary DS39616B-page 23

I/O (OSC2)

C

EXT > 20 pF

Internal

Clock

PIC18FXXXX

PIC18F2331/2431/4331/4431

2.6 Internal Oscillator Block

The PIC18F2331/2431/4331/4431 devices include an
internal oscillator block, which generates two different
clock signals; ei ther can be used a s t he s y ste m’s clock
source. This can eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the system clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator
(INTRC), which provides a 31kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source, or when any of the
following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Spe ed Start-up
These features are discussed in greater detail in

Section 2 2.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC

direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register 2-2).

2.6.2 INTRC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
This changes the frequency of the INTRC source from
its nominal 31.25 kHz. Peripherals and features that
depend on the INTRC source will be affected by this
shift in frequency.

2.6.3 OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at
the factory, but can be adjusted in the user's applica­tion. Thi s is do ne by writi ng to the OS CTUNE regi ster
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.

When the OSCTUNE regis ter is mo di fied , the IN T O SC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new fre­quency within 8clock cycles (approximately
8*32µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during th is shi ft.
There is no indicati on that th e shift ha s occurre d. Oper­ation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in frequency.

2.6.1 INTIO MODES

Using the internal oscillator as the clock source can
eliminate the need for up t o two extern al oscilla tor pins,
which can then be used for digital I/O. Two distinct
configurations are available:

• In INTIO1 mode, the OSC2 pin outputs F
while OSC1 functions as RA 7 fo r dig it a l in put a nd
output.

• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.

OSC/4,

DS39616B-page 24 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

bit 7, 6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits

011111 = Maximum frequency

• •

• •

000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111

• •

• •
100000 = Minimum frequency

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. Preliminary DS39616B-page 25

PIC18F2331/2431/4331/4431

2.7 Clock Sources and Oscillator

Switching

Like previous PIC18 devices, the PIC18F2331/2431/
4331/4431 devices include a feature that allows the
system clock source to be switched from the main
oscillator t o an alternate lo w frequency clock s ource.
PIC18F2331/2431/4331/4431 devices offer two alter­nate clock sources. When enabled, these give addi­tional options for switching to the various power­managed operating modes.

Essentially, there are three clock sources for these
devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the external crystal
and resonator modes, the external RC modes, the
external clock modes and the internal oscillator block.
The particular mod e is defined on POR by the content s
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.

The s econdary oscillat ors are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.

PIC18F2331/2431/4331/4431 devices offer only the
Timer1 oscillator as a secondary oscillator. This
oscillator, in all power-managed modes, is often the
time base for functions such as a real-time clock.

Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO and RC1/T1OSI pins. Like
the LP mode oscillator circuit, loading capacitors are
also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in
Section 1 2.2 “Timer1 Oscillator”.

In addition to being a p rimary clock source, the internal
oscillator block is available as a power-managed
mode clock source. The INTRC source is a lso us ed as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2331/2431/4331/
4431 devices are shown in Figure 2-8. See
Section 12.0 “Timer1 Module” for further details of
the Timer1 oscillator. See Section 22.1 “Configura-
tion Bits” for Configurati on register details.

2.7.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power-managed modes.

The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating
in power-managed mod es. The availab le clock sources
are the primary clock (defined in Configuration register
1H), the secondary clock (Timer1 oscillator) and the
internal oscillator block. The clock selection has no
effect until a SLEEP instruction is executed and the
device enters a power-managed mode of operation.
The SCS bits are cleared on all forms of Reset.

The Internal Oscill ator Select bit s, IRCF2:IRCF0, select
the frequency output of the interna l oscill ator block th at
is used to dr ive t he sys tem clo ck. Th e choi ces are t he
INTRC source, the INTOSC source (8 MHz) or one of
the six frequencies derived from the INTOSC
postscaler (125kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of thes e bits w ill ha ve an immedi ate cha nge on
the internal oscillator’s output.

The OSTS, IOFS and T1RUN bits ind icate wh ich cl oc k
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer has
timed out, and the p rimary clock i s providing the s ystem
clock in pri mary clock mode s. The IOFS b it indicates
when the internal oscillator block has stabilized, and is
providing the system clock in RC clock modes. The
T1RUN bit (T1CON<6>) indicates when the Timer1
oscillator is providing the system clock in secondary
clock modes. In power-managed modes, only one of
these three bits will be se t at any time. If none of these
bits are set, the INTRC is providi ng the syste m clock, or
the internal oscillator block has just started and is not
yet stable.

The IDLEN bit controls the selective shut down of the
controller’s CPU in power-man aged modes. Th e use of
these bits is discussed in more detail in Section 3.0

“Power-Managed Modes”

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The
Timer1 osc illator is enabled by s etting the
T1OSCEN bit in th e T imer1 C ontrol re gis­ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any at tem pt to se lec t
a secondary clock source when execut­ing a SLEEP instruction will be ignored.

2: It is recommended that the Timer1 oscil-

lator be operating and stable before exe­cuting the SLEEP instruction, or a very
long delay may occur while the Timer1
oscillator starts.

DS39616B-page 26 Preliminary  2003 Microchip Technology Inc.

PIC18F2331/2431/4331/4431

FIGURE 2-8: PIC18F2331/2431/4331/4431 CLOCK DIAGRAM

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

Secondary Oscillator

T1OSCEN
Enable
Oscillator

OSCCON<6:4>

Internal

Oscillator

Block

INTRC

Source

PIC18F2331/2431/4331/4431

8 MHz
4 MHz
2 MHz
1 MHz

8 MHz

(INTOSC)

Postscaler

500 kHz
250 kHz
125 kHz

31 kHz

4 x PLL

OSCCON<6:4>

111

110

101

100

MUX

011

010

001

000

C4NFIG1H <3:0>

HSPLL

LP, XT, HS, RC, EC

T1OSC

Clock Source Option
for Other Modules

Internal Oscillator

Clock

Control

MUX

OSCCON<1:0>

Peripherals

CPU

IDLEN

WDT, FSCM

 2003 Microchip Technology Inc. Preliminary DS39616B-page 27

PIC18F2331/2431/4331/4431

REGISTER 2-2: OSCCON REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

bit 7 IDLEN: Idle Enable bit

1 = Idle mode enabled; CPU core is not clocked in power-managed modes
0 = Run mode enabled; CPU core is clocked in power-managed modes

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 M Hz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 k Hz
010 = 250 k Hz
001 = 125 k Hz
000 = 31 kHz (INTRC source drives clock directly)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Oscillator start-up time-out timer has expired; primary oscillator is running
0 = Oscillator start-up time-out timer is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits

1x = Internal oscillator block (RC modes)
01 = Timer1 oscillator (Secondary modes)
00 = Primary oscillator (Sleep and PRI_IDLE modes)

Note 1: Depends on state of the IESO bit in Configuration Register 1H.

(1)

R-0 R/W-0 R/W-0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

2.7.2 OSCILLATOR TRANSITIONS

The PIC18F2331/2431/4331/4431 devices contain
circuitry to prevent clocking “glitches” when switching
between clock sources. A short pause in the system
clock occurs during the clock switc h. Th e leng th of thi s
pause is between 8 and 9 clock periods of the new
clock source. This ensures that the new clock source is
stable and that its pulse width will not be less than the
shortest pulse width of the two clock sources.

Clock transitions are discussed in greater detail in
Section 3 .1.2 “Entering Power-Managed Modes”.

DS39616B-page 28 Preliminary  2003 Microchip Technology Inc.