MICROCHIP PIC18F2220, PIC18F2320, PIC18F4220, PIC18F4320 DATA SHEET

PIC18F2220/2320/4220/4320

Data Sheet

28/40/44-Pin High-Performance,

Enhanced Flash Microcontrollers

with 10-Bit A/D and nanoWatt Technology

 2003 Microchip Technology Inc. DS39599C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, MPLAB, PIC, PICmic ro, PI C START,

PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartT el and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of develop m ent
systems is ISO 9001 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

DS39599C-page ii  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

28/40/44-Pin High-Performance, Enhance d Flash MCUs

with 10-bit A/D and nanoWatt Technology

Low-Power Features:

• Power Managed modes:

- Run: CP U on, peripherals on

- Idle: CPU off, peripherals on

- Sleep: CPU off, peripherals off

• Power Consumption modes:

- PRI_RUN: 150 µA, 1 MHz, 2V

- PRI_IDLE: 37 µA, 1 MHz, 2V

- SEC_RUN: 14 µA, 32 kHz, 2V

- SEC_IDLE: 5.8 µA, 32 kHz, 2V

- RC_RUN: 110 µA, 1 MHz, 2V

- RC_IDLE: 52 µA, 1 MHz, 2V

- Sleep: 0.1 µA, 1 MH z, 2V

• Timer1 Oscillator: 1.1 µA, 32 kHz, 2V

• Watchdog Timer: 2.1 µA

• Two-Speed Oscillator Start-up

Oscillators:

• Four Crystal modes:

- LP, XT, HS: up to 25 MHz

- HSPLL: 4-10 MHz (16-40 MHz internal)

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal oscillator block:

- 8 user selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz

- 125 kHz-8 MHz calibrated to 1%

- Two modes select one or two I/O pins

- OSCTUNE – Allows user to shift frequency

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor

- Allows for safe shutdown if peripheral clock stops

Peripheral Highlight s:

• High current sink/source 25 mA/25 mA

• Three external interrupts

• Up to 2 Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution is 6.25 ns (T

- Compare is 16-bit, max. resolution is 100 ns (T

- PWM output: PWM resolution is 1 to 10-bit

• Enhanced Capture/Compare/PWM (ECCP) module:

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead-time

- Auto-Shutdown and Auto-Restart

• Compatible 10-bit, up to 13-channel
Analog-to-Digital Converter module (A/D) with
programmable acqui sit ion time

• Dual analog comparators

• Addressable USART module:

- RS-232 operation using internal oscillator

block (no external crystal required)

CY/16)

CY)

Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced Flash program
memory typical

• 1,000,000 erase/write cycle Data EEPROM memo ry
typical

• Flash/Data EEPROM Retention: > 40 years

• Self-programmable under software control

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

- 2% stability over V

• Single-supply 5V In-Circuit Serial Programming™
(ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Wide operating voltage range: 2.0V to 5.5V

DD and Temperature

Program Memory Data Memory

Device

PIC18F2220 4096 2048 512 256 25 10 2/0 Y Y Y 2 2/3
PIC18F2320 8192 4096 512 256 25 10 2/0 Y Y Y 2 2/3
PIC18F4220 4096 2048 512 256 36 13 1/1 Y Y Y 2 2/3
PIC18F4320 8192 4096 512 256 36 13 1/1 Y Y Y 2 2/3

 2003 Microchip Technology Inc. DS39599C-page 1

Flash

(bytes)

# Single Word

Instructions

SRAM
(bytes)

EEPROM

(bytes)

I/O

10-bit

A/D (ch)

CCP/

ECCP

(PWM)

SPI™

MSSP

Master

USART

2

C™

I

Timers

8/16-bit

Comparators

PIC18F2220/2320/4220/4320

Pin Diagrams

PDIP

RA2/AN2/V

RA5/AN4/SS

SPDIP, SOIC

RA2/AN2/V

RA5/AN4/SS

MCLR/VPP/RE3

RA0/AN0
RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

/LVDIN/C2OUT

RE0/AN5/RD

RE1/AN6/WR

RE2/AN7/CS

VDD
VSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2*

RC2/CCP1/P1A

RC3/SCK/SCL

RD0/PSP0
RD1/PSP1

MCLR/VPP/RE3

RA0/AN0
RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

/LVDIN/C2OUT

V

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1/P1A

RC3/SCK/SCL

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7

SS

*

8
9

10
11

12
13
14

PIC18F4220

PIC18F2220

PIC18F4320

PIC18F2320

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7/KBI3/PGD
RB6/KBI2/PGC

RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2*
RB2/AN8/INT2

RB1/AN10/INT1
RB0/AN12/INT0
V

DD

VSS
RD7/PSP7/P1D
RD6/PSP6/P1C

RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2

RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2
RB2/AN8/INT2
RB1/AN10/INT1
RB0/AN12/INT0
V

DD

VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

*

* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 40-pin PIC16C7X devices.

DS39599C-page 2  2003 Microchip Technology Inc.

Pin Diagrams (Cont.’d)

TQFP

PIC18F2220/2320/4220/4320

*

RC7/RX/DT

RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

RB0/AN12/INT0
RB1/AN10/INT1

RB2/AN8/INT2

RB3/AN9/CCP2*

V
VDD

SS

1
2
3
4
5
6
7
8
9
10
11

* RB3 is the alternate pin for the CCP2 pin multiplexing.

QFN

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

4443424140

PIC18F4220
PIC18F4320

121314

15

16

NC

NC

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/AN11/KBI0

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

38

39

37

1819202122

17

RA0/AN0

/VPP/RE3

RB7/KBI3/PGD

MCLR

RC2/CCP1/P1A

363435

RA1/AN1

RC1/T1OSI/CCP2

REF-/CVREF

RA2/AN2/V

NC

33
32
31
30
29
28
27
26
25
24

23

RA3/AN3/VREF+

NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7

SS

V
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN/C2OUT
RA4/T0CKI/C1OUT

*

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

RC0/T1OSO/T1CKI

RC7/RX/DT

RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

RB0/AN12/INT0
RB1/AN10/INT1

RB2/AN8/INT2

V
VDD
VDD

4443424140

1
2
3
4

PIC18F4220

SS

5
6

PIC18F4320

7
8
9
10
11

121314

NC

RB3/AN9/CCP2*

39

363435

37

38

16

17

1819202122

15

/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/AN11/KBI0

MCLR

33
32
31
30
29
28
27
26
25
24

23

REF+

RA1/AN1

RA0/AN0

REF-/CVREF

RA3/AN3/V

RA2/AN2/V

OSC2/CLKO/RA6
OSC1/CLKI/RA7

SS

V
VSS
VDD
NC
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN/C2OUT
RA4/T0CKI/C1OUT

* RB3 is the alternate pin for the CCP2 pin multiplexing.

 2003 Microchip Technology Inc. DS39599C-page 3

PIC18F2220/2320/4220/4320

Table of Contents

1.0 Device Overview..........................................................................................................................................................................7

2.0 Oscillator Configurations............................................................................................................................................................ 19

3.0 Power Managed Modes ......................................................................... .. .. .. ..... .... .. .. .. .. .. .. ......................................................... 29

4.0 Reset..........................................................................................................................................................................................43

5.0 Memory Organization................................................................................................................................................................. 53

6.0 Flash Program Memory............... .......................... ......................... ......................... ................................................................... 71

7.0 Data EEPROM Memory....................... ............ .......................... ......................... .......................................................................81

8.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 85

9.0 Interrupts....................................................................................................................................................................................87

10.0 I/O Ports........................ ......................... ............ .......................... ............ ............... ................................................................. 101

11.0 Timer0 Module ......................................................................................................................................................................... 117

12.0 Timer1 Module ......................................................................................................................................................................... 121

13.0 Timer2 Module ......................................................................................................................................................................... 127

14.0 Timer3 Module ......................................................................................................................................................................... 129

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 133

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................141

17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 155

18.0 Addressable Universal Synchronous Asynchronous Receiv er Transmitter (USA RT )..............................................................195

19.0 10-bit Analog-to-Digital Converter (A/D) Module......................................................................................................................211

20.0 Comparator Module............................................................................................. .... .. .... ...........................................................221

21.0 Comparator Voltage Reference Module.................................................................. .... .. .... ....... .. .............................................. 227

22.0 Low-Voltage Detect.................................................................................................................................................................. 231

23.0 Special Features of the CPU................................................................ ....................................................................................237

24.0 Instruction Set Summary.......................................................................................................................................................... 255

25.0 Development Support. .............................................................................................................................................................. 299

26.0 Electrical Characteristics..........................................................................................................................................................305

27.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................343

28.0 Packaging Information.............................. ......................... ...................................... ................................................................. 361

Appendix A: Revision History.............................................................................................................................................................369

Appendix B: Device Differences......................................................................................................................................................... 369

Appendix C: Conversion Considerations ........................................................................................................................................... 370

Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 370

Appendix E: Migration from Mid-Range to Enhanced Devices ..........................................................................................................371

Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 371

Index ..................................................................................................................................................................................................373

On-Line Support........................................................................ .... .. ......... .... .. .... .... ....... .... ................................................................. 383

Systems Information and Upgrade Hot Line...................................................................................................................................... 383

Reader Response..............................................................................................................................................................................384

PIC18F2220/2320/4220/4320 Product Identification System ............................................................................................................385

DS39599C-page 4  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone].
We welcome your feedback.

Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.

 2003 Microchip Technology Inc. DS39599C-page 5

PIC18F2220/2320/4220/4320

NOTES:

DS39599C-page 6  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:

• PIC18F2220 • PIC18F4220

• PIC18F2320 • PIC18F4320

This family offers the advantages of all PIC18 micro­controllers – namely, high computational performance
at an economical price with the addition of high­endurance Enhanced Flash program memory. On top
of these features, the PIC18F2220/2320/4220/4320
family introduces design enhancements that make
these microcontrollers a logical choice for many
high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2220/2320/4220/4320
family incorporate a range of features that can signifi­cantly reduce power consumption during operation.
Key items include:

• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run
with its CPU c ore disable d, but the pe ripherals are
still active. In these states, power consumption can
be reduced even further, to as little as 4% of normal
operation requirements.

• On-the-fly Mode Switching: The power managed
modes are invoked by user code during operation,
allowing th e user to inco rpor ate po wer sav ing id eas
into their application’s software design.

• Lower Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer have been reduced by up to 80%, with typical
values of 1.8 and 2.2 µA, respectively.

1.1.2 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F2220/2320/4220/4320
family offer nine different oscillator options, allowing
users a wide ran ge of choice s in develo ping applic ation
hardware. These include:

• Four Crystal modes using crystals or ceramic
resonators.

• Two External Clock modes offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input with the
second pin reassigned as general I/O).

• Two External RC Oscillator modes with the same
pin options as the External Clock modes.

• An internal oscillator block, which provides a 31 kHz
INTRC clock and an 8 MHz clock with 6 program
selectable divider ratios (4 MHz to 125 kHz) for a
total of 8 clock frequencies.

Besides its ava ilability as a cloc k source, the intern al
oscillator block pro vid es a s t ab le re fere nce source that
gives the family additional features for robust
operation:

• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator block, allowing for continued
low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the internal
oscillator to serve as the clock source from Power-on
Reset, or wake-up from Sleep mode, until the primary
clock source is available. This allows for code execu­tion during what would otherwise be the clock start-up
interval and can even allow an application to perform
routine background activities and return to Sleep
without returning to full power operation.

1.2 Other Special Features

• Memory Endurance: The Enhanced Flash cells for
both program memory and data EEPROM are rated
to last for many thousands of erase/write cycles – up
to 100,000 for program memory and 1,000,000 for
EEPROM. Data retention without refresh is

conservatively estimated to be greater than 40 years.

• Self-programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Block at the top of pro­gram memory, it becomes possible to create an
application that can update itself in the field.

• Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers. Other
features include Auto-Shutdown for disabling PWM
outputs on interrupt or other select conditions and
Auto-Restart to reactivate outputs once the
condition has cleared.

• Addressable USART: This serial communication
module is capable of standard RS-232 operation
using the internal oscillator block, removing the
need for an external crystal (and its accompanying
power requirement) in applications that talk to the
outside world.

• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a chan­nel to be sel ected and a convers ion to be initiated
without waiting for a sampling period and thus,
reduce code overhead.

• Extended Watchdog Timer (WDT): This enhanced
version incorporates a 16-bit prescaler, allowing a
time-out ra nge from 4 ms to over 2 mi nutes, that is
stable across operating voltage and temperature.

 2003 Microchip Technology Inc. DS39599C-page 7

PIC18F2220/2320/4220/4320

1.3 Details on Individual Family Members

Devices in the PIC18F 2220/2320/42 20/4320 famil y are
available in 28-pin (PIC18F2X20) and 40/44-pin
(PIC18F4X20) packages. Block diagrams for the two
groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in five
ways:

1. Flash program memory (4 Kbytes for

PIC18FX220 devices, 8 Kbytes for PIC18FX320)

2. A/D channels (10 for PIC18F2X20 devices, 13 for

PIC18F4X20 devices)

3. I/O ports (3 bidirectional ports and 1 input only
port on PIC18F2X20 devices, 5 bidirectional
ports on PIC18F4X20 devices)

4. CCP and Enhanced CCP implementation
(PIC18F2X20 devices have 2 standard CCP
modules, PIC18F4X20 devices have one
standard CCP module and one ECCP module)

5. Parallel Slave Port (present only on
PIC18F4X20 devices)

All other features fo r device s in this family are identi cal.
These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and
Table 1-3.

TABLE 1-1: DEVICE FEATURES

Features PIC18F2220 PIC18F2320 PIC18F4220 PIC18F4320

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 4096 8192 4096 8192
Program Memory (Instruction s) 2048 4096 20 48 4096
Data Memory (Bytes) 512 512 512 512
Data EEPROM Memory (Bytes) 256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C (E) Ports A, B, C (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 2 2 1 1
Enhanced Capture/

Compare/PWM Modules
Serial Communications MSSP,

Parallel Communications (PSP) No No Yes Yes
10-bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Resets (and Delays) POR, BOR,

RESET Instruction,

MCLR

Programmable Low-Voltage
Detect

Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions 75 Instr uctions 75 Instructions 75 Instructions
Packages 28-pin SPDIP

0011

MSSP,

Addressable

USART

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

WDT

Yes Yes Yes Yes

28-pin SOIC

Addressable

USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

28-pin SPDIP

28-pin SOIC

MSSP,

Addressable

USART

POR, BOR,

RESET Instruction,

Stack Full,

Stac k U nde rflo w

(PWRT, OST),

(optional),

MCLR

WDT

40-pin PDIP

44-pin TQFP

44-pin QFN

MSSP,

Addressable

USART

POR, BOR,

RESET Instruction,

Stack Full,

Stac k U nde rflo w

(PWRT, OST),

(optional),

MCLR

WDT

40-pin PDIP

44-pin TQFP

44-pin QFN

DS39599C-page 8  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

FIGURE 1-1: PIC18F2220/2320 BLOCK DIAGRAM

Data Bus<8>

21

Address Latch

Program Memory

(4 Kbytes)

Data Latch

16

(3)

OSC1

(3)

OSC2

T1OSI

T1OSO

(2)

MCLR

VDD, VSS

21

Table Pointer <2>

21

inc/dec logic

Table Latch

8

Instruction

Decode &

Control

Internal

Oscillator

Block

INT RC

Oscillator

Low-Voltage

Programming

In-Circuit
Debugger

20

8

PCLATH

PCLATU

PCU

PCH PCL

Program Counter

31 Level Stack

ROM Latch

Instruction
Register

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Clock Monitor

8

8

8

4
BSR

Decode

BIT OP

Precision

Voltage

Reference

Data RAM
(512 Bytes)

Address Latch

Address<12>

12 4

FSR0
FSR1
FSR2

inc/dec

3

8

8

Data Latch

12

Bank0, F

logic

PRODLPRODH

8 x 8 Multiply

WREG

8

ALU<8>

8

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT

(2)

PORTB

12

PORTC

8

8

8

PORTE

RA5/AN4/SS
OSC2/CLKO/RA6
OSC1/CLKI/RA7

RB0/AN12/INT0
RB1/AN10/INT1

RB2/AN8/INT2
RB3/AN9/CCP2
RB4/AN11/KBI0
RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1/P1A

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RE3

(2)

/LVDIN/C2OUT

(3)

(3)

(1)

(1)

Timer0

(8- or 16-bit)

CCP1

Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCPMX2 configuration bit.

2: RE3 is available only when the MCLR
3: OSC1, OSC2, CLKI and CLKO are only ava ilable in select o scillator modes and when th ese pins are not being use d as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

Timer1
(16-bit)

CCP2

Timer2

(8-bit)

Master

Synchronous

Serial Port

Resets are disabled.

Timer3
(16-bit)

Addressable

USART

10-bit A/D
Converter

Data EEPROM

(256 Bytes)

 2003 Microchip Technology Inc. DS39599C-page 9

PIC18F2220/2320/4220/4320

FIGURE 1-2: PIC18F4220/4320 BLOCK DIAGRAM

Data Bus<8>

21

Address Latch

Program Memory

(8 Kbytes)

Data Latch

16

(3)

OSC1

(3)

OSC2

T1OSI

T1OSO

(2)

MCLR

DD, VSS

V

21

Table Pointer <2>

21

inc/dec logic

Table Latch

8

Instruction

Decode &

Control

Internal

Oscillator

Block

INT RC

Oscillator

Low-Voltage

Programming

In-Circuit
Debugger

20

8

PCLATU

PCLATH

PCU

PCH PCL

Program Counter

31 Level Stack

ROM Latch

Instruction
Register

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Clock Monitor

Data Latch

8

8

8

4
BSR

Decode

BIT OP

Precision

Voltage

Reference

Data RAM

(512 Bytes)

Address Latch

Address<12>

12 4

FSR0
FSR1
FSR2

inc/dec

3

WREG

8

8

(2)

12

Bank0, F

logic

PRODLPRODH

8 x 8 Multiply

8

ALU<8>

8

12

8

PORTA

PORTB

PORTC

PORTD

8

8

PORTE

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
OSC2/CLKO/RA6
OSC1/CLKI/RA7

RB0/AN12/INT0

RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC

RB7/KBI3/PGD

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1/P1A

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

RE0/AN5/RD
RE1/AN6/WR

RE2/AN7/CS
RE3

(2)

/LVDIN/C2OUT

(3)

(3)

(1)

(1)

Timer0

(8- or 16-bit)

Enhanced

CCP

Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCP2MX configuration bit.

2: RE3 is available only when the MCLR
3: OSC1, OSC2, CLKI and CL KO are only av ailable in se lect oscillator modes and when th ese pins a re not being us ed as digital I /O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

Timer1 Timer2
(16-bit) (8-bit)

Master

CCP2

Synchronous

Serial Por t

Resets are disabled.

Timer3
(16-bit)

Addressable

USART

10-bit A/D
Converter

Data EEPROM

(256 Bytes)

DS39599C-page 10  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

T ABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

PDIP SOIC

Pin

Type

Buffer

Type

Description

/VPP/RE3

MCLR

MCLR
VPP

RE3

OSC1/CLKI/RA7

OSC1
CLKI
RA7

OSC2/CLKO/RA6

OSC2
CLKO
RA6

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
VREF­CV

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI/C1OUT

RA4
T0CKI
C1OUT

RA5/AN4/SS

RA5
AN4
SS
LVDIN

C2OUT
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.

REF-/CVREF

REF

REF+

REF+

/LVDIN/C2O UT

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

2: Alternate assignment for CCP2 when CCP2MX is cleared.

11

99

10 10

22

33

44

55

66

77

I

ST

P

I

ST

I

ST

I

CMOS

I/O

TTL

O
O

I/O

I/OITTL

I/OITTL

I/O

O

I/O

I/O

O

I/O

O

I
I

I
I

I

I
I
I

DD)

—
—

TTL

Analog

Analog

TTL
Analog
Analog
Analog

TTL
Analog
Analog

ST/OD

ST

—

TTL
Analog

TTL
Analog

—

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low Reset
to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
Comparator Reference Voltage output.

Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.

Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.

Digital I/O.
Analog input 4.
SPI Slave Select input.
Low-Voltage Detect input.
Comparator 2 output.

 2003 Microchip Technology Inc. DS39599C-page 11

PIC18F2220/2320/4220/4320

TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/AN12/INT0

RB0
AN12
INT0

RB1/AN10/INT1

RB1
AN10
INT1

RB2/AN8/INT2

RB2
AN8
INT2

RB3/AN9/CCP2

RB3
AN9

(1)

CCP2

RB4/AN11/KBI0

RB4
AN11
KBI0

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 wh en CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number
PDIP SOIC

21 21

22 22

23 23

24 24

25 25

26 26

27 27

28 28

Pin

Type

I/O

I
I

I/O

I
I

I/O

I
I

I/O

I

I/O

I/O

I
I

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

DD)

Buffer

Type

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all i nputs.

Digital I/O.
Analog input 12.
External interrupt 0.

Digital I/O.
Analog input 10.
External interrupt 1.

Digital I/O.
Analog input 8.
External interrupt 2.

Digital I/O.
Analog input 9.
Capture2 input, Compare2 output, PWM2 output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
Low-voltage ICSP programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programmi ng cl ock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programmi ng data pin.

DS39599C-page 12  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

T ABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(2)

CCP2

RC2/CCP1/P1A

RC2
CCP1
P1A

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX

DT
RE3 — — — — See MCLR
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP SOIC

11 11

12 12

13 13

14 14

15 15

16 16

17 17

18 18

Pin

Buffer

Type

Type

I/O

O

I

I/O

I

CMOS

I/O

I/O
I/O

O

I/O
I/O
I/O

I/O

I

I/O

I/OOST

I/O

O

I/O

I/O

I

I/O

DD)

PORTC is a bidirectional I/O port.

ST

—

ST

ST
ST

ST
ST

—

ST
ST
ST

ST
ST
ST

—

ST

—

ST

ST
ST
ST

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
Enhanced CCP1 output.

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
SPI data in.

2

C data I/O.

I

Digital I/O.
SPI data out.

Digital I/O.
USART asynchronous transmit.
USART synchronous clock (see related RX/DT).

Digital I/O.
USART asynchronous receive.
USART synchronous data (see related TX/CK).

/VPP/RE3 pin.

Description

2

C mode.

 2003 Microchip Technology Inc. DS39599C-page 13

PIC18F2220/2320/4220/4320

TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

PDIP TQFP QFN

Pin

Type

Buffer

Type

Description

/VPP/RE3

MCLR

MCLR
VPP

RE3

OSC1/CLKI/RA7

OSC1
CLKI

RA7

OSC2/CLKO/RA6

OSC2
CLKO
RA6

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI/C1OUT

RA5/AN4/SS/LVDIN/
C2OUT

RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

Note 1: Default assignment for CCP2 wh en CCP2MX (CONFIG3H<0>) is set.

REF-/CVREF

RA2
AN2
V

REF-

CV

REF

REF+

RA3
AN3
V

REF+

RA4
T0CKI
C1OUT

RA5
AN4
SS
LVDIN
C2OUT

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

2: Alternate assignment for CCP2 when CCP2MX is cleared.

11818

13 30 32

14 31 33

21919

32020

42121

52222

62323

72424

I

P

I

I
I

CMOS

I/O

O
O

I/O

I/OITTL

Analog

I/OITTL

Analog

I/O

Analog

I

Analog

I

Analog

O

I/O

I

Analog

I

Analog

I/O

ST/OD

I

O

I/O

Analog

I
I

Analog

I

O

DD)

Master Clear (input) or programming voltage (input).

ST

ST

ST

TTL

—
—

TTL

TTL

TTL

ST

—

TTL
TTL

—

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage inpu t.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External cl ock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator reference voltage output.

Digital I/O.
Analog input 3.
A/D reference voltage (High) input.

Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.

Digital I/O.
Analog input 4.
SPI slave select input.
Low-Voltage Detect input.
Comparator 2 output.

DS39599C-page 14  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

T ABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/AN12/INT0

RB0

AN12

INT0
RB1/AN10/INT1

RB1

AN10

INT1
RB2/AN8/INT2

RB2

AN8

INT2
RB3/AN9/CCP2

RB3

AN9

(1)

CCP2
RB4/AN11/KBI0

RB4

AN11

KBI0
RB5/KBI1/PGM

RB5

KBI1

PGM
RB6/KBI2/PGC

RB6

KBI2

PGC
RB7/KBI3/PGD

RB7

KBI3

PGD
Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP TQFP QFN

33 8 9

34 9 10

35 10 11

36 11 12

37 14 14

38 15 15

39 16 16

40 17 17

Pin

Type

I/O

I
I

I/O

I
I

I/O

I
I

I/O

I

I/O

I/O

I
I

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

DD)

Buffer

Type

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.
Analog input 12.
External interrupt 0.

Digital I/O.
Analog input 10.
External interrupt 1.

Digital I/O.
Analog input 8.
External interrupt 2.

Digital I/O.
Analog input 9.
Capture2 input, Compare2 output, PWM2 output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
Low-voltage ICSP programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

 2003 Microchip Technology Inc. DS39599C-page 15

PIC18F2220/2320/4220/4320

TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(2)

CCP2

RC2/CCP1/P1A

RC2
CCP1
P1A

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 wh en CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP TQFP QFN

15 32 34

16 35 35

17 36 36

18 37 37

23 42 42

24 43 43

25 44 44

26 1 1

Pin

Type

I/O

O

I

I/O

I

I/O

I/O
I/O

O

I/O
I/O
I/O

I/O

I

I/O

I/OOST

I/O

O

I/O

I/O

I

I/O

DD)

Buffer

Type

ST

—

ST

ST

CMOS

ST

ST
ST

—

ST
ST
ST

ST
ST
ST

—

ST

—

ST

ST
ST
ST

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
Enhanced CCP1 output.

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchron ous serial clock input/o utput for I

Digital I/O.
SPI data in.

2

C data I/O.

I

Digital I/O.
SPI data out.

Digital I/O.
USART asynchronous trans m it.
USART synchronous clock (see related RX/DT).

Digital I/O.
USART asynchronous receive.
USART synchronous data (see related TX/CK).

2

C mode.

DS39599C-page 16  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

T ABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/PSP0

RD0

PSP0
RD1/PSP1

RD1

PSP1
RD2/PSP2

RD2

PSP2
RD3/PSP3

RD3

PSP3
RD4/PSP4

RD4

PSP4
RD5/PSP5/P1B

RD5

PSP5

P1B
RD6/PSP6/P1C

RD6

PSP6

P1C
RD7/PSP7/P1D

RD7

PSP7

P1D
Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP TQFP QFN

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Pin

Buffer

Type

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/O

O

I/O
I/O

O

I/O
I/O

O

DD)

Type

PORTD is a bidirectional I/O port or a Parallel Slave Port
(PSP) for interfacing to a microprocessor port. These pins
have TTL input buffers when PSP module is enabled.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

ST

TTL

—

ST

TTL

—

ST

TTL

—

Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.

Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.

Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.

Description

 2003 Microchip Technology Inc. DS39599C-page 17

PIC18F2220/2320/4220/4320

TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/AN5/RD

RE0
AN5
RD

RE1/AN6/WR

RE1
AN6
WR

RE2/AN7/CS

RE2
AN7
CS

RE3 1 18 18 — — See MCLR

SS 12,

V

DD 11, 32 7, 28 7, 8,

V

NC — — 13 NC NC No connect.
Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 wh en CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP TQFP QFN

82525

92626

10 27 27

6, 29 6, 30, 31P — Ground reference for logic and I/O pins.

31

28, 29

Pin

Buffer

Type

DD)

Type

PORTE is a bidirectional I/O port.

I/O

I/O

I/O

ST

I

Analog

I

TTL

ST

I

Analog

I

TTL

ST

I

Analog

I

TTL

P — Positive supply for logic and I/O pins.

Digital I/O.
Analog input 5.
Read control for Parallel Slave Port
(see also WR

Digital I/O.
Analog input 6.
Write control for Parallel Slave Port
(see CS

Digital I/O.
Analog input 7.
Chip select control for Parallel Slave Port
(see related RD

and RD pins).

/VPP/RE3 pin.

Description

and CS pins).

and WR).

DS39599C-page 18  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

The PIC18F2X20 and PIC18F4X20 devices can be
operated in ten dif ferent osci llator modes . The user can
program the configuration bits, FOSC3:FOSC0, in
Configuration Register 1H to select one of these ten
modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL enabled

5. RC External Resistor/Cap ac ito r with

OSC/4 output on RA6

F

6. RCIO External Resistor/Capacito r with

I/O on RA6

7. INTIO1 Internal Oscillator with F

output on RA6 and I/O on RA7

8. INTIO2 Internal O scil lat or with I/O on RA6

and RA7

9. EC External Clock with F

10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.

The oscillator design requires the use of a parallel cut
crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturers
specifications.

OSC/4

OSC/4 output

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)

(1)

C1

(1)

C2

Note 1: See Table 2-1 and Table 2-2 for initial values

2: A series resistor (R

3: R

OSC1

To

Internal

XTAL

(2)

RS

OSC2

of C1 and C2.

strip cut crystals.

F varies with the oscillator mode chosen.

(3)

RF

PIC18FXXXX

S) may be required for AT

Logic

Sleep

T ABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz
Capacitor values are for design guidance only.
These capacitors were tested with the resonators

listed below for basic start-up and operation. These
values are not optimized.

Different cap acitor values may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes on page 20 for additional information.

Resonators Used:

455 kHz 4.0 MHz

2.0 MHz 8.0 MHz

16.0 MHz

56 pF
47 pF
33 pF

27 pF
22 pF

56 pF
47 pF
33 pF

27 pF
22 pF

 2003 Microchip Technology Inc. DS39599C-page 19

PIC18F2220/2320/4220/4320

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc T y pe

Crystal

Freq

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF

4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed

below for basic start-up and op erat ion . These values

are not optimized.

Different capa citor values may be required to produc e
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes following this table for additional

information.

32 kHz 4 MHz

200 kHz 8 MHz

1 MHz 20 MHz

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the
start-up time.

2: When operating below 3V V

using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

S may be required to avoid overdriving

4: R

crystals with low driv e lev e l spe ci fic ati on.

5: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

T ypical Cap acitor V alues

Tested:

C1 C2

Crystals Used:

DD, or when

An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS OSC
CONFIGURATION)

Clock from
Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.3 HSPLL

A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
crystal oscillator circuit, or to clock the device up to its
highest rated frequency from a crystal oscillator. This
may be useful for customers who are concerned with
EMI due to high-frequency crystals.

The HSPLL mode make s use of the HS mode osc illator
for frequencies up t o 10 MHz. A PLL then multipl ies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.

The PLL is enabled only when the oscillator configura­tion bits are programmed for HSPLL mode. If
programmed for any other mode, the PLL is not
enabled.

FIGURE 2-3: PLL BLOCK DIAGRAM

HS Osc Enable

PLL Enable

(from Configuration Register 1H)

OSC2

OSC1

HS Mode

Crystal

Osc

IN

F
FOUT

÷4

Phase

Comparator

Loop
Filter

VCO

SYSCLK

MUX

DS39599C-page 20  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

2.4 External Clock Input

The EC and ECIO Oscillator mode s require an externa l
clock source to be conn ected to the OSC1 pi n. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK INPUT

OPERATION
(EC CONFIGURATION)

Clock from
Ext. System

OSC/4

F

The ECIO Oscillator mode func ti ons li ke t he EC m od e,
except that the OSC2 pin becomes an additional gen­eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK INPUT

Clock from
Ext. System

RA6

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

OPERATION
(ECIO CONFIGURATION)

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

2.5 RC Oscillator

For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from uni t to unit due to
normal manufacturing variation. Furthermore, the dif­ference in lead frame capacitance between package
types will also affect the oscillation frequency, espe­cially for low C

EXT values. The user also needs to take

into account variation due to tolerance of external R
and C components used. Figure 2-6 shows how the
R/C combination is connected.

In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic.

FIGURE 2-6: RC OSCILLATOR MODE

VDD

REXT

CEXT

VSS

F

OSC/4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

The RCIO Oscillator mode (Figure 2-7) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).

EXT) and capacitor (CEXT) val-

OSC1

Internal

Clock

PIC18FXXXX

OSC2/CLKO

EXT > 20 pF

C

FIGURE 2-7: RCIO OSCILLATOR MODE

VDD

REXT

OSC1

CEXT

VSS

RA6

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

 2003 Microchip Technology Inc. DS39599C-page 21

I/O (OSC2)

C

EXT > 20 pF

Internal

Clock

PIC18FXXXX

PIC18F2220/2320/4220/4320

2.6 Internal Oscillator Block

The PIC18F2X20/4X20 devices include an internal
oscillator block wh ich generat es two dif ferent cl ock sig­nals. Either can be used as the system’s clock source.
This can eliminate the need for external oscillator
circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the system clock. It
also drives a postscaler which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator
(INTRC) which provides a 31 kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source or when any of the
following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Spe ed Start-up
These features are discussed in greater detail in

Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC

direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 26).

2.6.1 INTIO MODES

Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pin s
which can then be used for digital I/O. Two distinct
configurations are available:

• In INTIO1 mode, the OSC2 pin outputs F
while OSC1 functions as RA 7 fo r dig it a l in put a nd
output.

• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.

OSC/4,

2.6.2 INTRC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
This changes the frequency of the INTRC source from
its nominal 31.25 kHz. Peripherals and features that
depend on the INTRC source will be affected by this
shift in frequency.

Once set during factory calibration, the INTRC
frequency will remain within ±1% as temperature and

DD change across their full specified operating

V
ranges.

2.6.3 OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at
the factory but c an be adjusted in the user's ap plication.
This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.

When the OSCTUNE regis ter is mo di fied , the IN T O SC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new fre­quency within 8clock cycles (approximately
8*32µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code execution conti nues du ring th is shift.
There is no indicati on that th e shift ha s occurre d. Oper­ation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in frequency.

DS39599C-page 22  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits

011111 = Maximum frequency (+12.5%, approximately)

• •

• •

000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111

• •

• •
100000 = Minimum frequency (-12.5%, approximately)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS39599C-page 23

PIC18F2220/2320/4220/4320

2.7 Clock Sources and Oscillator

Switching

Like previous PIC18 devices, the PIC18F2X20 and
PIC18F4X20 devices include a feature that allows the
system clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
PIC18F2X20/4X20 devices offer two alternate clock
sources. When enabled, these give additional options
for switching to the various power managed operating
modes.

Essentially, there are three clock sources for these
devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the E xternal Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mod e is defined on POR by the content s
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.

The s econdary oscillat ors are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.

PIC18F2X20/4X20 devices offer only the Timer1
oscillator as a seco ndary oscilla tor . This oscil lator , in all
power managed modes, is often the time base for
functions such as a real-time clock.

Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/ T1CKI and RC1 /T1OSI pins.
Like the LP mode oscillator circuit, loading capacitors
are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in
Section 12.2 “Timer1 Oscillator”.

In addition to being a p rimary clock source, the internal
oscillator block is available as a power managed
mode clock source. The INTRC source is a lso us ed as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2X20/4X20 devices
are shown in Figure 2-8. See Section 12.0 “Timer1

Module” for further details of th e Timer1 os cillator . See
Section 23.1 “Configuration Bits” for Configuration

register details.

2.7.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power managed modes.

The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating
in power managed modes. The ava ilable c lock sou rces
are the primary clock (defined in Configuration
Register 1H), the secondary clock (Timer1 oscillator)
and the internal oscillator block. The clock selection
has no effect until a SLEEP instruction is executed and
the device enters a power managed mode of opera tion.
The SCS bits are cleared on all forms of Reset.

The Internal Oscill ator Select bit s, IRCF2:IRCF0, select
the frequency output of the interna l oscill ator block th at
is used to dr ive t he sys tem clo ck. Th e choi ces are t he
INTRC source, the INTOSC source (8 MHz) or one of
the six frequencies derived from the INTOSC
postscaler (125kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of thes e bits w ill ha ve an immedi ate cha nge on
the internal oscillator’s output.

The OSTS, IOFS and T1RUN bits ind icate wh ich cl oc k
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer has
timed out and the prima ry clock is providin g the system
clock in pri mary clock mode s. The IOFS b it indicates
when the internal oscillator block has stabilized and is
providing the system clock in RC Clock modes. The
T1RUN bit (T1CON<6>) indicates when the Timer1
oscillator is providing the system clock in secondary
clock modes. If none of th ese bit s are set, th e INTRC is
providing the system clock, or the internal oscillator
block has just started and is not yet stable.

The IDLEN bit controls the selective shutdown of the
controller’s CPU in power managed mo des. The use of
these bits is discussed in more detail in Section 3.0

“Power Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The
Timer1 osc illator is enabled by s etting the
T1OSCEN bit in th e T imer1 C ontrol re gis­ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any atte mpt to set the
SCS0 bit will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before
executing the SLEEP instr u ct ion or a very
long delay may occur while the Timer1
oscillator starts.

DS39599C-page 24  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

FIGURE 2-8: PIC18F2X20/4X20 CLOCK DIAGRAM

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

Secondary Oscillator

T1OSCEN
Enable
Oscillator

OSCCON<6:4>

Internal

Oscillator

Block

INTRC

Source

8 MHz

(INTOSC)

PIC18F2X20/4X20

4 x PLL

OSCCON<6:4>

8 MHz

111

4 MHz

110

2 MHz

101

1 MHz

31 kHz

100

011

010

001

000

Postscaler

500 kHz
250 kHz
125 kHz

CONFIG1H<3:0>

HSPLL

LP, XT, HS, RC, EC

Clock Source Option
for Other Modules

Internal Oscillator

MUX

T1OSC

Clock

Control

MUX

OSCCON<1:0>

Peripherals

CPU

IDLEN

WDT, FSCM

 2003 Microchip Technology Inc. DS39599C-page 25

PIC18F2220/2320/4220/4320

REGISTER 2-2: OSCCON REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

bit 7 IDLEN: Idle Enable bit

1 = Idle mode enabled; CPU core is not clocked in power managed modes
0 = Run mode enabled; CPU core is clocked in power managed modes

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (INTRC source drives clock directly)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Oscillator start-up time-out timer has expired; primary oscillator is running
0 = Oscillator start-up time-out timer is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits

1x = Internal oscillator block (RC modes)
01 = Timer1 oscillator (Secondary modes)
00 = Primary oscillator (Sleep and PRI_IDLE modes)

Note 1: Depends on state of IESO bit in Configuration Register 1H.

2: SCS0 may not be set while T1OSCEN (T1CON<3>) is clear.

(1)

(2)

(1)

R-0 R/W-0 R/W-0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39599C-page 26  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

2.7.2 OSCIL LAT OR TRANSITIONS

The PIC18F2X20/4X20 de vices contain ci rcuitry to pre­vent clocking “glitches” when switching between clock
sources. A short p aus e in the sy stem c lock o ccurs dur­ing the clock switch. The length of this pause is
between 8 and 9 clock pe riods of the n ew clock sourc e.
This ensures that the new clock source is stable and
that its pulse width will not be less than the shortest
pulse width of the two clock sources.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power Managed Modes”.

2.8 Effects of Power Managed Modes on the Various Clock Sources

When the device executes a SLEEP instruction, the
system is switched to one of the power managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power Managed Modes” for details.

When PRI_IDLE mode is selected, the designated pri­mary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the o scillat or) will sto p oscillat ing.

In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is op erat ing an d p ro­viding the s ystem clo ck. The T ime r1 osci llator m ay als o
run in all power managed modes if required to clock
Timer1 or Timer3.

In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power managed mode (see Section 23.2 “Watchdog

Timer (WDT)” through Section 23.4 “Fail-Safe Clock
Monitor”). The INTOSC output at 8 MHz may be used

directly to clock the system or may be divided down
first. The INTOSC out put is disabled if the sy stem clock
is provided directly from the INTRC output.

If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).

Enabling any on-chip feature that will operate during
Sleep will increase the current co nsumed duri ng Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a real­time clock. Ot her features may be operating that do n ot
require a system clock source (i.e., SSP slave, PSP,
INTn pins, A/D conversions and others).

2.9 Power-up Delays

Power-up delays are c ontrolled by two ti mers so that no
external Reset circuitry is required for most applica­tions. The delays ensure that the device is kept in
Reset until the device powe r supply i s stable under nor­mal circumstan ces and the pri mary clock is ope rating
and stable. For additional information on power-up
delays, see Section 4.1 “Power-on Reset (POR)”
through Section 4.5 “Brown-out Reset (BOR)”.

The first timer is the Power-up Timer (PWRT) which
provides a fixed delay on power-up (parameter 33,
Table 26-10), if enabled, in Configuration Register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Rese t until the crys­tal oscillator is stable (LP, XT and HS modes). The OST
does this by counting 1024 oscillator cycles before
allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, the
device is kept in Res et for an add iti onal 2ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequ enc y.

There is a delay of 5 to 10 µs, following POR, while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the only del ay that occurs when any o f the EC ,
RC or INTIO modes are used as the primary clock
source.

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC Mode OSC1 Pin OSC2 Pin

RC, INTIO1 Floating, external resistor

should pull high

RCIO, INTIO2 Floating, external resistor

should pull high
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT, and HS Feedback inverter disabled at

quiescent voltage level

Note: See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR

 2003 Microchip Technology Inc. DS39599C-page 27

At logic low (clock/4 output)

Configured as PORTA, bit 6

Feedback inverter disabled at
quiescent voltage level

Reset.

PIC18F2220/2320/4220/4320

NOTES:

DS39599C-page 28  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

3.0 POWER MANAGED MODES

The PIC18F2X20 and PIC18F4X20 devices offer a total
of six operating modes for more efficient power
management (see Table 3-1). These operating modes
provide a variety of options for selective power
conservation in applications where resources may be
limited (i.e., battery-powered devices).

There are three categories of power managed modes:

• Sleep mode

• Idle modes

• Run modes
These categories define which portions of the device

are clocked and some times , what sp eed. The R un and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.

The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator) and the Sleep mode offered by all
PICmicro
stopped) are both offered in the PIC18F2X20/4X20
devices (SEC_RUN and Sleep modes, respectively).
However, additional power managed modes are avail­able that allow the u ser greater flexibili ty in dete rmining
what portions of the device are operating. The power
managed modes are event driven; that is, some
specific event must occur for the device to enter or
(more particularly) exit these operating modes.

®

devices (where all system clocks are

For PIC18F2X20/4X20 devices, the power managed
modes are invoked by using the existing SLEEP
instruction. All modes exit to PRI_RUN mode when trig­gered by an interrupt, a Reset, or a WDT time-out
(PRI_RUN mode is the normal full power execution
mode; the CPU and peri phe rals are cl ock ed by the p ri­mary oscillator source). In addition, power managed
Run modes may also exit to Sleep mode or their
corresponding Idle mode.

3.1 Selecting Power Managed Modes

Selecting a power managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit co ntro ls CPU c lo ck ing whil e th e
SC1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.

3.1.1 CLOCK SOURCES

The clock source is selected by setting the SCS bits of
the OSCCON register. Three clock sources are avail­able for use in power manag ed Idle modes: th e primary
clock (as configured in Configuration Register 1H), the
secondary clock (Timer1 oscillator) and the internal
oscillator block. The secondary and internal oscillator
block sources are available for the power managed
modes (PRI_RUN mode is the normal full power exe­cution mode; the CPU and peripherals are clocked by
the primary oscillator source).

TABLE 3-1: POWER MANAGED MODES

OSCCON Bits Module Clocking

Mode

Sleep 000 Off Off
PRI_RUN 000Clocked Clocked

SEC_RUN 001Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN 01xClocked Clocked Internal Oscillator Block
PRI_IDLE 100 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 101 Off Clocked Secondary – Timer1 Oscilla tor
RC_IDLE 11x Off Clocked Internal Oscillator Block

Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

IDLEN

<7>

SCS1:SCS0

<1:0>

CPU Peripherals

Available Clock and Oscillator Source

None – All clocks are disabled
Primary – LP, XT, HS, HSPLL, RC, EC, INTR C

This is the normal full power execution mode.

(1)

(1)

(1)

.

 2003 Microchip Technology Inc. DS39599C-page 29

PIC18F2220/2320/4220/4320

3.1.2 ENTERING POWER MANAGED MODES

In general, entry, exit and switching between power
managed clock sources requires clock source
switching. In each case, the sequence of events is the
same.

Any change in the power managed mode begins with
loading the OSCCON register and executing a SLEEP
instruction. The SCS1:SCS0 bits select one of three
power managed clock sources; the primary clock (as
defined in Configuration R egister 1H), the s econdary
clock (the Timer1 os cillator) and the inte rnal osci llator
block (used i n RC mode s). Mo dif ying the SCS bits wi ll
have no effec t until a SLEEP instruction is executed.
Entry to the power managed mode is triggered by the
execution of a SLEEP instruction.

Figure 3-5 shows how the system is clocked while
switching from the primary clock to the Timer1 oscilla­tor. When the SLEEP instruction is executed, clocks to
the device are stopped at the beginning of the next
instruction cycle. Eight clock cycles from the new clock
source are counted to synchronize with the new clock
source. After eight clock pulses from the new clock
source are counted, clocks from the new clock source
resume clocking the system. The actual length of the
pause is betwe en eight and nine cl ock periods from the
new clock source. This ensures that the new clock
source is stab le a nd th at its pulse wid th wil l not be less
than the shortest pulse width of the two clock sources.

Three bits in dicat e the current cloc k so urce: OSTS an d
IOFS in the OSCCON register and T1RUN in the
T1CON register. Only one o f these bit s will be se t while
in a power managed mode othe r than PRI_RUN. Whe n
the OSTS bit is set, the primary clock is providing the
system clock. When the IOFS bit is set, the INTOSC
output is providing a stable 8MHz clock source and is
providing the sy stem cl ock. When the T1R UN bit is set,
the Timer1 oscillator is providing the system clock. If
none of these bits are set, then either the INTRC clock
source is cloc ki ng t he sy ste m or the INTOSC sourc e i s
not yet stable.

If the internal oscillator block is configured as the pri­mary clock source in Configuration Register 1H, then
both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering a power managed RC mode
(same frequency) would clear the OSTS bit.

Note 1: Caution should be used when m odifying a

single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep
mode; executing a SLEEP instruction is
simply a trigger to place th e controller in to
a power managed mode selected by the
OSCCON register, one of which is Sleep
mode.

DD is less than 3V, it is

3.1.3 MULTIPLE SLEEP COMMANDS

The power managed mode that is invoked with the
SLEEP instruction is determined by the settings of the
IDLEN and SCS bits at the time the instruction is exe­cuted. If another SLEEP instruction is executed, the
device will enter the power manag ed mode spe cified by
these same bits at that time. If the bits have changed,
the device will enter the new power managed mode
specified by the new bit settings.

3.1.4 COMPARISONS BETWEEN RUN AND IDLE MODES

Clock source selection for the Run modes is identical to
the corresponding Idle modes. When a SLEEP instruc­tion is executed, the SCS bits in the OSCCON register
are used to switch to a different clock source. As a
result, if there is a ch ange of clock sour ce at th e ti me a
SLEEP instruction is ex ecuted, a clock swi tch will occur .

In Idle modes, the CPU is not clocked and is not run­ning. In Run mode s, the CPU is clocked and executin g
code. This difference modifies the operation of the
WDT when it times out. I n Id le modes, a WDT time-o ut
results in a wake from power managed modes. In Run
modes, a WDT time-out results in a WDT Reset (see
Table 3-2).

During a wake-up from an Idle mode, the CPU starts
executing code by entering the corresponding Run
mode until the primary clock becomes ready. When the
primary clock becomes ready, the clock source is auto­matically switched to the primary clock. The IDLEN and
SCS bits are unchanged during and after the wake-up.

Figure 3-2 shows how the system is clocked dur ing the
clock source switch. The example assumes the device
was in SEC_IDLE or SEC_RUN mode when a wake is
triggered (the primary clock was configured in HSPLL
mode).

DS39599C-page 30  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

TABLE 3-2: COMPARISON BETWEEN POWER MANAGED MODES

Power

Managed

Mode

Sleep Not clocked (not running) Wake-up Not clocked None or INTOSC multiplexer if

Any Idle mode Not clocked (not running) Wake-up Primary, Secondary or

Any Run mode Secondary or INTOSC

CPU is clocked by ...

multiplexer

WDT time-out

causes a ...

Reset Secondary or INTO SC

Peripherals are

clocked by ...

INTOSC multiplexer

multiplexer

Clock during wake-up

(while primary becomes

ready)

Two-Speed Start-up or
Fail-Safe Clock Monitor are
enabled.

Unchanged from Idle mode
(CPU operates as in
corresponding Run mode).

Unchanged from Run mode.

3.2 Sleep Mode

The power managed Sleep mode in the PIC18F2X20/
4X20 devices is identical to that offered in all other
PICmicro controllers. It is entered by clearing the
IDLEN and SCS1:SCS0 bits (this is the Reset state)
and executing the SLEEP instruction. This s huts down
the primary oscillator and the OSTS bit is cleared (see
Figure 3-1).

When a wake ev ent occurs i n Sleep mo de (by int errupt,
Reset or WDT time-out), th e system w ill not be cloc ked
until the primary clock source becomes ready (see
Figure 3-2), or it will be clocked from the internal
oscillator block if either the Two-Speed Start-up or the
Fail-Safe Clock Monitor are enabl ed (see Section 23.0
“Special Features of the CPU”). In either case, the
OSTS bit is set whe n t he primary clock is providing the
system clocks. The IDLEN and SCS bits are not
affected by the wake-u p.

3.3 Idle Modes

The IDLEN bit allows the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Clearing ID LEN allows t he CPU to be cl ocked.
Setting IDLEN disables clocks to the CPU, effectively
stopping program execution (see Register 2-2). The
peripherals continue to be clocked regardless of the
setting of the IDLEN bit.

There is one exception to ho w the IDLEN bit functions.
When all the low-power OSCCON bits are cleared
(IDLEN:SCS1:SCS0 = 000), the device enters Sleep
mode upon the execu tion of the SLEEP instruction. This
is both the Reset state of the OSCCON register and the
setting that selects Sleep mode. This maintains com­patibility with other PICmicro devices that do not offer
power managed modes.

If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a
‘1’ when a SLEEP instruction is executed, the
peripherals will be clocked from the clock source
selected using the SCS1 :SCS0 bits ; however, the CPU
will not be clocked. Since the CPU is not executing
instructions, the only exits from any of the Idle modes
are by interrupt, WDT time-out or a Reset.

When a wake-up event occurs, CPU execution is
delayed approxim ately 10µs while it becomes ready to
execute code. When the CPU begins executing code,
it is clocked by the same clock source as was selected
in the power managed mode (i.e., when waking from
RC_IDLE mode, the internal oscillator block will clock
the CPU and peripherals unti l the primar y clock so urce
becomes ready – this is essentially RC_RUN mode).
This continues until the primary clock source becomes
ready. When the primary clock becomes ready, the
OSTS bit is set and the system clock source is
switched to the primary clock (see Figure 3-4). The
IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep m ode, a WDT time-out
will result in a W DT wak e-up t o full power op erat ion.

 2003 Microchip Technology Inc. DS39599C-page 31

PIC18F2220/2320/4220/4320

FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE

Q4Q3Q2

Q1Q1

OSC1

CPU
Clock

Peripheral
Clock

Sleep
Program

Counter

FIGURE 3-2: TRANSITION TI MING FOR WAKE FROM SLEEP (HSPLL)

PC + 2PC

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Note 1: T

Q1 Q2 Q3 Q4 Q1 Q2

(1)

TOST

PC

Wake-up Event

OST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

(1)

TPLL

OSTS bit Se t

PC + 2

Q3 Q4 Q1 Q2

PC + 4

Q3 Q4

PC + 6

Q1 Q2 Q3 Q4

PC + 8

DS39599C-page 32  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

3.3.1 PRI_IDLE MODE

This mode is unique among the three Low-Power Idle
modes in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation, with its
more accurate primary clock source, since the clock
source does not have to “warm up” or transition from
another oscillator.

When a wake-up event occurs, the CPU is clocked
from the primary clock source. A delay of approxi­mately 10 µs is required between the wake-up event
and when code execution starts. This is required to
allow the CPU to bec ome ready to exec ute instructions.
After the wake-up, the OSTS bit remains set. The
IDLEN and SCS bits are not affected by the wak e-up
(see Figure 3-4).

PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEP instruc­tion. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).

FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE

Q1

Q4

Q3

OSC1

CPU Clock

Q1

Q2

Peripheral

Clock

Program

Counter

PC PC + 2

FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

Q1 Q3 Q4

CPU Start-up Delay

PC

Wake-up Event

Q2

PC + 2

 2003 Microchip Technology Inc. DS39599C-page 33

PIC18F2220/2320/4220/4320

3.3.2 SEC_ID LE MO DE

In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the IDLEN
bit, modifying to SCS1:SCS0 = 01 and executing a
SLEEP instruction. When the clock source is switched
to the Timer1 oscillator (see Figure 3-5), the primary
oscillator is shut down, th e OSTS bit is cleared and the
T1RUN bit is set.

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mod e.

When a wake-up event occurs, the peripherals continue
to be clocked from th e Timer1 oscillator. After a 10 µs
delay following the wake-up event, the CPU begins exe­cuting code, being clocked by the Timer1 oscillator. The
microcontroller operates in SE C_RUN mode until the
primary clock becomes ready. When the primary clock
becomes ready, a clock switch back to the primary clock
occurs (see Figure 3-6). When the clock switch is com­plete, the T1RUN bit is cleared , the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wa ke-up;
the Timer1 oscillator continues to run.

If the T1OSCEN bit is not set when try­ing to set the SCS0 bit (OSCCON<0>),
the write to SCS0 will not occur. If the

Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the os cill at or ha s start ed; in su ch si t­uations, initial oscillator operation is far
from stable and unpredictable operation
may result.

FIGURE 3-5: TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE

Q4Q3Q2

Q1

Q1

T1OSI
OSC1

CPU
Clock

Peripheral
Clock

Program
Counter

12345678

Clock Transition

PC + 2PC

FIGURE 3-6: TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)

Q2

Q3 Q4

T1OSI

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Q1

PC PC + 2

TOST

Q2

(1)

Q3

TPLL

Q1

Q4

(1)

12345678

Clock Transition

PC + 4

Q1

PC + 6

Q2

Q3

Wake-up from Interrupt Event

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

DS39599C-page 34  2003 Microchip Technology Inc.

OSTS bit Set

PIC18F2220/2320/4220/4320

3.3.3 RC_IDLE MODE

In RC_IDLE mode, t he C PU is d isabled but the periph­erals continue to b e c loc ke d fro m t he internal oscilla tor
block using the INTOSC multiplexer. This mode allows
for controllable power cons ervation during Idl e periods .

This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before exec uti ng th e SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.

If the IRCF bits are set to a non-zero value (thus
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
INTOSC source stabilizes. If the IRCF bits were previ-

was executed and the INTOSC source was already
stable, the IOFS bit will remain set. If the IRCF bits are
all clear, the INTOSC output is not enabled and the
IOFS bit will remain clear; there will be no indication of
the current cl ock source.

When a wake-up event occurs, the peripherals con­tinue to be clocked from the INTOSC multiplexer. After
a 10 µs delay following the wake-up event, the CPU
begins executing code, being clocked by the INTOSC
multiplexer. The microcontroller operates in RC_RUN
mode until the primar y clock bec omes read y. When the
primary cloc k becomes ready, a clock switc h back to
the primary clock occurs (see Figure 3-8). When the
clock switch is complete, the IOFS bit is cleared, the
OSTS bit is set and the primary clock is providing the
system clock. The I DLEN and SCS bi ts are not a ffected
by the wake-up. The INT RC sour ce will c ontinu e to run
if either the WDT or the Fail-Safe Clock Monitor is
enabled.

ously at a non-zero value before the SLEEP instruction

FIGURE 3-7: TIMING TRANSITION TO RC_IDLE MODE

Q4Q3Q2

Q1

INTRC
OSC1

Q1

12345678

Clock Transition

CPU
Clock

Peripheral
Clock

Program
Counter

PC + 2PC

FIGURE 3-8: TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)

Q3 Q4

Q1

Q1

Q2

Q3

TPLL

OSTS bit Set

Q4

INTOSC

Multiplexer

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Wake-up from Interrupt Event

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

PC PC + 2

Q1

TOST

(1)

Q4

(1)

12345678

Clock Transition

PC + 4

Q2

Q2

PC + 6

Q3

 2003 Microchip Technology Inc. DS39599C-page 35

PIC18F2220/2320/4220/4320

3.4 Run Modes

If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While these operating mo des may not aff ord the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
greater than the primary clock.

Wake-up from a power managed Run mode can be
triggered by an interrupt, or any Reset, to return to full
power operation. As the CPU i s exec uti ng c od e in Ru n
modes, several additional exits from Run modes are
possible. They inclu de exit to Sleep m ode, exit to a cor­respondin g Idl e mode , and ex it by exec uting a RESET
instruction. While the device is in any of the power
managed Run modes, a WDT time-out will result in a
WDT Reset.

3.4.1 PRI_RUN MODE

The PRI_RUN mode is the normal full power execution
mode. If the SLEEP instruction is never executed, the
microcontroller opera tes in this m ode (a SLEEP instruc­tion is executed to enter all other power managed
modes). All other power managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.

There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section2.7.1
“Oscillator Control Register”).

3.4.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the T imer1 osci llator. This gives users the
option of lower power c onsumption w hile still using a
high accuracy clock source.

SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01 and executing a SLEEP
instruction. The system clo ck source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscilla­tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.

Note: The Timer1 oscillator should already be

running prior to entering SEC_RU N mode.

If the T1OSCEN bit is not set when try­ing to set the SCS0 bit, the write to
SCS0 will not occur. If t he Timer1 oscilla-

tor is enabled, but not ye t run nin g, s ys tem
clocks will be delayed until the oscillator
has started; in such sit uation s, initi al osci l­lator operation is far from stable and
unpredictable operation may result.

When a wake-up event occurs, the peripherals and
CPU continue to be c locked fro m the Timer1 oscilla tor
while the primary clock is started. When the primary
clock becomes ready, a clock switch back to the primary
clock occurs (see Figure 3-6). When the clock switch is
complete, the T1RUN bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wa ke-up;
the Timer1 oscillator continues to run.

Firmware can force an exit from SE C_RUN mode. By
clearing the T1OSC EN bit (T1CON<3>), an exit from
SEC_RUN back to normal full po wer operation is trig­gered. The Timer1 oscillator will continue to run and
provide the system clock even though the T1OSCEN bit
is cleared. The prim ary clock is started. When the pri­mary clock becomes ready, a clock switch back to the
primary clock occurs (see Figure 3-6). When the clock
switch is complete, the Timer1 oscillator is disabled, the
T1RUN bit is cleared, t he OSTS bit is set and the pri­mary clock is providing the system clock. The IDLEN
and SCS bits are not affected by the wake-up.

FIGURE 3-9: TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE

Q4Q3Q2

Q1

T1OSI
OSC1

CPU
Clock

Peripheral
Clock

Program
Counter

DS39599C-page 36  2003 Microchip Technology Inc.

Q1

12345678

Clock Transition

PC + 2PC

Q2

Q4Q3

Q1

Q2

Q3

PC + 2

PIC18F2220/2320/4220/4320

3.4.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode pro­vides the best power con servation of all the Run mode s
while still ex ecuting code. I t works well for use r applic a­tions which are not highly timing sensitive or do not
require high-speed clocks at all times.

If the primary clock source is the internal oscillator
block (either of the INTIO1 or INTIO2 os cillator s), there
are no distinguishable differences between PRI_RUN
and RC_RUN modes during execution. However, a
clock switch delay will occur during entry to, and exit
from, RC_RUN mode. Therefore, if the primary clock
source is the internal oscillator block, the use of
RC_RUN mode is not recommended.

This mode is ente red by c lea rin g th e IDLEN b it, se ttin g
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The IRCF bits may select the clock
frequency before the SLEEP instruction is executed.
When the clock source is switched to the INTOSC
multiplexer (see Figure 3-10), the primary oscillator is
shut down and the OSTS bit is cleared.

The IRCF bits may be modified at any time to immedi­ately change the system clock speed. Executing a
SLEEP instruction is not required to select a new clock
frequency from the INTOSC multiplexer.

Note: Cautio n s hou ld be u se d w he n m odi fy ing a

single IRCF bit. If V

DD is less than 3V, it is

possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.

If the IRCF bits are all clear, the INTOSC output is not
enabled and the IOFS bit wi ll remain clear; there will be
no indication of the current clock source. The INTRC
source is providing the system clocks.

If the IRCF bits are changed from all clear (thus
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC out put becom es stab le. Clocks to
the system continue while the INTOSC source
stabilizes in approximately 1ms.

If the IRCF bits were previously at a non-zero value
before the SLEEP instruction was executed and the
INTOSC source was already stable, the IOFS bit will
remain set.

When a wake-up event occurs , the system continues to
be clocked from the INTOSC multiplexer while the pri­mary clock is st arted. When t he primary cl ock become s
ready, a clock switch to the primary clock occurs (see
Figure 3-8). When the clock switch is complete, the
IOFS bit is cleared, the O STS bit is se t and the prim ary
clock is providing the system clock. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enab led .

FIGURE 3-10: TIMING TRANSITION TO RC_RUN MODE

Q3Q2Q1

Q4

12345678

Clock Transition

PC + 2PC

INTRC
OSC1

CPU
Clock

Peripheral
Clock

Program
Counter

Q4

Q3Q2Q1 Q4 Q2Q1 Q3

PC + 4

 2003 Microchip Technology Inc. DS39599C-page 37

PIC18F2220/2320/4220/4320

3.4.4 EXIT TO IDLE MODE

An exit from a power managed Run mode to its corre­sponding Idle mode is executed by setting the IDLEN
bit and executing a SLEEP instruction. The CPU is
halted at the beginning of the instruction following the
SLEEP instruction. There are no changes to any of the
clock source status bits (OSTS, IOFS or T1RUN).
While the CPU is halte d, the periphe rals c ontin ue to b e
clocked from the previously selected clock source.

3.4.5 EXIT TO SLEEP MODE

An exit from a power managed Run mode to Sleep
mode is executed by clearing the IDLEN and
SCS1:SCS0 bits and executing a SLEEP instruction.
The code is no diff erent than the me thod used to invoke
Sleep mode from the normal operating (full power)
mode.

The primary clock and internal oscillator block are dis­abled. The INTRC will continue to operate if the WDT
is enabled. The Timer1 oscillator will continue to run, if
enabled, in the T1C ON regis ter. All clock sourc e st atus
bits are cleared (OSTS, IOFS and T1RUN).

3.5 Wake-up From Power Managed

Modes

An exit from any of the power managed modes is trig­gered by an interrupt, a Rese t, or a WDT time -out. This
section discusses the triggers that cause exits from
power managed modes. The clocking subsystem
actions are discussed in each of the power managed
modes (see Section 3.2 “Sleep Mode” through

Section 3.4 “Run Modes”).

Note: If application code is timing sensitive, it

should wait for the OSTS bi t to become set
before continuing. Use the interval during
the low-power exit sequence (before
OSTS is set) to perform timing insensitive
“housekeeping” tasks.

Device behavior during Low-Power mode exits is
summarized in Table 3-3.

3.5.1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the
device to exit a power managed mode and resume full
power operation. To enable this functionality, an inter­rupt source must be e nab le d by s etti ng its enable bit i n
one of the INTCON or PIE register s. The exit sequenc e
is initiated when the corresponding interrupt flag bit is
set. On all exits from Lower Power mode by interrupt,
code execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).

DS39599C-page 38  2003 Microchip Technology Inc.

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TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR

ANY IDLE MODE (BY CLOCK SOURCES)

Power
Clock in Power
Managed Mode

Primary System

Clock

Managed

Mode Exit

Delay

LP, XT, HS

Primary System
Clock
(PRI_IDLE mode)

HSPLL
EC, RC, INTRC
INTOSC

(2)

(1)

5-10 µs

LP, XT, HS OST

T1OSC or

(1)

INTRC

HSPLL OST + 2 ms

(1)

EC, RC, INTRC
INTOSC

(2)

5-10 µs

1ms

LP, XT, HS OST

INTOSC

(2)

HSPLL OST + 2 ms

(2)

(1)

5-10 µs

None IOFS

EC, RC, INTRC
INTOSC
LP, XT, HS OST

Sleep mode

HSPLL OST + 2 ms

(1)

EC, RC, INTRC
INTOSC

(2)

5-10 µs

1ms

Note 1: In this instance, refers specifically to the INTRC clock source.

2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: Two-Speed Start-up is covered in greater detail in Section 23.3 “Two-Speed Start-up”.
4: Execution continues during the INTOSC stabilization period.
5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other

required delays (see Section 3.3 “Idle Modes”).

(5)

(5)

(4)

(5)

(5)

(4)

Clock Ready

Status Bit

(OSCCON)

OSTS

—

IOFS

OSTS

—

IOFS

OSTS

—

OSTS

—

IOFS

Activity During Wake-up from

Power Managed Mode

Exit by Interrupt Exit by Reset

CPU and peripherals
clocked by prim ary cloc k
and executing

Not clocked or
Two-Speed Start-up
(if enabled)

instructions.

CPU and peripherals
clocked by selected
power managed mode
clock and executing
instructions until prim ary
clock source becomes
ready.

Not clocked or
Two-Speed Start-up (if
enabled) until primary
clock source becomes

(3)

ready

.

(3)

.

 2003 Microchip Technology Inc. DS39599C-page 39

PIC18F2220/2320/4220/4320

3.5.2 EXIT BY RESET

Normally, the device is held in Reset by the Oscillator
Star t-up Timer (OST) until the primary clock (defi ned in
Configuration Register 1H) becomes ready. At that
time, the OSTS bit is set and the device begins
executing code.

Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 23.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 23.4 “Fail-Safe Clock
Monitor”) are enabled in Configuration Register 1H,
the device may begin execution as soon as the Reset
source has cleared. Execution is clocked by the
INTOSC multiplexer driven by the internal oscillator
block. Since the OSCCON register is cleared fo llowing
all Resets, the INTRC clock source is selected. A higher
speed clock may be selected by modifying the IRCF bits
in the OSCCON register. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready, or a power managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.

3.5.3 EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending
on which power managed mode the device is in when
the time-out occurs.

If the devic e is not exec uti ng co de (al l Id le mo des and
Sleep mode), the time -out wi ll resu lt i n a w ake-up from
the power managed mode (see Section 3.2 “Sleep
Mode” through Section 3.4 “Run Modes”).

If the device is executing code (all Run modes), the
time-out will result in a WDT Reset (see Section 23.2
“Watchdog Timer (WDT)”).

The WDT timer and postscaler are cleared by execut­ing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
system clock source.

3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY

Certain exits from power managed modes do not
invoke the OST at all. These are:

• PRI_IDLE mode, where the primary clock source

is not stopped; and

• the primary clock source is not any of the LP, XT,

HS or HSPLL modes.

In these cases, the primary clock source either does
not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes).

However, a fixed del ay (a ppro xi ma tel y 10 µs) following
the wake-up event is required when leaving Sleep and
Idle modes. This delay is required for the CPU to pre­pare for execution. Instruction execution resumes on
the first clock cycle following this delay.

3.6 INTOSC Frequency Drift

The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways.

It is possible to adjust the INTOSC frequency by modi­fying the value in the OSCTUNE register. This has the
side effect that the INTRC clock source frequency is
also affected. However, the features that use the
INTRC source often do not require an exact frequency.
These features inc lude the Fail-Safe Clock Moni tor, the
Watchdog Timer and the RC_RUN/RC_IDLE modes
when the INTRC clock source is selected.

Being able to adjust the INTOSC requires knowing
when an adjustment is required, in which direction it
should be made and in some cases, how large a
change is needed. Three examples are shown but
other techniques may be used .

DS39599C-page 40  2003 Microchip Technology Inc.

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3.6.1 EXAMPLE – USART

An adjustment may be indicated when the USART
begins to generate framing errors or receives data
with errors while in Asynchronous mode. Framing
errors indicate that the system clock frequency is too
high – try decrementing the value in the OSCTUNE
register to reduce the system cl ock frequency. Errors in
data may suggest that the system clock speed is too
low – increment OSCTUNE.

3.6.2 EXAMPLE – TIMERS

This technique compares system clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillat or.

Both timers are cleared but the tim er clocked by the ref­erence generates interr upts. Whe n an interrupt occurs ,
the internally clocked timer is read and both timers are
cleared. If the internally clocked timer value is greater
than expected, then the internal oscillator block is
running too fast – decrement OSCTUNE.

3.6.3 EXAMPLE – CCP IN CAPTURE MODE

A CCP module can use free running Timer1 (or
Timer3), cl oc ked by the internal oscillator block and an
external event with a known period (i.e., AC power fre­quency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is su btra cte d fro m the tim e of th e
second event. Since the period of the external event is
known, the time difference between events can be
calculated.

If the measured time is much greater than the
calculated time, the i nternal oscillator block is ru nning
too fast – decreme nt OSCT UNE. I f the me asured time
is much less than the calculated time, the internal
oscillator block is running too slow – increment
OSCTUNE.

 2003 Microchip Technology Inc. DS39599C-page 41

PIC18F2220/2320/4220/4320

NOTES:

DS39599C-page 42  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

4.0 RESET

Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal oper-

The PIC18F2X20/4X20 devices differentiate between
various kinds of Reset:

a) Power-on Reset (POR)
b) MCLR

Reset while executing instructions
c) MCLR Reset when not executing instructions
d) Watchdog Timer (WDT) Reset (during

execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset

Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.

ation. Status bits from the RCON register, RI

and BOR, are set or cleared differently in different

POR
Reset situations as indicated in Table 4-2. These bits
are used in software to determine the nature of the
Reset. See Table4-3 for a full description of the Reset
states of all registers.

A simplified block di agram o f the on- chip Re set circ uit
is shown in Figure 4-1.

The enhanced MCU devices have a MCLR
in the MCLR

Reset path. The filter will detect and

ignore small pulses.
The MCLR

pin is not driven low by any internal Resets,

including the WDT.
The MCLR input pro vided by the MCLR p in ca n be dis -

abled with the MCL RE bit i n Configuration Registe r 3H
(CONFIG3H<7>). See Section 23.1 “Configuration

Bits” for more information.

FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

, TO, PD,

noise filter

MCLR

VDD

OSC1

( )_IDLE

Sleep

WDT

Time-out

DD Rise

V

Detect

Brown-out

Reset

OST/PWRT

32 µs

(1)

INTRC

External Reset

MCLRE

POR Pulse

BOREN

OST

PWRT

1024 Cycles

10-bit Ripple Counter

65.5 ms

11-bit Ripple Counter

S

Chip_Reset

R

Q

Enable PWRT

Enable OST

(2)

Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.

2: See Table 4-1 for time-out situations.

 2003 Microchip Technology Inc. DS39599C-page 43

PIC18F2220/2320/4220/4320

4.1 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

DD rise is detected. To take advantage of the PO R cir-

V
cuitry, just tie the MCLR
10 kΩ) to V

DD. This will eliminate external RC compo-

nents usually needed to create a Power-on Reset
delay. A minimum rise rate for V
(parameter D004) . For a s low rise t ime, see F igure 4-2.

When the device st arts normal operati on (i.e ., ex its the
Reset condition), device operating parameters (volt­age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.

FIGURE 4-2: EXTERNAL POWER-ON

V

VDD

Note 1: External Power-on Reset circuit is

DD

D

required only if the V
too slow. The diode D helps discharge the
capacitor quickly when V

2: R < 40 k Ω is recommend ed to make sure

that the voltage drop across R does not
violate the device’s electrical specification.

3: R1 ≥ 1 kΩ will limit any current flowing into

MCLR
event of MCLR
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).

pin through a resistor (1k to

DD is specified

RESET CIRCUIT (FOR
SLOW V

R

C

from external capacitor C, in the

DD POWER-UP)

R1

MCLR

PIC18FXXXX

DD power-up slope is

DD powers down.

/VPP pin breakdown, due to

4.3 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (para meter #33). Th is ensures th at
the crystal oscillator or resonator has started and
stabilized.

The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most power managed modes .

4.4 PLL Lock Time-out

With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A portion of the
Power-up Tim er is used to provi de a fixed time-ou t that
is sufficient f or the PLL to loc k to the main os cillator f re­quency. This PLL lock time-out (T

PLL) is typically 2 ms

and follows the oscillator start-up time-out.

4.5 Brown-out Reset (BOR)

A configuration bit, BOREN, can disable (if clear/
programmed) or enable (if set) the Brown- out Reset cir­cuitry. If V
greater than T
ation will reset the chip. A Reset may not occur if V

DD falls below VBOR (parameter D005) for

BOR (parameter #35), the brown-out sit u-

DD

falls below VBOR for less than TBOR. The chip will
remain in Brown-out Reset until V

DD rises above VBOR .

If the Power-up T imer is enable d, it will be invo ked after

DD rises above VBOR; it then will keep the chip in

V
Reset for an additional time delay T
#33). If V

DD drops below VBOR while the Power-up

PWRT (parameter

Timer is ru nni ng, the chip will go ba ck in to a Bro w n-o ut
Reset and the Power-up Timer will be initialized. Once

DD rises above VBOR, the Power-up Timer will execute

V
the additional time delay. Enabling BOR Res et does
not automatically enable the PWRT.

4.6 Time-out Sequence

On power-up, the time-out sequence is as follows:
First, after the POR pulse has cle are d, PWRT time-out

4.2 Power-up Timer (PWRT)

The Power-up Timer (PWRT) of the PIC18F2X20/4X20
devices is an 11-bit counter, which uses the INTRC
source as the clock input. This yields a count of
2048 x 32 µs = 65.6 ms. While the PWRT is counting,
the device is held in Reset.

The power-up time delay depe nd s on the INTRC cl oc k
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter #33 for details.

The PWRT is enabled by clearing configuration bit,
PWRTEN

.

is invoked (if enab led). Then , the OST i s activated . The
total time-out wi ll var y base d o n oscill ator confi guratio n
and the status of the PWR T. For example, in RC mode
with the PWRT disabled , there will be no time-o ut at all.
Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and
Figure 4-7 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, if MC LR
is kept low long e nough, all ti me -out s will e xpire. Brin g­ing MCLR

high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.

Table 4-2 shows the Reset conditions for some Special
Function Registers, while Table 4-3 shows the Reset
conditions for all the registers.

DS39599C-page 44  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS

Oscillator

Configuration

HSPLL 66 ms

PWRTEN = 0 PWRTEN = 1

(1)

+ 1024 TOSC + 2 ms
HS, XT, LP 66 ms
EC, ECIO 66 ms
RC, RCIO 66 ms
INTIO1, INTIO2 66 ms

Power-up

(1)

+ 1024 TOSC 1024 TOSC 1024 TOSC

(1)
(1)
(1)

Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.

2: 2 ms is the nominal time required for the 4x PLL to lock.

REGISTER 4-1: RCON REGISTER BITS AND POSITIONS

R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-1 R/W-1

IPEN

bit 7 bit 0

Note: Refer to Section 5.14 “RCON Register” for bit definitions.

— —RITO PD POR BOR

(2)

and Brown-out

(2)

1024 TOSC + 2 ms

Exit from

Power Managed Mode

(2)

1024 TOSC + 2 ms

(2)

——
——
——

TABLE 4-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Condition

Program

Counter

Power-on Reset 0000h 0--1 1100 1 1 1 0 0 0 0
RESET Instruction 0000h 0--0 uuuu 0 u u u u u u

Brown-out 0000h 0--1 11u- 1 1 1 u 0 u u

during power managed

MCLR
Run modes

during power managed

MCLR
Idle modes and Sleep mode

WDT Ti me -out du rin g full power
or power managed Run mode

during ful l power

MCLR

0000h 0--u 1uuu u 1 u u u u u

0000h 0--u 10uu u 1 0 u u u u

0000h 0--u 0uuu u 0 u u u u u

execution
Stack Full Reset (STVREN = 1) 1u

0000h 0--u uuuu u u u u u

Stack Underflow Reset
(STVREN = 1)

Stack Underflow Error (not an
actual Reset, STVREN = 0)

WDT Time-out during power
managed Idle or Sleep modes

Interrupt exit from power
managed modes

0000h u--u uuuu u u u u u u 1

PC + 2 u--u 00uu u 0 0 u u u u

PC + 2 u--u u0uu u u 0 u u u u

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (0x00000 8h or 0x00 001 8h ).

RCON

Register

TO PD POR BOR STKFUL STKUNF

RI

uu

u1

 2003 Microchip Technology Inc. DS39599C-page 45

PIC18F2220/2320/4220/4320

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Resets

MCLR

Register Applicable Devices

Power-on Reset,

Brown-out Reset

TOSU 2220 2320 4220 4320 ---0 0000 ---0 0000 ---0 uuuu
TOSH 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
TOSL 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
STKPTR 2220 2320 4220 4320 uu-0 0000 00-0 0000 uu-u uuuu
PCLATU 2220 2320 4220 4320 ---0 0000 ---0 0000 ---u uuuu
PCLATH 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
PCL 2220 2320 4220 4320 0000 0000 0000 0000 PC + 2
TBLPTRU 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu
TBLPTRH 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
TABLAT 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
PRODH 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 2220 2320 4220 4320 0000 000x 0000 000u uuuu uuuu
INTCON2 2220 2320 4220 4320 1111 -1-1 1111 -1-1 uuuu -u-u
INTCON3 2220 2320 4220 4320 11-0 0-00 11-0 0-00 uu-u u-uu
INDF0 2220 2320 4220 4320 N/A N/A N/A
POSTINC0 2220 2320 4220 4320 N/A N/A N/A
POSTDEC0 2220 2320 4220 4320 N/A N/A N/A
PREINC0 2220 2320 4220 4320 N/A N/A N/A
PLUSW0 2220 2320 4220 4320 N/A N/A N/A
FSR0H 2220 2320 4220 4320 ---- xxxx ---- uuuu ---- uuuu
FSR0L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 2220 2320 4220 4320 N/A N/A N/A
POSTINC1 2220 2320 4220 4320 N/A N/A N/A
POSTDEC1 2220 2320 4220 4320 N/A N/A N/A
PREINC1 2220 2320 4220 4320 N/A N/A N/A
PLUSW1 2220 2320 4220 4320 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated devic e.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is du e t o an in terrupt and the GIEL or G IEH bi t i s s et, the T O SU, TOSH and TO SL ar e

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

WDT Reset

RESET Instruction

Stack Rese ts

Wake-up via WDT

or Interrupt

(3)
(3)
(3)
(3)

(2)

(1)
(1)
(1)

DS39599C-page 46  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

Register Applicable Devices

FSR1H 2220 2320 4220 4320 ---- xxxx ---- uuuu ---- uuuu
FSR1L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 2220 2 320 4220 4320 ---- 0000 ---- 0000 ---- uuuu
INDF2 2220 2320 4220 4320 N/A N/A N/A
POSTINC2 2220 2320 4220 4320 N/A N/A N/A
POSTDEC2 2220 2320 4220 4320 N/A N/A N/A
PREINC2 2220 2320 4220 4320 N/A N/A N/A
PLUSW2 2220 2320 4220 4320 N/A N/A N/A
FSR2H 2220 2320 4220 4320 ---- xxxx ---- uuuu ---- uuuu
FSR2L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 2220 2320 4220 4320 ---x xxxx ---u uuuu ---u uuuu
TMR0H 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
TMR0L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu
OSCCON 2220 2320 4220 4320 0000 q000 0000 q000 uuuu qquu
LVDCON 2220 2320 4220 4320 --00 0101 --00 0101 --uu uuuu
WDTCON 2220 2320 4220 4320 ---- ---0 ---- ---0 ---- ---u

(4)

RCON
TMR1H 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 2220 2320 4220 4320 0000 0000 u0uu uuuu uuuu uuuu
TMR2 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
PR2 2220 2320 4220 4320 1111 1111 1111 1111 1111 1111
T2CON 2220 2320 4220 4320 -000 0000 -000 0000 -uuu uuuu
SSPBUF 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
SSPCON1 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
SSPCON2 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

3: When the wake-up is du e t o an in terrupt and the GIEL or GI EH bi t i s set, the TOSU, T OSH an d TOSL are

4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

2220 2320 4220 4320 0--1 11q0 0--q qquu u--u qquu

Shaded cells indicate condi tions do not apply for the designated devic e.

interrupt vector (0008h or 0018h).

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

not enabled as PORTA pins, they are disabled and read ‘0’.

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Rese ts

Wake-up via WDT

or Interrupt

 2003 Microchip Technology Inc. DS39599C-page 47

PIC18F2220/2320/4220/4320

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

Register Applicable Devices

ADRESH 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu
ADCON1 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu
ADCON2 2220
CCPR1H 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON
CCPR2H 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu
PWM1CON 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
ECCPAS 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
CVRCON 2220 2320 4220 4320 000- 0000 000- 0000 uuu- uuuu
CMCON 2220 2320 4220 4320 0000 0111 0000 0111 uuuu uuuu
TMR3H 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 2220 2320 4220 4320 0000 0000 uuuu uuuu uuuu uuuu
SPBRG 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
RCREG 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
TXREG 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
TXSTA 2220 2320 4220 4320 0000 -010 0000 -010 uuuu -uuu
RCSTA 2220 2320 4220 4320 0000 000x 0000 000x uuuu uuuu
EEADR 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
EEDATA 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
EECON1 2220 2320 4220 4320 xx-0 x000 uu-0 u000 uu-0 u000
EECON2 2220 2320 4220 4320 0000 0000 0000 0000 0000 0000
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated devic e.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is du e t o an in terrupt and the GIEL or G IEH bi t i s s et, the T O SU, TOSH and TO SL ar e

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

2320 4220 4320 0-00 0000 0-00 0000 u-uu uuuu

2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Rese ts

Wake-up via WDT

or Interrupt

DS39599C-page 48  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

Register Applicable Devices

Power-on Reset,

Brown-out Reset

IPR2 2220 2320 4220 4320 11-1 1111 11-1 1111 uu-u uuuu
PIR2 2220 2320 4220 4320 00-0 0000 00-0 0000 uu-u uuuu
PIE2 2220 2320 4220 4320 00-0 0000 00-0 0000 uu-u uuuu

IPR1

PIR1

PIE1

2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu
2220 2320

4220 4320 -111 1111 -111 1111 -uuu uuuu
2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
2220 2320 4220 4320 -000 0000 -000 0000 -uuu uuuu
2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
2220 2320 4220 4320 -000 0000 -000 0000 -uuu uuuu

OSCTUNE 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu
TRISE

2220 2320 4220 4320 0000 -111 0000 -111 uuuu -uuu

TRISD 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu
TRISC 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu
TRISB 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu
TRISA

(5)

2220 2320 4220 4320 1111 1111

(5)

LATE 2220 2320 4220 4320 ---- -xxx ---- -uuu ---- -uuu
LATD

2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu

LATC 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
LATA

(5)

2220 2320 4220 4320 xxxx xxxx

(5)

PORTE 2220 2320 4220 4320 ---- xxxx ---- xxxx ---- uuuu
PORTD 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA

(5)

2220 2320 4220 4320 xx0x 0000

(5)

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated devic e.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is du e t o an in terrupt and the GIEL or GI EH bi t i s set, the TOSU, T OSH an d TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

WDT Reset

RESET Instruction

Stack Rese ts

1111 1111

uuuu uuuu

uu0u 0000

(5)

(5)

(5)

Wake-up via WDT

or Interrupt

uuuu uuuu

uuuu uuuu

uuuu uuuu

(1)

(1)
(1)

(5)

(5)

(5)

 2003 Microchip Technology Inc. DS39599C-page 49

PIC18F2220/2320/4220/4320

FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Re s e t

TPWRT

NOT TIED TO VDD): CASE 1

TOST

FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

DS39599C-page 50  2003 Microchip Technology Inc.

NOT TIED TO VDD): CASE 2

TOST

PIC18F2220/2320/4220/4320

FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

5V

VDD

MCLR

Internal POR

0V

T

PWRT

1V

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

PLL Time-out

TOST

TPLL

Internal Reset

Note: TOST = 1024 clock cycles.

T

PLL ≈ 2 ms max. First three stages of the PWRT timer.

 2003 Microchip Technology Inc. DS39599C-page 51

PIC18F2220/2320/4220/4320

NOTES:

DS39599C-page 52  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

5.0 MEMORY ORGANIZATION

There are three memory types in Enhanced MCU
devices. These memory types ar e:

• Program Memory

• Data RAM

• Data EEPROM
Data and program m emory use sep arate bus ses which

allow for concurrent access of these types.
Additional det ailed infor mation for F lash program mem-

ory and data EEPROM is provided in Section 6.0

“Flash Program Memory” and Section 7.0 “Data
EEPROM Memory”, respectively.

FIGURE 5-1: PROGRAM MEMORY MAP

AND STACK FOR
PIC18F2220/4220

PC<20:0>

CALL,RCALL,RETURN
RETFIE,RETLW

Stack Level 1

Stack Level 31

21

•

•

•

5.1 Program Memory Organization

A 21-bit progra m count er is capab le of addr essin g the
2-Mbyte program m emo ry space. Accessing a l oca tion
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).

The PIC18F2220 and PIC18F4220 each have
4 Kbytes of Flash memory and can store up to 2,048
single-word instructions.

The PIC18F2320 and PIC18F4320 each have
8 Kbytes of Flash memory and can store up to 4,096
single-word instructions.

The Reset vector address is at 0000h and the interru pt
vector addresses are at 0008h and 0018h.

The Program Memory Maps for PIC18F2220/4220 and
PIC18F2320/4320 devices are shown in Figure 5-1
and Figure 5-2, respectively.

FIGURE 5-2: PROGRAM MEMORY MAP

AND STACK FOR
PIC18F2320/4320

PC<20:0>

CALL,RCALL,RETURN
RETFIE,RETLW

Stack Level 1

Stack Level 31

21

•

•

•

Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector

On-Chip

Program Memory

Read ‘0’

0000h
0008h

0018h

0FFFh
1000h

1FFFFFh
200000h

Reset Vector

High Priority Interrupt Vector

Low Priority Interrupt Vector

On-Chip

Program Memory

User Memory Space

Read ‘0’

0000h
0008h

0018h

1FFFh
2000h

User Memory Space

1FFFFFh
200000h

 2003 Microchip Technology Inc. DS39599C-page 53

PIC18F2220/2320/4220/4320

5.2 Return Address Stack

The return address s tack allows any co mbination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is execute d or an interrup t is
Acknowledged. The PC val ue is pul led of f th e stack on
a RETURN, RETLW or a RETFIE instruct ion. P CLATU
and PCLATH are not affected by any of the RETURN or
CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all Resets. There is no RAM associated
with stack pointer 00000b. This is only a Reset value.
During a CALL type instruc tion, causing a pu sh onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC (already pointing to the
instruction following the CALL). During a RETURN type
instruction, causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR are
transferred to the PC and then the stack pointer is
decremented.

The stack space is not part of either program or data
space. The stack po inter is r eadabl e and writabl e and
the address on the top of the stac k is readab le and writ­able through the top-of-stack Special File Registers.
Data can also be pushed to, or popped from, the stack
using the top-of-stack SFRs. Status bits indicate if the
stack is full, has overflowed or underflowed.

5.2.1 TOP-OF-STACK ACCESS

The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, hold the
contents of the stack location pointed to by the
STKPTR register (Figure 5-3). This allows users to
implement a software stack if nece ssary . Afte r a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU, TO SH and TOSL regis ters.
These values can b e placed on a user define d software
stack. At return time, the software can replace the
TOSU, TOSH and TOSL and do a return.

The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.

5.2.2 RETURN STACK POINTER (STKPTR)

The STKPTR register (Re giste r 5-1) contains the st ac k
pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the stack pointer can be 0 through 31. The stack
pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. At Reset, the stack pointer value will be zero.
The user may read and write the stack pointer value.
This feature can be used by a Real-Time Operating
System for return stack maintenance.

After the PC is pus hed on to the st ack 31 tim es (wi thout
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.

The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over­flow Reset Enable) configuration bit. (Refer to
Section 23.1 “Configuration Bits” for a descript ion of
the device configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the stack
pointer will be set to zero.

If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push,
and STKPTR will remain at 31.

When the stack has been popped enough times to
unload the stac k, the next pop will ret urn a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at zero. The STKUNF bit will remain
set until cleared by software or a POR occurs.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.

FIGURE 5-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address S t ac k

11111
11110

TOSLTOSHTOSU

34h1Ah00h

Top-of-Stack

DS39599C-page 54  2003 Microchip Technology Inc.

001A34h

000D58h

11101

00011
00010
00001
00000

STKPTR<4:0>

00010

PIC18F2220/2320/4220/4320

REGISTER 5-1: STKPTR REGISTER

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL STKUNF

bit 7 bit 0

— SP4 SP3 SP2 SP1 SP0

(1)

bit 7

(1)

bit 6

bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Location bits

STKFUL: Stack Full Flag bit

1 = Stack became full or overflowed
0 = Stack has not become full or overflowed

STKUNF: Stack Underflow Flag bit

1 = Stack underflow occurred
0 = Stack underflow did not occur

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

Legend:

R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

5.2.3 PUSH AND POP INSTRUCTIONS

Since the Top-of-Stack (TOS) is rea dab le a nd w ritable,
the ability to push valu es onto the stack and pull va lues
off the sta ck, withou t disturbi ng normal program ex ecu­tion, is a desirable optio n. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will i ncrem ent th e stack point er and load the cu r­rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place data or a return address
on the stack.

The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP inst ruction. T he POP instru c­tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.

5.2.4 STACK FULL/UNDERFLOW RESETS

These Resets are enabled by programming the
STVREN bit in Configuration Register 4L. When the
STVREN bit is cleared, a full or underf low conditi on will
set the appropriate STKFUL or STKUNF bit but not
cause a device Reset. When the STVREN bit is set, a
full or underflow condition will set the appropriate
STKFUL or STKUNF bit and then cause a device
Reset. The STKFUL or STKUNF bits are cl eared by the
user software or a POR Reset.

 2003 Microchip Technology Inc. DS39599C-page 55

PIC18F2220/2320/4220/4320

5.3 Fast Register Stack

A “fast return” option is available for interrupts. A Fast
Register Stack is provided for the Status, WREG and
BSR registers and are only one in depth. The stack is
not readable or writable and is loaded with the current
value of the correspo nding regi ster when the pro cessor
vectors for an interrupt. The values in the registers are
then loaded back into the working registers if the
RETFIE, FAST instruction is used to return from the
interrupt.

All interrupt sources w ill push va lues into the stack reg­isters. If both low and high priority interrupts are
enabled, the stack registers cannot be used reliably to
return from low priority interrupt s. If a high pri ority inter­rupt occurs while servicing a low priority interrupt, the
stack register v al ues s tor ed by the l ow p riori ty in terru pt
will be overwritten. Users must save the key registers
in software during a low priority interrupt.

If interrupt priority is not used, all interrupts ma y use the
Fast Register Stack for returns from interrupt.

If no interrupts are used, the F ast Register S ta ck can be
used to restore the S tatus, WR EG and BSR registers at
the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the Status,
WREG and BSR registers to the Fast Register S tack. A
RETURN, FAST instruction is then ex ec uted to re sto r e
these registers from the Fast Register Stack.

Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.

5.4 PCL, PCLATH and PCLATU

The Program Counter (PC) s pecifies the ad dress of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte, known as the PCL register, is both
readable and writable. The high byte, or PCH register,
contains the PC<15 :8> bit s and is not direc tly read able
or writable. Updates to the PCH register may be per­formed through the PCLATH register. The upper byte i s
called PCU. This register contains the PC<20:16> bits
and is not directly readable or writable. Updates to the
PCU register may be performed through the PCLATU
register.

The contents of PCLATH and PCLATU will be trans­ferred to the program counter by any operation that
writes PCL. Similarly, the upper two bytes of the pro­gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 5.8.1
“Computed GOTO”).

The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ‘0’.
The PC increments by 2 to address sequential
instructions in the program memo ry.

The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.

EXAMPLE 5-1: FAST REGISTER STACK

CODE EXAMPLE

CALL SUB1, FAST ;STATUS, WREG, BSR

•

•

SUB1 •

•

RETURN FAST ;RESTORE VALUES SAVED

;SAVED IN FAST REGISTER
;STACK

;IN FAST REGISTER STACK

DS39599C-page 56  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

5.5 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q 2, Q3 and Q4. Internally, the Pro­gram Counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc­tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure5-4.

FIGURE 5-4: CLOCK/ INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1
Q2
Q3

Q4
PC

OSC2/CLKO

(RC mode)

Q1

PC

Execute INST (PC-2)

Fetch INST (PC)

Q1

Execute INST (PC)
Fetch INST (PC+2)

5.6 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruc tio n fetch and execute ar e
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are req uired to c omplete the ins truction
(Example 5-2).

A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.

In the execution cy cle, the fetch ed instruction i s latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 c ycles. Dat a m emory is read during Q2
(operand read) and written during Q4 (destination
write).

Q2 Q3 Q4

PC+2

Q2 Q3 Q4

Q1

PC+4

Execute INST (PC+2)

Fetch INST (PC+4)

Internal
Phase
Clock

EXAMPLE 5-2: INSTRUCTION PIPELINE FLOW

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

All instructions are single cycle, except for any program branche s. These take tw o cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.

 2003 Microchip Technology Inc. DS39599C-page 57

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush (NOP)

Fetch SUB_1 Execute SUB_1

PIC18F2220/2320/4220/4320

5.7 Instructions in Program Memory

The program memory is addressed in bytes. Instruc­tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 5-5 shows an
example of how instructi on words are stored in the pro­gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 5.4 “PCL,
PCLATH and PCLATU”).

The CALL and GOTO instruc tions have the absolute p ro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound­aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-5 shows how the
instruction ‘GOTO 000006h’ is encoded in the program
memory. Program branch i nst ructions, which encode a
relative address offset, operate in the same manner.
The offset value stored in a branch instruction repre­sents the number of single-word instructions that the
PC will be offset by. Section 24.0 “Instruction Set
Summary” provides further details of the instruction
set.

FIGURE 5-5: INSTRUCTIONS IN PROGRAM MEMORY

LSB = 1 LSB = 0 ↓

0Fh 55h 000008h
EFh 03h 00000Ah
F0h 00h 00000Ch
C1h 23h 00000Eh
F4h 56h 000010h

Instruction 1:
Instruction 2:

Instruction 3:

Program Memory
Byte Locations

MOVLW 055h
GOTO 000006h

MOVFF 123h, 456h

→

Word Address

000000h
000002h
000004h
000006h

000012h
000014h

5.7.1 TWO-WORD INSTRUCTIONS

PIC18F2X20/4X20 devic es have four two-wor d instruc­tions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the 4 MSBs set to ‘1’s
and is decoded as a NOP instruction. The lower 12 bits
of the second word contain data to be used by the
instruction. If the first word of the instruction is exe­cuted, the data in the second word is accessed. If the

second word of the in struction is executed by itself (firs t
word was skipped), it will exec ute as a NOP. This action
is necessary when the two-word inst ruction is prec eded
by a conditional instruction that results in a skip opera­tion. A program example that demonstrates this con­cept is shown in Example 5-3. Refer to Section 24.0
“Instruction Set Summary” for further details of the
instruction set.

EXAMPLE 5-3: TWO-WORD INSTRUCTIONS

CASE 1:
Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:
Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

DS39599C-page 58  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

5.8 Look-up Tables

Look-up tables are implemented two ways:

• Computed GOTO

• Table Reads

5.8.1 COMPUTED GOTO

A computed GOTO is accomplish ed by adding an of fset
to the program counter. An example is shown in
Example 5-4.

A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to tha t t able. The first instru ction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.

The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSB = 0).

In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.

EXAMPLE 5-4: COMPUTED GOTO USING

AN OFFSET VALUE

MOVFW OFFSET

CALL TABLE
ORG 0xnn00
TABLE ADDWF PCL

RETLW 0xnn

RETLW 0xnn

RETLW 0xnn

•

•

•

5.8.2 TABLE READS/TABLE WRITES

A better method of storing data in program memory
allows two bytes of dat a to be stored in each instruction
location.

Look-up table data may be stored two bytes per pro­gram word by using table reads and writes. The table
pointer (TBLPTR) specifies the byte address and the
table latch (TABLAT) contains the data that is read
from, or written to pro gram memory. Data is transferred
to/from program memory, one byte at a time.

The Table Read/Table Write operation is discussed
further in Section 6.1 “Table Reads and Table

Writes”.

5.9 Data Memory Organization

The data memory is im ple me nte d as st atic RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 5-6
shows the data memory organization for the
PIC18F2X20/4X20 devices.

The data memory map is divided into as many as 16
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR<3:0>) select which
bank will be access ed. Th e uppe r 4 bit s o f the BSR a re
not implemented.

The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are us ed for data
storage and scratch pad operations in the user’s appli­cation. The SFRs start at the last location of Bank 15
(FFFh) and extend towa rds F80h. Any remain ing space
beyond the SFRs in the bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any re ad of a n un im ple me nte d l oca tion
will read as ‘0’s.

The entire data memory may be accessed directly or
indirectly. Direct add ress in g m ay re qui re the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indi­rect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the data memory map without banking. See

Section 5.12 “Indirect Addressing, INDF and FSR
Registers” for indirect addressing details.

The instruction set and architecture allow operations
across all banks. This ma y be accompli shed by indirec t
addressing or by the us e of th e MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.

To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A s egment of Bank 0 and a segme nt of
Bank 15 comprise the Access RAM. Section 5.10
“Access Bank” provides a detailed description of the
Access RAM.

5.9.1 GENERAL PURPOSE REGISTER FILE

Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.

Data RAM is available for use as GPR registers by all
instructions. The second half of Bank 15 (F80h to
FFFh) contains SFRs. All other banks of data memory
contain GPRs, starting with Bank 0.

 2003 Microchip Technology Inc. DS39599C-page 59

PIC18F2220/2320/4220/4320

FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2X20/4X20 DEVICES

BSR<3:0>

= 0000

= 0001

= 0010
= 1110

Bank 0

Bank 1

Bank 2

to

Bank 14

Data Memory Map

00h

Access RAM

FFh

00h

FFh

GPR

GPR

Unused

Read ‘00h’

000h

07Fh

080h
0FFh
100h

1FFh

200h

Access Bank

Access RAM Low

Access RAM High

(SFRs)

00h
7Fh

80h

FFh

= 1111

Bank 15

00h

FFh

Unused

SFR

EFFh
F00h
F7Fh

F80h
FFFh

When a = 0:

The BSR is ignored and the
Access Bank is used.

The first 128 bytes are
general purpose RAM
(from Bank 0).

The second 128 bytes are
Special Function Registers
(from Bank 15).

When a = 1:

The BSR specifies the bank
used by the instruction.

DS39599C-page 60  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

5.9.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers
used by the CPU and p eripheral modul es for controllin g
the desired operation of the device. These reg isters are
implemented as static RAM. A list of these registers is
given in Table 5-1 and Table 5-2.

The SFRs can be classified into two sets: those asso-

“core” are described i n this section, whil e tho se rel ate d
to the operation of the peripheral features are
described in the section of that periphe ral feature.

The SFRs are typically distributed among the
peripherals whose functions they control.

The unused SFR locations will be unimplemented and
read as ‘0’s.

ciated with the “core” function and those related to the
peripheral functions. Those registers related to the

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2X20/4X20 DEVICES

Address Name Address Name Address Name Address Name

(2)

FFFh TOSU FDFh INDF2
FFEh TOSH FDEh POSTINC2
FFDh TOSL FDDh POSTDEC2
FFCh STKPTR FDCh PREINC2
FFBh PCLATU FDBh PLUSW2
FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —

FF9h PCL FD9h FSR2L FB9h — F99h —
FF8h TBLPTRU FD8h STATUS FB8h — F98h —
FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON
FF6h TBLPTRL FD6h TMR0L FB6h ECCPAS
FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD
FF4h PRODH FD4h — FB4h CMCON F94h TRISC
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB
FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —
FF0h INTCON3 FD0h RCON FB0h — F90h —

(2)

FEFh INDF0

FEEh POSTINC0
FEDh POSTDEC0
FECh PREINC0
FEBh PLUSW0

FCFh TMR1H FAFh SPBRG F8Fh —

(2)

FCEh TMR1L FAEh RCREG F8Eh —

(2)

FCDh T1CON FADh TXREG F8Dh LATE

(2)

FCCh TMR2 FACh TXSTA F8Ch LATD

(2)

FCBh PR2 FABh RCSTA F8Bh LATC

FEAh FSR0H FCAh T2CON FAAh — F8Ah LATB

FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA

FE8h WREG FC8h SSPADD FA8h EEDATA F88h —

(2)

FE7h INDF1

FE6h POSTINC1

FE5h POSTDEC1

FE4h PREINC1

FE3h PLUSW1

FC7h SSPSTAT FA7h EECON2 F87h —

(2)

FC6h SSPCON1 FA6h EECON1 F86h —

(2)

FC5h SSPCON2 FA5h — F85h —

(2)

FC4h ADRESH FA4h — F84h PORTE

(2)

FC3h ADRESL FA3h — F83h PORTD
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

FBFh CCPR1H F9Fh IPR1

(2)

FBEh CCPR1L F9Eh PIR1

(2)

FBDh CCP1CON F9Dh PIE1

(2)

FBCh CCPR2H F9Ch —

(2)

FBBh CCPR2L F9Bh OSCTUNE

(1)

F97h —

(1)

F96h TRISE

(1)
(1)

(1)
(1)

(1)

Legend: — = Unimplemented registers, read as ‘0’.
Note 1: This register is not available on PIC18F2X20 devices.

2: This is not a physical register.

 2003 Microchip Technology Inc. DS39599C-page 61

PIC18F2220/2320/4220/4320

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TOSU
TOSH Top-of-Sta ck High Byte (TOS<15:8>) 0000 0000 46, 54
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 46, 54
STKPTR STKFUL STKUNF
PCLATU
PCLATH Holding Register for PC<15:8> 0000 0000 46, 56
PCL PC Low Byte (PC<7:0>) 0000 0000 46, 56
TBLPTRU
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 46, 74
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 46, 74
TABLAT Program Memory Table Latch 0000 0000 46, 74
PRODH Product Register High Byte xxxx xxxx 46, 85
PRODL Product Register Low Byte xxxx xxxx 46, 85
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 46, 89
INTCON2 RBPU
INTCON3 INT2IP INT1IP
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) n/a 46, 66
POSTINC0 Uses contents of FSR0 to address data memory – value of FS R0 post-incremented (not a physical register) n/a 46, 66
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) n/a 46, 66
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) n/a 46, 66
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 off set by W (not a physical register) n/a 46, 66
FSR0H
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 46, 66
WREG Working Register xxxx xxxx 46
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) n/a 46, 66
POSTINC1 Uses contents of FSR1 to address data memory – value of FS R1 post-incremented (not a physical register) n/a 46, 66
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) n/a 46, 66
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) n/a 46, 66
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 off set by W (not a physical register) n/a 46, 66
FSR1H
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 47, 66
BSR
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) n/a 47, 66
POSTINC2 Uses contents of FSR2 to address data memory – value of FS R2 post-incremented (not a physical register) n/a 47, 66
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) n/a 47, 66
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) n/a 47, 66
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 off set by W (not a physical register) n/a 47, 66
FSR2H
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 47, 66
STATUS
TMR0H Timer0 Register High Byte 0000 0000 47, 119
TMR0L Timer0 Register Low Byte xxxx xxxx 47, 119
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 47, 117

Legend: x = unknown , u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read

2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as

5: These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.
6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is

— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 46, 54

— Return Stack Pointer 00-0 0000 46, 55

— —bit 21

— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 46, 74

INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 46, 90

— — — — Indirect Data Memory Address Pointer 0 High ---- 0000 46, 66

— — — — Indirect Data Memory Address Pointer 1 High ---- 0000 47, 66

— — — — Bank Select Register ---- 0000 47, 65

— — — — Indirect Data Memory Address Pointer 2 High ---- 0000 47, 66

— — —NOVZDCC---x xxxx 47, 68

‘0’ in all other oscillator modes.

analog input and read ‘0’ following a Reset.

read-only.

(3)

Holding Register for PC<20:16> ---0 0000 46, 56

—INT2IEINT1IE— INT2IF INT1IF 11-0 0-00 46, 91

Value on

POR, BOR

Details on

page:

DS39599C-page 62  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

T ABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 26, 47
LVDCON
WDTCON

RCON IPEN
TMR1H Timer1 Register High Byte xxxx xxxx 47, 125
TMR1L Timer1 Register Low Byte xxxx xxxx 47, 125
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T 1SYNC
TMR2 Timer2 Register 0000 0000 47, 127
PR2 Timer2 Period Register 1111 1111 47, 127
T2CON
SSPBUF SSP Receive Buffer/Tran smit Register xxxx xxxx 47, 156,

SSPADD SSP Address Register in I
SSPSTAT SMP CKE D/A

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 47, 157,

SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 47, 167
ADRESH A/D Result Register High Byte xxxx xxxx 48, 220
ADRESL A/D Result Register Low Byte xxxx xxxx 48, 220
ADCON0
ADCON1
ADCON2 ADFM
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 48, 134
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 48, 134
CCP1CON P1M1

CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 48, 134
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 48, 134
CCP2CON
PWM1CON

(5)

ECCPAS
CVRCON CVREN CVROE CVRR
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 48, 221
TMR3H Timer3 Register High Byte xxxx xxxx 48, 131
TMR3L Timer3 Register Low Byte xxxx xxxx 48, 131
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
SPBRG USART Baud Rate Generator 0000 0000 48, 198
RCREG USART Receive Register 0000 0000 48, 204,

TXREG USART Transmit Register 0000 0000 48, 202,

TXSTA CSRC TX9 TXEN SYNC
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 48, 197

Legend: x = unknown , u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read

2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as

5: These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.
6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is

— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 47, 233
— — — — — — —SWDTEN--- ---0 47, 246

— —RITO PD POR BOR 0--1 11q0 45, 69, 98

TMR1CS TMR1ON 0000 0000 47, 121

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 47, 127

2

C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 47, 164

PSR/WUA BF 0000 0000 47, 156,

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 48, 211
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 48, 212

— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 48, 213

(5)

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 48, 133

(5)

PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 48, 149

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 48, 150

‘0’ in all other oscillator modes.

analog input and read ‘0’ following a Reset.

read-only.

P1M0

(5)

DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 48, 133,

— CVR3 CVR2 CVR1 CVR0 000- 0000 48, 227

TMR3CS TMR3ON 0000 0000 48, 129

— BRGH TRMT TX9D 0000 -010 48, 196

Value on

POR, BOR

Details on

page:

164

165

166

141

203

203

 2003 Microchip Technology Inc. DS39599C-page 63

PIC18F2220/2320/4220/4320

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

EEADR EEPROM Address Register 0000 0000 48, 81
EEDATA EEPROM Data Register 0000 0000 48, 84
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 48, 72, 81
EECON1 EEPGD CFGS
IPR2 OSCFIP CMIP
PIR2 OSCFIF CMIF
PIE2 OSCFIE CMIE
IPR1 PSPIP
PIR1 PSPIF
PIE1 PSPIE
OSCTUNE

(5)

TRISE

(5)

TRISD

(5)

ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 49, 96

(5)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 49, 92

(5)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 49, 94

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 23, 49

IBF OBF IBOV PSPMODE — D a ta Direc tion bits for PORTE

Data Direction Control Register for PORTD 1111 1111 49, 110

— FREE WRERR WREN WR RD xx-0 x000 48, 73, 82
— EEIP BCLIP LVDIP TMR3IP CCP2IP 11-1 1111 49, 97
— EEIF BCLIF LVDIF TMR3IF CCP2IF 00-0 0000 49, 93
— EEIE BCLIE LVDIE TMR3IE CCP2IE 00-0 0000 49, 95

(5)

0000 -111 49, 112

TRISC Data Direction Control Register for PORTC 1111 1111 49, 108
TRISB Data Direction Control Register for PORTB 1111 1111 49, 106
TRISA TRISA7

(5)

LATE
LATD

(5)

— — — — — Read/Write PORTE Data Latch ---- -xxx 49, 113

Read/Write PORTD Data Latch xxxx xxxx 49, 110

(2)

TRISA6

(1)

Data Direction Control Register for PORTA 1111 1111 49, 103

LATC Read/Write PORTC Data Latch xxxx xxxx 49, 108
LATB Read/Write PORTB Data Latch xxxx xxxx 49, 106
LATA LATA<7>
PORTE

— — — —RE3

(2)

LATA<6>

(1)

Read/Write PORTA Data Latch xxxx xxxx 49, 103

(6)

Read PORTE pins,
Write PORTE Data Latch

(5)

---- xxxx 49, 113

PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 49, 110
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 49, 108
PORTB Read PORTB pins, Write PORTB Data Latch
PORTA RA7

(2)

RA6

(1)

Read PORT A pins, Write PORTA Data Latch xx0x 0000 49, 103

(4)

xxxx xxxx 49, 106

Legend: x = unknown , u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read

‘0’ in all other oscillator modes.

2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as

analog input and read ‘0’ following a Reset.

5: These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.
6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is

read-only.

Details on

page:

DS39599C-page 64  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

5.10 Access Bank

The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.

This data memory region can be used for:

• Intermediate computational values

• Local variables of subroutines

• Faster context saving/switching of variables

• Common variables

• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the last 128 bytes in

Bank 15 (SFRs) and the first 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 5-6
indicates the Access RAM areas.

A bit in the instruction word spec ifie s if the opera tion is
to occur in the bank spec ifi ed by the BSR register or in
the Access Bank. This bit is denoted as the ‘a’ bit (for
access bit).

When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so these registers can
be accessed without any software overhead. This is
useful for testing st atus flags and m odifying control bit s.

5.1 1 Bank Select Register (BSR)

The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into as ma ny as six teen ban ks. When using
direct addressing, th e BSR should be confi gured for the
desired bank.

BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect (see Figure 5-7).

A MOVLB instruction has been provided in the
instruction set to assist in selecting banks.

If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Stat us register bit s will be set/clea red as appropriate for
the instruction performed.

Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.

A MOVFF instruction ignores the BSR since the 12-bit
addresses are embedded into the instruction word.

Section 5.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect address-

ing which allows linear addressing of the entire RAM
space.

FIGURE 5-7: DIRECT ADDRESSING

Direct Addressing

BSR<7:4>

0000

Bank Select

Note 1: For register file map detail, see Table 5-1.

2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the

registers of the Access Bank.

3: The MOVFF instruction embeds the entire 12-bit address in the instruction.

BSR<3:0> 7

(2)

Location Select

From Opcode

Data
Memory

(3)

(1)

(3)

0

00h 01h 0Eh 0Fh

000h

0FFh

Bank 0 Bank 1 Bank 14 Bank 15

100h

1FFh

E00h

EFFh

F00h

FFFh

 2003 Microchip Technology Inc. DS39599C-page 65

PIC18F2220/2320/4220/4320

5.12 Indirect Addressing, INDF and FSR Registers

Indirect addressing is a mode of addressing dat a mem­ory, where the data memory address in the instruction
is not fixed. An FSR regis ter i s u sed as a poi nte r to th e
data memory location that i s to be read or written. Since
this pointer is in RAM, the cont en t s c an be mo difi ed by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 5-8
shows how the fetched instruction is modified prior to
being executed.

Indirect addressing is possible by using one of the
INDF registers. Any ins tru cti on u si ng the IN DF reg ist er
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address which is shown in
Figure 5-9.

The INDFn register is not a physical register. Address­ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer); t his is indir ect addressing.

Example 5-5 shows a simple use of indirect add ressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.

EXAMPLE 5-5: HOW TO CLEAR RAM

(BANK 1) USING
INDIRECT ADDRESSING

LFSR FSR0,0x100 ;

NEXT CLRF POSTINC0 ; Clear INDF

; register then
; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank1?

GOTO NEXT ; NO, clear next

CONTINUE ; YES, continue

There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required:

1. FSR0: composed of FSR0H:FSR0L

2. FSR1: composed of FSR1H:FSR1L

3. FSR2: composed of FSR2H:FSR2L

In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address­ing with the value in the corresponding FSR register
being the a ddress of the data. If an instruction writes a
value to INDF0, th e v al ue will be w ritten to the address
pointed to by FSR 0H:FSR0L. A read f rom INDF 1 reads
the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.

If INDF0, I NDF1 or INDF2 are re ad indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivale nt to a NOP instruction and the
status bits are not affected.

5.12.1 INDIRECT ADDRESSING OPERATION

Each FSR register has an INDF register associated
with it, plus four addition al register addresses. Perform ­ing an operation using one of these five registers
determines how the FSR will be modified during
indirect addressing.

When data access is performed using one of the five
INDFn locations, the address selected will configure
the FSRn register to:

• Do nothing to FSRn after an indirect access (no

change) – INDFn

• Auto-decrement FSRn after an indirect acce ss

(post-decrement) – POSTDECn

• Auto-increment FSRn after an indirect access

(post-increment) – POSTINCn

• Auto-increment FS Rn before an indirect access

(pre-increment) – PREINCn

• Use the value in the WREG register as an offset

to FSRn. Do not mo dify the va lue of the WREG or
the FSRn register after an indirect access (no
change) – PLUSWn

When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
Status register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.

Auto-incrementing or auto-decrementing an FSR
affects all 12 bits. That is, when FSRnL overflows from
an increment, FSRnH will be incremented
automatically.

Adding these features allows the FSRn to be used as a
stack pointer, in addition to its use for table operations
in data memo ry.

Each FSR has an address associated with it that per­forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add th e s ig ned v alu e in the WREG regis­ter and the value in F S R to f orm the add res s befo re a n
indirect access. The FSR value is not changed. The
WREG offset range is -128 to +127.

If an FSR register contains a value that poin ts to one of
the INDFn, an indirect rea d will read 00h (zero b it is set)
while an indirect write will be equivalent to a NOP
(status bi ts are not affected).

If an indire ct addressing wr ite is performed when the
target address is an FSRnH or FSRnL register, the
data is written to the FSR register but no pre- or
post-increment/decrement is performed.

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FIGURE 5-8: INDIRECT ADDRESSING OPERATION

RAM

Instruction
Executed

Opcode Address

12

File Address = access of an indirect addressing register

0h

FFFh

BSR<3:0>

Instruction
Fetched

Opcode

12

4

8

File

12

FIGURE 5-9: INDIRECT ADDRESSING

Indirect Addressing

FSRnH:FSRnL

30

11 0

07

Location Select

Data
Memory

FSR

0000h

(1)

0FFFh

Note 1: For register file map detail, see Table5-1.

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5.13 Status Register

The St atus register , s hown in Register5-2, contains the
arithmetic status of the ALU. The Status register can be
the operand for any instruction as with any other regis­ter. I f the S tatus re gister is the des tination for an instruc­tion that affects the Z, DC, C, OV or N bits, then the
write to these five bit s is dis abled . These b its are set or
cleared according to the device logic. Therefore, the
result of an instruction with the Status register as
destination may be different than intended.

REGISTER 5-2: STATUS REGISTER

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDCC

bit 7 bit 0

bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).

1 = Result was negative
0 = Result was positive

bit 3 OV: Overf low bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions.

1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

Note: For borrow,

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.

bit 0 C: Carry/borrow bit

For ADDWF, ADDLW, SUBLW and SUBWF instructions.

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow,

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.

bit

the polarity is reversed. A subtraction is executed by adding the two’s

the polarity is reversed. A subtraction is executed by adding the two’s

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the Status register
as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the Status register, because these instructions do
not affect the Z, C, DC, OV or N bits in the Status reg­ister . For other instruct ions not af fecting any st atus bits ,
see Table24-2.

Note: The C and DC bits operate as a borrow

and digit borrow bit respectively, in
subtraction.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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5.14 RCON Register

The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO
BOR

and RI bits. This re gister is reada ble and w ritabl e.

REGISTER 5-3: RCON REGISTER

R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0

IPEN

bit 7 bit 0

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6-5 Unimplemented: Read as ‘0’
bit 4 RI

bit 3 TO

bit 2 PD

bit 1 POR

bit 0 BOR

: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET in struction was exe cuted causi ng a devic e Reset (mu st be set i n software aft er

a Brown-out Reset occurs)

: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-down Detection Flag bit

1 = Set by power-up or by the CLRWDT instruction
0 = Cleared by execution of the SLEEP instruction

: Power-on Reset Status bit

1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

, PD, POR,

— —RITO PD POR BOR

Note 1: If the BOREN configuration bit is set

(Brown-out Reset enabled), the BOR
is ‘1’ on a Power-on Reset. After a Bro wn­out Reset has occurred, the BOR bit will
be cleared and mu st be set by firmware to
indicate the occurrence of the next
Brown-out Reset.

2: It is recommended that the PO R

after a Power-on Reset has been
detected so that subsequent Power-on
Resets may be detected.

bit

bit be set

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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NOTES:

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6.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and
erasable during normal operation over the entire V
range.

A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 byt es at a time. Program mem ory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.

While writing or erasing program memory, instruction
fetches cease until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.

A value written to progra m memory does not nee d to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.

6.1 Table Reads and Table Writes

In order to read and write program memory, there are
two operati ons that all ow the pro cess o r to m ove by tes
between the program memory space and the data
RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

DD

The program memory space is 16 bits wide while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).

Table read operations retrieve data from program
memory and place it into TABLAT in the data RAM
space. Figure 6-1 shows the operation of a table read
with program memory and data RAM.

Table write operations store data from TABLAT in the
data memory space into holding registers in program
memory. The procedure to write the contents of the
holding registers into program memory is detailed in
Section 6.5 “Writing to Flash Program Memory”.
Figure 6-2 shows the operation of a table write with
program memory and data RAM.

Table operations work with byte entities. A table block
containing d ata, rather than prog ram instruct ions, is n ot
required to be word aligned. Therefore, a table block
can start and en d at any byte ad dress. If a table wr ite is
being used to write executable code into program
memory, program instructions will need to be word
aligned (TBLPTRL<0> = 0).

The EEPROM on-chip timer controls the write and
erase times. The write and erase voltages are gener­ated by an on-chip charge pump rated to operate over
the voltage range of the device for byte or word
operations.

FIGURE 6-1: TABLE READ OPERATION

Table Pointer

TBLPTRU

Note 1: Table Pointer points to a byte in program memory.

TBLPTRH TBLPTRL

(1)

Program Memory
(TBLPTR)

Instruction: TBLRD*

Program Memory

Table Latch (8-bit)

TABLAT

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FIGURE 6-2: TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Table Pointer

TBLPTRU

Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by

TBLPTRH TBLPTRL

TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in

Section 6.5 “Writing to Flash Program Memory”.

(1)

Program Memory
(TBLPTR)

Holding Registers

Table Latch (8-bit)

TABLAT

6.2 Control Registers

Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

6.2.1 EECON1 AND EECO N2 REGISTERS

EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.

Control bit, EEPGD, determines if the a cces s wil l be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, pr ogram memory is accessed.

Control bit, CFGS, determines if the access will be to
the configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.

The FREE bit controls program memory erase opera­tions. When the FREE bit is set, the erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.

The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled – the WR bit can not be set while the W REN bit
is clear . Thi s process helps to preve nt accident al w rites
to memory due to errant (unexpected) code execution.

Firmware should keep the WREN bit clear at all times
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.

The WRERR bit is set when a write operation is inter­rupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location . It will be
necessary to reload the data and address registers
(EEDA T A and EEADR) as these registers hav e cleared
as a result of the Reset.

Control bits, RD and WR, start read and erase/write
operations, respec tively. These bi ts are set by fi rmware
and cleared by hardware at the completion of the
operation.

The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instruc tions. See Section 6.3 “Reading the

Flash Program Memory” regarding table reads.

Note: Interrupt flag bit, EEIF in the PIR2 regi ster,

is set when the write is complete. It must
be cleared in software.

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REGISTER 6-1: EECON1 REGISTER

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access program Flash memory
0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EE or Configuration Select bit

1 = Access configuration registers
0 = Access program Flash or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation – TBLPTR<5:0> are ignored)

0 = Perform write only

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation was prematurely terminated (any Reset during self-timed programming)
0 = The write operation completed normally

Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows

tracing of the error condition.

bit 2 WREN: Write Enable bit

1 = Allows erase or write cycles
0 = Inhibits erase or write cycles

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write

cycle. (The operation is self-timed and the bit is cleared by hardware once write is
complete. The WR bit can only be set (not cleared) in software.)

0 = Write cycle completed

bit 0 RD: Read Control bit

1 = Initiates a memory read (Read t akes o ne c ycle. RD is cle ared i n hard ware. The RD b it ca n

only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Read completed

Legend:

R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’ W = Writable bit

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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6.2.2 TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.

6.2.3 TBLPTR – TABLE POINTER REGISTER

The Table Poi nte r (TBLPTR) register addresses a by te
within the program memory. The TBLPTR is comprised
of three SFR registers : Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis­ters join to form a 22-bit wide pointer. The low order
21 bits allow the device to address up to 2 Mbytes of
program memory space. Setting the 22nd bit allows
access to the device ID, the user ID and the
configuration bit s.

The table pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways based on the table opera­tion. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low order
21 bits.

6.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the
Flash program memory.

When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program or
configuration memory into TABLAT.

When a TBLWT is executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the TBLPTR (TBLPT R<21:3>) will deter­mine which program memory block of 8 bytes is written
to (TBLPTR<2:0> are ignored). For more detail, see
Section 6.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the
16 MSbs of the T able Poi nter (TBLPT R<21:6>) p oint to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.

Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.

TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Example Operation on Table Pointer

TBLRD*
TBLWT*

TBLRD*+
TBLWT*+

TBLRD*­TBLWT*-

TBLRD+*
TBLWT+*

TBLPTR is not modified

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

21 16 15 87 0

TBLPTRU

ERASE – TBLPTR<21:6>

TBLPTRH

LONG WRITE – TBLPTR<21:3>

TBLPTRL

READ or WRITE – TBLPTR<21:0>

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6.3 Reading the Flash Program Memory

The TBLRD instruction is used to retrieve data from
program memory and place it into data RAM. Table

The internal program memory is typically organize d by
words. The Least Significant b it of th e address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.

reads from program memory are pe rformed one by te at
a time.

TBLPTR points to a byte address in program space.
Executing a TBLRD instruction places the byte pointed
to into TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.

FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY

Program Memory

Odd (High) Byte

Even (Low) Byte

TBLPTR

LSB = 1

Instruction Register

(IR)

EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment TBLPTR
MOVFW TABLAT ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment TBLPTR
MOVFW TABLAT ; get data
MOVWF WORD_ODD

TBLPTR
LSB = 0

TABLAT

Read Register

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6.4 Erasing Flash Program Memory

The minimum erase block size is 32 words or 64 bytes
under firmware control. Only through the use of an
external programmer, or through ICSP control, can
larger blocks of program memory be bulk eras ed. Word
erase in Flash memory is not supported.

When initiating an erase sequence from the micro­controller itself, a blo ck of 64 bytes of program memo ry
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased;
TBLPTR<5:0> are ignored.

The EECON1 register comma nds the erase operation.
The EEPGD bit must be set to point to the Flash pro­gram memory. The CFGS bit must be clear to access
program Flash and data EEPROM memory. The
WREN bit must be set to enable write operations. The
FREE bit is set to select an erase operation. The WR
bit is set as part of the required instruction sequence
(as shown in Example 6-2) and starts the actual erase
operation. It is not necessary to load the TABLAT
register with any data as it is ignored.

For protection, the write initiate sequence using
EECON2 must be used.

A long write is nec essa ry for erasin g the i nternal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.

6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE

The sequence of events for erasing a block of internal
program memory location is:

1. Load Table Pointer with address of row being

erased.

2. Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program
memory;

• clear the CFGS bit to access program
memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable interrupts.

4. Write 55h to EECON2.

5. Write AAh to EECON2.

6. Set the WR bit. This will begin the row erase
cycle.

7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).

8. Execute a NOP.

9. Re-enable interrupts.

EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW

ERASE_ROW

Required MOVLW AAh
Sequence MOVWF EECON2 ; write AAH

MOVWF TBLPTRL

BSF EECON1,EEPGD ; point to Flash program memory
BSF EECON1,WREN ; enable write to memory
BSF EECON1,FREE ; enable Row Erase operation
BCF INTCON,GIE ; disable interrupts
MOVLW 55h
MOVWF EECON2 ; write 55H

BSF EECON2,WR ; start erase (CPU stall)
NOP
BSF INTCON,GIE ; re-enable interrupts

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6.5 Writing to Flash Program Memory

The programming block size is 4 words or 8 bytes.
Word or byte programming is not supported.

Table writ es are us ed inte rnally to load th e holdi ng reg­isters needed to program the Flas h memory. There are
8 holding registers used by the table writes for
programming.

Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essenti ally be short wr ites becaus e only
the holding registers are w ritte n. At the end of upda ting
8 registers, the EECON1 register must be w ritten to, to
start the programming operation with a long write.

The long write is necessary for programming the inter­nal Flash. Instruc tion exe cution is halted w hile in a long
write cycle. The long write will be terminated by the
internal programming timer.

FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT

Write Register

8 8 8

TBLPTR = xxxxx2

Holding Register

TBLPTR = xxxxx0

Holding Register

8

TBLPTR = xxxxx1

Holding Register

TBLPTR = xxxxx7

Holding Register

Program Memory

6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE

The sequence of events for programming an internal
program memory location should be:

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer with address being erased.

4. Do the row erase procedure (see Section 6.4.1

“Flash Program Memory Erase Sequence”).

5. Load Table Pointer with address of first byte

being written.

6. Write the first 8 bytes into the holding registers

with auto-increment.

7. Set the EECON1 register for the w rite operation:

• set EEPGD bit to point to program
memory;

• clear the CFGS bit to access program
memory;

• set WREN bit to enable byte writes.

8. Disable interrupts.

9. Write 55h to EECON2.

10. Write AAh to EECON2.
1 1. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for dura tion of t he write (about
2 ms using internal timer).

13. Execute a NOP.

14. Re-enable interrupts.

15. Repeat steps 6-14 seven times, to write 64
bytes.

16. Verify the memory (table read).

This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.

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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW D'64 ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW ; 6 LSB = 0
MOVWF TBLPTRL

READ_BLOCK

MODIFY_WORD

ERASE_BLOCK

WRITE_BUFFER_BACK

PROGRAM_LOOP

WRITE_WORD_TO_HREGS

TBLRD*+ ; read into TABLAT, and inc
MOVFW TABLAT ; get data
MOVWF POSTINC0 ; store data and increment FSR0
DECFSZ COUNTER ; done?
GOTO READ_BLOCK ; repeat

MOVLW DATA_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW DATA_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word and increment FSR0
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH ; update buffer word
MOVWF INDF0

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW ; 6 LSB = 0
MOVWF TBLPTRL
BCF EECON1,CFGS ; point to PROG/EEPROM memory
BSF EECON1,EEPGD ; point to Flash program memory
BSF EECON1,WREN ; enable write to memory
BSF EECON1,FREE ; enable Row Erase operation
BCF INTCON,GIE ; disable interrupts
MOVLW 55h ; Required sequence
MOVWF EECON2 ; write 55H
MOVLW AAh
MOVWF EECON2 ; write AAH
BSF EECON1,WR ; start erase (CPU stall)
NOP
BSF INTCON,GIE ; re-enable interrupts

MOVLW 8 ; number of write buffer groups of 8 bytes
MOVWF COUNTER_HI
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L

MOVLW 8 ; number of bytes in holding register
MOVWF COUNTER

MOVFW POSTINC0 ; get low byte of buffer data and increment FSR0
MOVWF TABLAT ; present data to table latch
TBLWT+* ; short write

; to internal TBLWT holding register, increment

TBLPTR
DECFSZ COUNTER ; loop until buffers are full
GOTO WRITE_WORD_TO_HREGS

DS39599C-page 78  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY

BCF INTCON,GIE ; disable interrupts
MOVLW 55h ; required sequence
MOVWF EECON2 ; write 55H
MOVLW AAh
MOVWF EECON2 ; write AAH
BSF EECON1,WR ; start program (CPU stall)
NOP
BSF INTCON,GIE ; re-enable interrupts
DECFSZ COUNTER_HI ; loop until done
GOTO PROGRAM_LOOP
BCF EECON1,WREN ; disable write to memory

6.5.2 WRITE VERIFY

Depending on the application, good programming
practice may dictate that the value written to the mem­ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.

6.6 Flash Program Operation During Code Protection

See Section 23.0 “Special Features of the CPU”
(Section 23.5 “Program Verification and Code Pro-
tection”) for details on code protection of Flash
program memory.

6.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION

If a write is termin ate d b y a n u npl anned event, such a s
loss of power or an unexpected Reset, the memory
location just pr ogrammed shou ld be verifi ed and rep ro­grammed if needed. The WRERR bit is set when a
write oper ation is interr upted by a MCLR

Reset, or a
WDT Time-out Reset, during normal operation. In
these situations, users can check the WRERR bit and
rewrite the location.

TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TBLPTRU

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000
TABLAT Program Memory Table Latch 0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL
EECON2 EEPROM Control Register 2 (not a physical register) — —
EECON1 EEPGD CFGS
IPR2 OSCFIP CMIP
PIR2 OSCFIF CMIF
PIE2 OSCFIE CMIE
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.

— — bit 21 Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

— FREE WRERR WREN WR RD xx-0 x000 uu-0 u000
— EEIP BCLIP LVDIP TMR3IP CCP2IP 11-1 1111 ---1 1111
— EEIF BCLIF LVDIF TMR3IF CCP2IF 00-0 0000 ---0 0000
— EEIE BCLIE LVDIE TMR3IE CCP2IE 00-0 0000 ---0 0000

Shaded cells are not used during Flash/EEPROM access.

Value on:

POR, BOR

--00 0000 --00 0000

Val ue on
all other

Resets

 2003 Microchip Technology Inc. DS39599C-page 79

PIC18F2220/2320/4220/4320

NOTES:

DS39599C-page 80  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

7.0 DATA EEPROM MEMORY

The data EEPROM is re adable and writ able durin g nor­mal operation over the entire V
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).

There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:

• EECON1

• EECON2

• EEDA TA

• EEADR
The EEPROM data memory allows byte read and write.

When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 00h to FFh.

The EEPROM data memory is rated for high erase/w rite
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write time
will vary with voltage and temperature, as well as from
chip to chip. Please refer to parameter D122 (Table 26-1
in Section 26.0 “Electrical Ch aracteristics”) for exact
limits.

7.1 EEADR

The address register can address 256 bytes of data
EEPROM.

7.2 EECON1 and EECON2 Registers

EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.

Control bit EEPGD determines if the access will be to
program or data EEPROM memory. When clear, oper­ations will access the data EEPROM memory. When
set, program memory is accessed.

DD range. The data

Control bit CFGS determines if the access will be to the
configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.

The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled; the WR bit ca nno t be s et whi le t he WREN b it
is clear. This mechanism helps to prevent accidental
writes to memory due to errant (unexpected) code
execution.

Firmware should keep the WREN bit clear at all times
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.

The WRERR bit is set when a write operation is inter­rupted by a Reset. In these situations, the user can
check the WRERR b it and rewrite the locati on. It is nec­essary to reload the data and address registers
(EEDATA and EEADR), as these registers have
cleared as a result of the Reset.

Control bits, RD and WR, start read and erase/write
operations, respec tively . These bits a re set by firmwa re
and cleared by hardware at the completion of the
operation.

The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “T able Read s

and Table Writes” regarding table reads.

Note: Interrupt flag bit, EEIF in the PIR2 regi ster,

is set when write is complete. It must be
cleared in software.

 2003 Microchip Technology Inc. DS39599C-page 81

PIC18F2220/2320/4220/4320

REGISTER 7-1: EECON1 REGISTER

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access program Flash memory
0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EE or Configuration Select bit

1 = Access configuration or calibration registers
0 = Access program Flash or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLP TR on the next WR comm and (cleared

by completion of erase operation)

0 = Perform write only

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation was prematurely terminated

or WDT Reset during self-timed erase or program operation)

(MCLR

0 = The write operation completed normally

Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows

tracing of the error condition.

bit 2 WREN: Erase/Write Enable bit

1 = Allows erase/write cycles
0 = Inhibits erase/write cycles

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memo ry erase cycle or write cycle.

(The operation is s elf -tim ed an d the bit is cleare d b y ha rdw are o nce w ri te is c om ple te. The
WR bit can only be set (not cleared) in software.)

0 = Write cycle is completed

bit 0 RD: Read Control bit

1 = Initiates a memory r ead (Read takes one c ycle. R D is c lea red i n h ard ware. Th e RD bit can

only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Read completed

Legend:

R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’ W = Writable bit

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39599C-page 82  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

7.3 Reading the Data EEPROM

Memory

T o read a d ata memory loca tion, the user must write the
address to the EEADR register, clear the EEPGD con­trol bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another re ad opera tion o r unt il it is writ ten to
by the user (during a write operation).

7.4 Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 7-2 must be followed to in itiate the write cycle.

The write will not begin if this sequence is not exactly
followed (write 55h to E ECON2, write AAh to EECON2,
then set WR bit) for each byte. It is strongly recom­mended that interrupts be disabled during this
code segment.

Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe­cution (i.e., runaway programs). The WREN bit should
be kept clear at all times except when updating the
EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc­tion. Both WR and WREN c an not be se t with th e s am e
instruction.

At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag b it
(EEIF) is set. The user may either enable this interrupt
or poll this bit. EEIF must be cleared by software.

7.5 Write Verify

Depending on the application, good programming
practice may dictate that the value written to the mem­ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.

7.6 Protection Against Spurious Write

There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-i n. On power-up, the WR EN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.

The write initiate sequence and the WREN bi t tog eth er
help prevent an accidental write during brown-out,
power glitch, or software malfunction.

EXAMPLE 7-1: DATA EEPROM READ

MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA

EXAMPLE 7-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts

MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW AAh ;

MOVWF EECON2 ; Write AAh

BSF EECON1, WR ; Set WR bit to begin write

BSF INTCON, GIE ; Enable Interrupts

SLEEP ; Wait for interrupt to signal write complete

BCF EECON1, WREN ; Disable writes

 2003 Microchip Technology Inc. DS39599C-page 83

PIC18F2220/2320/4220/4320

7.7 Operation During Code-Protect

Data EEPROM memory has its own code-protect bit s in
configuration words. External read and write opera­tions are disabled if either of these mechanisms are
enabled.

The microcontroller i tself can both re ad and wr ite to the
internal Data EEPROM regardless of the state of the
code-protect configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.

7.8 Using the Data EEPROM

The data EEPROM is a hi gh-endu rance, byte a ddress ­able array that has been optimized for the storage of
frequently changing information (e.g., program vari­ables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124 or D124A. If this is not the
case, an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.

A simple data EEPROM refresh routine is shown in
Example 7-3.

Note: If data EEPROM is only used to store

EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE

CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts

LOOP ; Loop to refresh array

BSF EECON1, WREN ; Enable writes

BSF EECON1, RD ; Read current address
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA Loop ; Not zero, do it again

constants an d/or data that change s rarel y,
an array refresh is likely not required. See
specification D124 or D124A.

BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts

TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE/GIEH PEIE/GIEL
EEADR EEPROM Address Registe r 0000 0000 0000 0000
EEDATA EEPROM Data Register 0000 0000 0000 0000
EECON2 EEPROM Control Register 2 (not a physical register) — —
EECON1 EEPGD CFGS
IPR2 OSCFIP CMIP
PIR2 OSCFIF CMIF
PIE2 OSCFIE CMIE
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.

Shaded cells are not used during Flash/EEPROM access.

DS39599C-page 84  2003 Microchip Technology Inc.

TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

— FREE WRERR WREN WR RD xx-0 x000 uu-0 u000
—EEIPBCLIP LVDIP TMR3IP CCP 2IP 11-1 1111 ---1 1111
—EEIFBCLIF LVDIF TMR3IF CCP2IF 00-0 0000 ---0 0000
—EEIEBCLIE LVDIE TMR3IE CCP 2IE 00-0 0000 ---0 0000

Value on:

POR, BOR

Value o n
all other

Resets

PIC18F2220/2320/4220/4320

8.0 8 X 8 HARDWARE MULTIPLIER

8.1 Introduction

An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F2X20/4X20 devi ces. By making the multipl y
a hardware o perati on, i t compl etes in a sing le in struc­tion cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PR ODH:PRODL). The m ultip lier d oes not
affect any flags in the Status register.

TABLE 8-1: PERFORMANCE COMPARISON

Program

Routine Multiply Method

8 x 8 unsigned

8 x 8 signed

16 x 16 unsigned

16 x 16 signed

Without hardware multiply 13 69 6.9 µs 27.6 µs 69 µs

Hardware multiply 1 1 100 ns 400 ns 1 µs

Without hardware multiply 33 91 9.1 µs 36.4 µs 91 µs

Hardware multiply 6 6 600 ns 2.4 µs6 µs

Without hardware multiply 21 242 24.2 µs 96.8 µs 242 µs

Hardware multiply 28 28 2.8 µs11.2 µs28 µs

Without hardware multiply 52 254 25.4 µs102.6 µs 254 µs

Hardware multiply 35 40 4.0 µs 16.0 µs 40 µs

Memory

(Words)

Making the 8 x 8 multiplier execute in a single-cycle
gives the following advantages:

• Higher computational throughput

• Reduces code size requirements for multiply
algorithms

The performance incre ase allows the device to be used
in applications previously reserved for Digital Signal
Processors.

Table 8-1 shows a performanc e comparison between
enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.

Cycles

(Max)

@ 40 MHz @ 10 MHz @ 4 MHz

Time

8.2 Operation

Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is al rea dy lo aded in
the WREG register.

Example 8-2 shows the sequence t o do an 8 x 8 signed
multiply. To account for the si gn bi ts of the ar gum ents,
each argumen t’s Most Signifi cant bit (MSb) is tested
and the appropriate subtractions are done.

EXAMPLE 8-1: 8 x 8 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH

; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

 2003 Microchip Technology Inc. DS39599C-page 85

PIC18F2220/2320/4220/4320

Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit re sult is st ored in four re gisters,
RES3:RES0.

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION
ALGORITHM

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2
(ARG1L • ARG2H • 2
(ARG1L • ARG2L)

16

) +

8

) +

8

) +

EXAMPLE 8-3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->

MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->

MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu­ments, each argum ent p ai rs’ M ost S ign ificant bit (MSb)
is tested and the appropriate subtractions are done.

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION
ALGORITHM

RES3:RES0

= ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2
(ARG1L • ARG2H ² 2

16

) +

8

) +

8

) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2

EXAMPLE 8-4: 16 x 16 SIGNED

MULTIPLY ROUTIN E

MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->

MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->

MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;

SUBWFB RES3
;
SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3
;
CONT_CODE
:

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

16

)

DS39599C-page 86  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

9.0 INTERRUPTS

The PIC18F2320/4320 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 000008h and the low prio rity interrupt vector
is at 000018h. High priority interrupt events will
interrupt any low priority interrupts that may be in
progress.

There are ten registers which are used to control
interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2
It is recommended that the Microchip header files

supplied with MPLAB
names in these registers. This allows the assembler/
compiler to automatical ly ta ke care of the pla ceme nt of
these bits within the specified register.

In general, each interrupt source has three bits to
control its operation. The functions of these bits are:

• Flag bit to indicate that an interrupt event
occurred

• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set

• Priority bit to select high priority or low priority
(most interrupt sources have priority bits)

The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally . Setti ng the GIEH bit (INTC ON<7>) enable s all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all inter­rupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt wi ll vec­tor immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual inter­rupts can be disabled through their corresponding
enable bits.

®

IDE be used for the symb olic bit

When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro
patibility mode, th e interrupt priority bits for each sourc e
have no effect. INTCON<6> is the PEIE bit which
enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.

When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interru pt priority
levels are used, this wi ll be either the GIEH or G IEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.

The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter­mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in s oftware be fore re-enab ling
interrupts to avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and set s the GIE bit (GIEH or GI EL
if priority levels are used) which re-enables interrupts.

For external interrupt events, such as the INT pins or
the PORTB input chang e interrupt, the i nterrupt latenc y
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.

Note: Do not use the MOVFF instruction to modify

any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.

®

mid-range device s. In Com-

 2003 Microchip Technology Inc. DS39599C-page 87

PIC18F2220/2320/4220/4320

FIGURE 9-1: INTERRUPT LOGIC

TMR0IF
TMR0IE
TMR0IP

RBIF
RBIE
RBIP

INT0IF
INT0IE

INT1IF
INT1IE

PSPIF
PSPIE
PSPIP

ADIF
ADIE
ADIP

RCIF
RCIE
RCIP

High Priority Interrupt Generation

Low Priority Interrupt Generation

PSPIF
PSPIE
PSPIP

ADIF
ADIE
ADIP

RCIF
RCIE
RCIP

Additional Peripheral Interrupts

Additional Peripheral Interrupts

TMR0IF
TMR0IE

TMR0IP

RBIF
RBIE

RBIP

INT0IF

INT0IE

INT1IF

INT1IE
INT1IP

INT2IF

INT2IE
INT2IP

IPE

INT1IP
INT2IF
INT2IE
INT2IP

IPEN

GIEL/PEIE

IPEN

Power Managed Mode

GIEH/GIE

GIEL\PEIE

Wake-up if in

Interrupt to CPU
Vector to Location
0008h

Interrupt to CPU
Vector to Location
0018h

DS39599C-page 88  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

9.1 INTCON Registers

The INTCON registers are readable and writable
registers which c ontai n various enable, priority a nd flag
bits.

REGISTER 9-1: INTCON REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN =

1 = Enables all unmasked interrupts
0 = Disables all interrupts

When IPEN =

1 = Enables all high priority interrupts
0 = Disables all high priority interrupts

bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN =

1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts

When IPEN =

1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cl eared in software)
0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state

Note: A mismatch condition will continue to set this bit. Reading PORTB will end the

0:

1:

0:

1:

mismatch condition and allow the bit to be cleared.

Note: Interrupt flag bits are set when an i nter rupt

condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS39599C-page 89

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REGISTER 9-2: INTCON2 REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1

RBPU

bit 7 bit 0

INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP

bit 7 RBPU

bit 6 INTEDG0: External Interrupt0 Edge Select bit

bit 5 INTEDG1: External Interrupt1 Edge Select bit

bit 4 INTEDG2: External Interrupt2 Edge Select bit

bit 3 Unimplemented: Read as ‘0’
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

bit 1 Unimplemented: Read as ‘0’
bit 0 RBIP: RB Port Change Interrupt Priority bit

: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = High priority
0 = Low priority

1 = High priority
0 = Low priority

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: In t err u pt f l ag bi ts a re s et wh en a n i nte r r upt co nd i tio n o cc ur s reg a r dl es s o f th e stat e

of its correspo nding en abl e bit or the globa l ena ble bi t. U ser so ftware s hould ensu re
the appropriate interrup t flag bits are clear prior to enab ling an interrupt. T his featu re
allows for software polling.

DS39599C-page 90  2003 Microchip Technology Inc.

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REGISTER 9-3: INTCON3 REGISTER

R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

INT2IP INT1IP

bit 7 bit 0

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority
0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 = High priority
0 = Low priority

bit 5 Unimplemented: Read as ‘0’
bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt

bit 2 Unimplemented: Read as ‘0’
bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur

—INT2IEINT1IE— INT2IF INT1IF

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: In t err u pt f l ag bi ts a re s et wh en a n i nte r r upt co nd i tio n o cc ur s reg a r dl es s o f th e stat e

of its correspo nding en abl e bit or the globa l ena ble bi t. U ser so ftware s hould ensu re
the appropriate interrup t flag bits are clear prior to enab ling an interrupt. T his featu re
allows for software polling.

 2003 Microchip Technology Inc. DS39599C-page 91

PIC18F2220/2320/4220/4320

9.2 PIR Registers

The PIR registers conta in the ind ividu al flag bi ts fo r the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag registers (PIR1, PIR2).

Note 1: Interrupt flag bits are set when an interrupt

condition occurs rega rdless of the st ate of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).

2: User software should ensure the ap propri-

ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.

REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

PSPIF

bit 7 bit 0

bit 7 PSPIF

bit 6 ADIF: A/D Converter Interrupt Flag bit

bit 5 RCIF: USART Receive Interrupt Flag bit

bit 4 TXIF: USART Transmit Interrupt Flag bit

bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit

bit 2 CCP1IF: CCP1 Interrupt Flag bit

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

(1)

1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred

Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit clear.

1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete

1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART receive buffer is empty

1 = The USART tr ansmit buffer, TXREG, is empty (cl eared when TXREG is written)
0 = The USART transmit buffer is full

1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive

Capture mode:

1 = A TMR1 re gister capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode:
Unused in this mode.

1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred

1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

: Parallel Slave Port Read/Write Interrupt Flag bit

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39599C-page 92  2003 Microchip Technology Inc.

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REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OSCFIF CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF

bit 7 bit 0

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, cl ock inp ut has change d to INT OSC ( must be clea red in softwa re)
0 = System clock operating

bit 6 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed

bit 5 Unimplemented: Read as ‘0’
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete, or has not been started

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision occurred (must be cleared in s oftware)
0 = No bus collision occurred

bit 2 LVDIF: Low-Volt a ge Detec t Interrupt Flag bit

1 = A low-voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low-Voltage Detect trip point

bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit

1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow

bit 0 CCP2IF: CCPx Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode:
Unused in this mode.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS39599C-page 93

PIC18F2220/2320/4220/4320

9.3 PIE Registers

The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph­eral interrupt sources, there are two Peripheral Inter­rupt Enable registe rs (PIE1, PIE2). Wh en IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.

REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

PSPIE

bit 7 bit 0

bit 7 PSPIE

bit 6 ADIE: A/D Converter Interrupt Enable bit

bit 5 RCIE: USART Receive Interrupt Enab le bit

bit 4 TXIE: USART Transmit Interrupt Enable bit

bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit

bit 2 CCP1IE: CCP1 Interrupt Enable bit

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

(1)

1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt

Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit clear.

1 = Enables the A/D interrupt
0 = Disables the A/D interrupt

1 = Enables the USART receive interrupt
0 = Disables the USART receiv e interrupt

1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt

1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

: Parallel Slave Port Read/Write Interrupt Enable bit

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39599C-page 94  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OSCFIE CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE

bit 7 bit 0

bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled
0 =Disabled

bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enabled
0 =Disabled

bit 5 Unimplemented: Read as ‘0’
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit

1 = Enabled
0 =Disabled

bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enabled
0 =Disabled

bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit

1 = Enabled
0 =Disabled

bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit

1 = Enabled
0 =Disabled

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enabled
0 =Disabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS39599C-page 95

PIC18F2220/2320/4220/4320

9.4 IPR Registers

The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of periph­eral interrupt sources, there are two Peripheral Inter­rupt Priority registers (IPR1, IPR2). Using the priority
bits requires that the In terrupt Priority Enabl e (IPEN) bit
be set.

REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

(1)

PSPIP

bit 7 bit 0

bit 7 PSPIP

bit 6 ADIP: A/D Converter Interrupt Priority bit

bit 5 RCIP: USART Receive Interrupt Priority bit

bit 4 TXIP: USART Transmit Interrupt Priority bit

bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit

bit 2 CCP1IP: CCP1 Interrupt Priority bit

bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit

(1)

1 =High priority
0 = Low priority

Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit set.

1 =High priority
0 = Low priority

1 =High priority
0 = Low priority

1 =High priority
0 = Low priority

1 =High priority
0 = Low priority

1 =High priority
0 = Low priority

1 =High priority
0 = Low priority

1 =High priority
0 = Low priority

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP

: Parallel Slave Port Read/Write Interrupt Priority bit

DS39599C-page 96  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2

R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

OSCFIP CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP

bit 7 bit 0

bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit

1 =High priority
0 = Low priority

bit 6 CMIP: Comparator Interrupt Priority bit

1 =High priority
0 = Low priority

bit 5 Unimplemented: Read as ‘0’
bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit

1 =High priority
0 = Low priority

bit 3 BCLIP: Bus Collision Interrupt Priority bit

1 =High priority
0 = Low priority

bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit

1 =High priority
0 = Low priority

bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit

1 =High priority
0 = Low priority

bit 0 CCP2IP: CCP2 Interrupt Priority bit

1 =High priority
0 = Low priority

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS39599C-page 97

PIC18F2220/2320/4220/4320

9.5 RCON Register

The RCON register cont ains bit s used to determine the
cause of the last Reset or wake-up from power man­aged mode. RCON also co ntains the bit that en ables
interrupt priorities (IPEN).

REGISTER 9-10: RCON REGISTER

R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0

IPEN

bit 7 bit 0

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6-5 Unimplemented: Read as ‘0’
bit 4 RI

bit 3 TO

bit 2 PD

bit 1 POR

bit 0 BOR

: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after

a Brown-out Reset occurs)

: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-Down Detection Flag bit

1 = Set by power-up or by the CLRWDT instruction
0 = Cleared by execution of the SLEEP instruction

: Power-on Reset Status bit

1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

— —RITO PD POR BOR

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39599C-page 98  2003 Microchip Technology Inc.