MICROCHIP PIC18F2220, PIC18F2320, PIC18F4220, PIC18F4320 DATA SHEET

PIC18F2220/2320/4220/4320

Data Sheet

28/40/44-Pin High-Performance,

Enhanced Flash Microcontrollers

with 10-Bit A/D and nanoWatt Technology

 2003 Microchip Technology Inc. DS39599C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, MPLAB, PIC, PICmic ro, PI C START,

PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartT el and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of develop m ent
systems is ISO 9001 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

DS39599C-page ii  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

28/40/44-Pin High-Performance, Enhance d Flash MCUs

with 10-bit A/D and nanoWatt Technology

Low-Power Features:

• Power Managed modes:

- Run: CP U on, peripherals on

- Idle: CPU off, peripherals on

- Sleep: CPU off, peripherals off

• Power Consumption modes:

- PRI_RUN: 150 µA, 1 MHz, 2V

- PRI_IDLE: 37 µA, 1 MHz, 2V

- SEC_RUN: 14 µA, 32 kHz, 2V

- SEC_IDLE: 5.8 µA, 32 kHz, 2V

- RC_RUN: 110 µA, 1 MHz, 2V

- RC_IDLE: 52 µA, 1 MHz, 2V

- Sleep: 0.1 µA, 1 MH z, 2V

• Timer1 Oscillator: 1.1 µA, 32 kHz, 2V

• Watchdog Timer: 2.1 µA

• Two-Speed Oscillator Start-up

Oscillators:

• Four Crystal modes:

- LP, XT, HS: up to 25 MHz

- HSPLL: 4-10 MHz (16-40 MHz internal)

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal oscillator block:

- 8 user selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz

- 125 kHz-8 MHz calibrated to 1%

- Two modes select one or two I/O pins

- OSCTUNE – Allows user to shift frequency

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor

- Allows for safe shutdown if peripheral clock stops

Peripheral Highlight s:

• High current sink/source 25 mA/25 mA

• Three external interrupts

• Up to 2 Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution is 6.25 ns (T

- Compare is 16-bit, max. resolution is 100 ns (T

- PWM output: PWM resolution is 1 to 10-bit

• Enhanced Capture/Compare/PWM (ECCP) module:

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead-time

- Auto-Shutdown and Auto-Restart

• Compatible 10-bit, up to 13-channel
Analog-to-Digital Converter module (A/D) with
programmable acqui sit ion time

• Dual analog comparators

• Addressable USART module:

- RS-232 operation using internal oscillator

block (no external crystal required)

CY/16)

CY)

Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced Flash program
memory typical

• 1,000,000 erase/write cycle Data EEPROM memo ry
typical

• Flash/Data EEPROM Retention: > 40 years

• Self-programmable under software control

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

- 2% stability over V

• Single-supply 5V In-Circuit Serial Programming™
(ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Wide operating voltage range: 2.0V to 5.5V

DD and Temperature

Program Memory Data Memory

Device

PIC18F2220 4096 2048 512 256 25 10 2/0 Y Y Y 2 2/3
PIC18F2320 8192 4096 512 256 25 10 2/0 Y Y Y 2 2/3
PIC18F4220 4096 2048 512 256 36 13 1/1 Y Y Y 2 2/3
PIC18F4320 8192 4096 512 256 36 13 1/1 Y Y Y 2 2/3

 2003 Microchip Technology Inc. DS39599C-page 1

Flash

(bytes)

# Single Word

Instructions

SRAM
(bytes)

EEPROM

(bytes)

I/O

10-bit

A/D (ch)

CCP/

ECCP

(PWM)

SPI™

MSSP

Master

USART

2

C™

I

Timers

8/16-bit

Comparators

PIC18F2220/2320/4220/4320

Pin Diagrams

PDIP

RA2/AN2/V

RA5/AN4/SS

SPDIP, SOIC

RA2/AN2/V

RA5/AN4/SS

MCLR/VPP/RE3

RA0/AN0
RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

/LVDIN/C2OUT

RE0/AN5/RD

RE1/AN6/WR

RE2/AN7/CS

VDD
VSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2*

RC2/CCP1/P1A

RC3/SCK/SCL

RD0/PSP0
RD1/PSP1

MCLR/VPP/RE3

RA0/AN0
RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

/LVDIN/C2OUT

V

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1/P1A

RC3/SCK/SCL

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7

SS

*

8
9

10
11

12
13
14

PIC18F4220

PIC18F2220

PIC18F4320

PIC18F2320

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7/KBI3/PGD
RB6/KBI2/PGC

RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2*
RB2/AN8/INT2

RB1/AN10/INT1
RB0/AN12/INT0
V

DD

VSS
RD7/PSP7/P1D
RD6/PSP6/P1C

RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2

RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2
RB2/AN8/INT2
RB1/AN10/INT1
RB0/AN12/INT0
V

DD

VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

*

* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 40-pin PIC16C7X devices.

DS39599C-page 2  2003 Microchip Technology Inc.

Pin Diagrams (Cont.’d)

TQFP

PIC18F2220/2320/4220/4320

*

RC7/RX/DT

RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

RB0/AN12/INT0
RB1/AN10/INT1

RB2/AN8/INT2

RB3/AN9/CCP2*

V
VDD

SS

1
2
3
4
5
6
7
8
9
10
11

* RB3 is the alternate pin for the CCP2 pin multiplexing.

QFN

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

4443424140

PIC18F4220
PIC18F4320

121314

15

16

NC

NC

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/AN11/KBI0

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

38

39

37

1819202122

17

RA0/AN0

/VPP/RE3

RB7/KBI3/PGD

MCLR

RC2/CCP1/P1A

363435

RA1/AN1

RC1/T1OSI/CCP2

REF-/CVREF

RA2/AN2/V

NC

33
32
31
30
29
28
27
26
25
24

23

RA3/AN3/VREF+

NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7

SS

V
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN/C2OUT
RA4/T0CKI/C1OUT

*

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

RC0/T1OSO/T1CKI

RC7/RX/DT

RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

RB0/AN12/INT0
RB1/AN10/INT1

RB2/AN8/INT2

V
VDD
VDD

4443424140

1
2
3
4

PIC18F4220

SS

5
6

PIC18F4320

7
8
9
10
11

121314

NC

RB3/AN9/CCP2*

39

363435

37

38

16

17

1819202122

15

/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/AN11/KBI0

MCLR

33
32
31
30
29
28
27
26
25
24

23

REF+

RA1/AN1

RA0/AN0

REF-/CVREF

RA3/AN3/V

RA2/AN2/V

OSC2/CLKO/RA6
OSC1/CLKI/RA7

SS

V
VSS
VDD
NC
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN/C2OUT
RA4/T0CKI/C1OUT

* RB3 is the alternate pin for the CCP2 pin multiplexing.

 2003 Microchip Technology Inc. DS39599C-page 3

PIC18F2220/2320/4220/4320

Table of Contents

1.0 Device Overview..........................................................................................................................................................................7

2.0 Oscillator Configurations............................................................................................................................................................ 19

3.0 Power Managed Modes ......................................................................... .. .. .. ..... .... .. .. .. .. .. .. ......................................................... 29

4.0 Reset..........................................................................................................................................................................................43

5.0 Memory Organization................................................................................................................................................................. 53

6.0 Flash Program Memory............... .......................... ......................... ......................... ................................................................... 71

7.0 Data EEPROM Memory....................... ............ .......................... ......................... .......................................................................81

8.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 85

9.0 Interrupts....................................................................................................................................................................................87

10.0 I/O Ports........................ ......................... ............ .......................... ............ ............... ................................................................. 101

11.0 Timer0 Module ......................................................................................................................................................................... 117

12.0 Timer1 Module ......................................................................................................................................................................... 121

13.0 Timer2 Module ......................................................................................................................................................................... 127

14.0 Timer3 Module ......................................................................................................................................................................... 129

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 133

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................141

17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 155

18.0 Addressable Universal Synchronous Asynchronous Receiv er Transmitter (USA RT )..............................................................195

19.0 10-bit Analog-to-Digital Converter (A/D) Module......................................................................................................................211

20.0 Comparator Module............................................................................................. .... .. .... ...........................................................221

21.0 Comparator Voltage Reference Module.................................................................. .... .. .... ....... .. .............................................. 227

22.0 Low-Voltage Detect.................................................................................................................................................................. 231

23.0 Special Features of the CPU................................................................ ....................................................................................237

24.0 Instruction Set Summary.......................................................................................................................................................... 255

25.0 Development Support. .............................................................................................................................................................. 299

26.0 Electrical Characteristics..........................................................................................................................................................305

27.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................343

28.0 Packaging Information.............................. ......................... ...................................... ................................................................. 361

Appendix A: Revision History.............................................................................................................................................................369

Appendix B: Device Differences......................................................................................................................................................... 369

Appendix C: Conversion Considerations ........................................................................................................................................... 370

Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 370

Appendix E: Migration from Mid-Range to Enhanced Devices ..........................................................................................................371

Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 371

Index ..................................................................................................................................................................................................373

On-Line Support........................................................................ .... .. ......... .... .. .... .... ....... .... ................................................................. 383

Systems Information and Upgrade Hot Line...................................................................................................................................... 383

Reader Response..............................................................................................................................................................................384

PIC18F2220/2320/4220/4320 Product Identification System ............................................................................................................385

DS39599C-page 4  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone].
We welcome your feedback.

Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.

 2003 Microchip Technology Inc. DS39599C-page 5

PIC18F2220/2320/4220/4320

NOTES:

DS39599C-page 6  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:

• PIC18F2220 • PIC18F4220

• PIC18F2320 • PIC18F4320

This family offers the advantages of all PIC18 micro­controllers – namely, high computational performance
at an economical price with the addition of high­endurance Enhanced Flash program memory. On top
of these features, the PIC18F2220/2320/4220/4320
family introduces design enhancements that make
these microcontrollers a logical choice for many
high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2220/2320/4220/4320
family incorporate a range of features that can signifi­cantly reduce power consumption during operation.
Key items include:

• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run
with its CPU c ore disable d, but the pe ripherals are
still active. In these states, power consumption can
be reduced even further, to as little as 4% of normal
operation requirements.

• On-the-fly Mode Switching: The power managed
modes are invoked by user code during operation,
allowing th e user to inco rpor ate po wer sav ing id eas
into their application’s software design.

• Lower Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer have been reduced by up to 80%, with typical
values of 1.8 and 2.2 µA, respectively.

1.1.2 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F2220/2320/4220/4320
family offer nine different oscillator options, allowing
users a wide ran ge of choice s in develo ping applic ation
hardware. These include:

• Four Crystal modes using crystals or ceramic
resonators.

• Two External Clock modes offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input with the
second pin reassigned as general I/O).

• Two External RC Oscillator modes with the same
pin options as the External Clock modes.

• An internal oscillator block, which provides a 31 kHz
INTRC clock and an 8 MHz clock with 6 program
selectable divider ratios (4 MHz to 125 kHz) for a
total of 8 clock frequencies.

Besides its ava ilability as a cloc k source, the intern al
oscillator block pro vid es a s t ab le re fere nce source that
gives the family additional features for robust
operation:

• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator block, allowing for continued
low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the internal
oscillator to serve as the clock source from Power-on
Reset, or wake-up from Sleep mode, until the primary
clock source is available. This allows for code execu­tion during what would otherwise be the clock start-up
interval and can even allow an application to perform
routine background activities and return to Sleep
without returning to full power operation.

1.2 Other Special Features

• Memory Endurance: The Enhanced Flash cells for
both program memory and data EEPROM are rated
to last for many thousands of erase/write cycles – up
to 100,000 for program memory and 1,000,000 for
EEPROM. Data retention without refresh is

conservatively estimated to be greater than 40 years.

• Self-programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Block at the top of pro­gram memory, it becomes possible to create an
application that can update itself in the field.

• Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers. Other
features include Auto-Shutdown for disabling PWM
outputs on interrupt or other select conditions and
Auto-Restart to reactivate outputs once the
condition has cleared.

• Addressable USART: This serial communication
module is capable of standard RS-232 operation
using the internal oscillator block, removing the
need for an external crystal (and its accompanying
power requirement) in applications that talk to the
outside world.

• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a chan­nel to be sel ected and a convers ion to be initiated
without waiting for a sampling period and thus,
reduce code overhead.

• Extended Watchdog Timer (WDT): This enhanced
version incorporates a 16-bit prescaler, allowing a
time-out ra nge from 4 ms to over 2 mi nutes, that is
stable across operating voltage and temperature.

 2003 Microchip Technology Inc. DS39599C-page 7

PIC18F2220/2320/4220/4320

1.3 Details on Individual Family Members

Devices in the PIC18F 2220/2320/42 20/4320 famil y are
available in 28-pin (PIC18F2X20) and 40/44-pin
(PIC18F4X20) packages. Block diagrams for the two
groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in five
ways:

1. Flash program memory (4 Kbytes for

PIC18FX220 devices, 8 Kbytes for PIC18FX320)

2. A/D channels (10 for PIC18F2X20 devices, 13 for

PIC18F4X20 devices)

3. I/O ports (3 bidirectional ports and 1 input only
port on PIC18F2X20 devices, 5 bidirectional
ports on PIC18F4X20 devices)

4. CCP and Enhanced CCP implementation
(PIC18F2X20 devices have 2 standard CCP
modules, PIC18F4X20 devices have one
standard CCP module and one ECCP module)

5. Parallel Slave Port (present only on
PIC18F4X20 devices)

All other features fo r device s in this family are identi cal.
These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and
Table 1-3.

TABLE 1-1: DEVICE FEATURES

Features PIC18F2220 PIC18F2320 PIC18F4220 PIC18F4320

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 4096 8192 4096 8192
Program Memory (Instruction s) 2048 4096 20 48 4096
Data Memory (Bytes) 512 512 512 512
Data EEPROM Memory (Bytes) 256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C (E) Ports A, B, C (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 2 2 1 1
Enhanced Capture/

Compare/PWM Modules
Serial Communications MSSP,

Parallel Communications (PSP) No No Yes Yes
10-bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Resets (and Delays) POR, BOR,

RESET Instruction,

MCLR

Programmable Low-Voltage
Detect

Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions 75 Instr uctions 75 Instructions 75 Instructions
Packages 28-pin SPDIP

0011

MSSP,

Addressable

USART

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

WDT

Yes Yes Yes Yes

28-pin SOIC

Addressable

USART

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

28-pin SPDIP

28-pin SOIC

MSSP,

Addressable

USART

POR, BOR,

RESET Instruction,

Stack Full,

Stac k U nde rflo w

(PWRT, OST),

(optional),

MCLR

WDT

40-pin PDIP

44-pin TQFP

44-pin QFN

MSSP,

Addressable

USART

POR, BOR,

RESET Instruction,

Stack Full,

Stac k U nde rflo w

(PWRT, OST),

(optional),

MCLR

WDT

40-pin PDIP

44-pin TQFP

44-pin QFN

DS39599C-page 8  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

FIGURE 1-1: PIC18F2220/2320 BLOCK DIAGRAM

Data Bus<8>

21

Address Latch

Program Memory

(4 Kbytes)

Data Latch

16

(3)

OSC1

(3)

OSC2

T1OSI

T1OSO

(2)

MCLR

VDD, VSS

21

Table Pointer <2>

21

inc/dec logic

Table Latch

8

Instruction

Decode &

Control

Internal

Oscillator

Block

INT RC

Oscillator

Low-Voltage

Programming

In-Circuit
Debugger

20

8

PCLATH

PCLATU

PCU

PCH PCL

Program Counter

31 Level Stack

ROM Latch

Instruction
Register

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Clock Monitor

8

8

8

4
BSR

Decode

BIT OP

Precision

Voltage

Reference

Data RAM
(512 Bytes)

Address Latch

Address<12>

12 4

FSR0
FSR1
FSR2

inc/dec

3

8

8

Data Latch

12

Bank0, F

logic

PRODLPRODH

8 x 8 Multiply

WREG

8

ALU<8>

8

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT

(2)

PORTB

12

PORTC

8

8

8

PORTE

RA5/AN4/SS
OSC2/CLKO/RA6
OSC1/CLKI/RA7

RB0/AN12/INT0
RB1/AN10/INT1

RB2/AN8/INT2
RB3/AN9/CCP2
RB4/AN11/KBI0
RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1/P1A

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RE3

(2)

/LVDIN/C2OUT

(3)

(3)

(1)

(1)

Timer0

(8- or 16-bit)

CCP1

Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCPMX2 configuration bit.

2: RE3 is available only when the MCLR
3: OSC1, OSC2, CLKI and CLKO are only ava ilable in select o scillator modes and when th ese pins are not being use d as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

Timer1
(16-bit)

CCP2

Timer2

(8-bit)

Master

Synchronous

Serial Port

Resets are disabled.

Timer3
(16-bit)

Addressable

USART

10-bit A/D
Converter

Data EEPROM

(256 Bytes)

 2003 Microchip Technology Inc. DS39599C-page 9

PIC18F2220/2320/4220/4320

FIGURE 1-2: PIC18F4220/4320 BLOCK DIAGRAM

Data Bus<8>

21

Address Latch

Program Memory

(8 Kbytes)

Data Latch

16

(3)

OSC1

(3)

OSC2

T1OSI

T1OSO

(2)

MCLR

DD, VSS

V

21

Table Pointer <2>

21

inc/dec logic

Table Latch

8

Instruction

Decode &

Control

Internal

Oscillator

Block

INT RC

Oscillator

Low-Voltage

Programming

In-Circuit
Debugger

20

8

PCLATU

PCLATH

PCU

PCH PCL

Program Counter

31 Level Stack

ROM Latch

Instruction
Register

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Clock Monitor

Data Latch

8

8

8

4
BSR

Decode

BIT OP

Precision

Voltage

Reference

Data RAM

(512 Bytes)

Address Latch

Address<12>

12 4

FSR0
FSR1
FSR2

inc/dec

3

WREG

8

8

(2)

12

Bank0, F

logic

PRODLPRODH

8 x 8 Multiply

8

ALU<8>

8

12

8

PORTA

PORTB

PORTC

PORTD

8

8

PORTE

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
OSC2/CLKO/RA6
OSC1/CLKI/RA7

RB0/AN12/INT0

RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC

RB7/KBI3/PGD

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1/P1A

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D

RE0/AN5/RD
RE1/AN6/WR

RE2/AN7/CS
RE3

(2)

/LVDIN/C2OUT

(3)

(3)

(1)

(1)

Timer0

(8- or 16-bit)

Enhanced

CCP

Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCP2MX configuration bit.

2: RE3 is available only when the MCLR
3: OSC1, OSC2, CLKI and CL KO are only av ailable in se lect oscillator modes and when th ese pins a re not being us ed as digital I /O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

Timer1 Timer2
(16-bit) (8-bit)

Master

CCP2

Synchronous

Serial Por t

Resets are disabled.

Timer3
(16-bit)

Addressable

USART

10-bit A/D
Converter

Data EEPROM

(256 Bytes)

DS39599C-page 10  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

T ABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

PDIP SOIC

Pin

Type

Buffer

Type

Description

/VPP/RE3

MCLR

MCLR
VPP

RE3

OSC1/CLKI/RA7

OSC1
CLKI
RA7

OSC2/CLKO/RA6

OSC2
CLKO
RA6

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
VREF­CV

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI/C1OUT

RA4
T0CKI
C1OUT

RA5/AN4/SS

RA5
AN4
SS
LVDIN

C2OUT
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.

REF-/CVREF

REF

REF+

REF+

/LVDIN/C2O UT

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

2: Alternate assignment for CCP2 when CCP2MX is cleared.

11

99

10 10

22

33

44

55

66

77

I

ST

P

I

ST

I

ST

I

CMOS

I/O

TTL

O
O

I/O

I/OITTL

I/OITTL

I/O

O

I/O

I/O

O

I/O

O

I
I

I
I

I

I
I
I

DD)

—
—

TTL

Analog

Analog

TTL
Analog
Analog
Analog

TTL
Analog
Analog

ST/OD

ST

—

TTL
Analog

TTL
Analog

—

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low Reset
to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
Comparator Reference Voltage output.

Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.

Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.

Digital I/O.
Analog input 4.
SPI Slave Select input.
Low-Voltage Detect input.
Comparator 2 output.

 2003 Microchip Technology Inc. DS39599C-page 11

PIC18F2220/2320/4220/4320

TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/AN12/INT0

RB0
AN12
INT0

RB1/AN10/INT1

RB1
AN10
INT1

RB2/AN8/INT2

RB2
AN8
INT2

RB3/AN9/CCP2

RB3
AN9

(1)

CCP2

RB4/AN11/KBI0

RB4
AN11
KBI0

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 wh en CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number
PDIP SOIC

21 21

22 22

23 23

24 24

25 25

26 26

27 27

28 28

Pin

Type

I/O

I
I

I/O

I
I

I/O

I
I

I/O

I

I/O

I/O

I
I

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

DD)

Buffer

Type

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all i nputs.

Digital I/O.
Analog input 12.
External interrupt 0.

Digital I/O.
Analog input 10.
External interrupt 1.

Digital I/O.
Analog input 8.
External interrupt 2.

Digital I/O.
Analog input 9.
Capture2 input, Compare2 output, PWM2 output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
Low-voltage ICSP programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programmi ng cl ock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programmi ng data pin.

DS39599C-page 12  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

T ABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(2)

CCP2

RC2/CCP1/P1A

RC2
CCP1
P1A

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX

DT
RE3 — — — — See MCLR
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP SOIC

11 11

12 12

13 13

14 14

15 15

16 16

17 17

18 18

Pin

Buffer

Type

Type

I/O

O

I

I/O

I

CMOS

I/O

I/O
I/O

O

I/O
I/O
I/O

I/O

I

I/O

I/OOST

I/O

O

I/O

I/O

I

I/O

DD)

PORTC is a bidirectional I/O port.

ST

—

ST

ST
ST

ST
ST

—

ST
ST
ST

ST
ST
ST

—

ST

—

ST

ST
ST
ST

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
Enhanced CCP1 output.

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
SPI data in.

2

C data I/O.

I

Digital I/O.
SPI data out.

Digital I/O.
USART asynchronous transmit.
USART synchronous clock (see related RX/DT).

Digital I/O.
USART asynchronous receive.
USART synchronous data (see related TX/CK).

/VPP/RE3 pin.

Description

2

C mode.

 2003 Microchip Technology Inc. DS39599C-page 13

PIC18F2220/2320/4220/4320

TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

PDIP TQFP QFN

Pin

Type

Buffer

Type

Description

/VPP/RE3

MCLR

MCLR
VPP

RE3

OSC1/CLKI/RA7

OSC1
CLKI

RA7

OSC2/CLKO/RA6

OSC2
CLKO
RA6

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI/C1OUT

RA5/AN4/SS/LVDIN/
C2OUT

RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

Note 1: Default assignment for CCP2 wh en CCP2MX (CONFIG3H<0>) is set.

REF-/CVREF

RA2
AN2
V

REF-

CV

REF

REF+

RA3
AN3
V

REF+

RA4
T0CKI
C1OUT

RA5
AN4
SS
LVDIN
C2OUT

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

2: Alternate assignment for CCP2 when CCP2MX is cleared.

11818

13 30 32

14 31 33

21919

32020

42121

52222

62323

72424

I

P

I

I
I

CMOS

I/O

O
O

I/O

I/OITTL

Analog

I/OITTL

Analog

I/O

Analog

I

Analog

I

Analog

O

I/O

I

Analog

I

Analog

I/O

ST/OD

I

O

I/O

Analog

I
I

Analog

I

O

DD)

Master Clear (input) or programming voltage (input).

ST

ST

ST

TTL

—
—

TTL

TTL

TTL

ST

—

TTL
TTL

—

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage inpu t.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External cl ock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator reference voltage output.

Digital I/O.
Analog input 3.
A/D reference voltage (High) input.

Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.

Digital I/O.
Analog input 4.
SPI slave select input.
Low-Voltage Detect input.
Comparator 2 output.

DS39599C-page 14  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

T ABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/AN12/INT0

RB0

AN12

INT0
RB1/AN10/INT1

RB1

AN10

INT1
RB2/AN8/INT2

RB2

AN8

INT2
RB3/AN9/CCP2

RB3

AN9

(1)

CCP2
RB4/AN11/KBI0

RB4

AN11

KBI0
RB5/KBI1/PGM

RB5

KBI1

PGM
RB6/KBI2/PGC

RB6

KBI2

PGC
RB7/KBI3/PGD

RB7

KBI3

PGD
Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP TQFP QFN

33 8 9

34 9 10

35 10 11

36 11 12

37 14 14

38 15 15

39 16 16

40 17 17

Pin

Type

I/O

I
I

I/O

I
I

I/O

I
I

I/O

I

I/O

I/O

I
I

I/O

I

I/O

I/O

I

I/O

I/O

I

I/O

DD)

Buffer

Type

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

ST

TTL

Analog

TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.
Analog input 12.
External interrupt 0.

Digital I/O.
Analog input 10.
External interrupt 1.

Digital I/O.
Analog input 8.
External interrupt 2.

Digital I/O.
Analog input 9.
Capture2 input, Compare2 output, PWM2 output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
Low-voltage ICSP programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

 2003 Microchip Technology Inc. DS39599C-page 15

PIC18F2220/2320/4220/4320

TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(2)

CCP2

RC2/CCP1/P1A

RC2
CCP1
P1A

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 wh en CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP TQFP QFN

15 32 34

16 35 35

17 36 36

18 37 37

23 42 42

24 43 43

25 44 44

26 1 1

Pin

Type

I/O

O

I

I/O

I

I/O

I/O
I/O

O

I/O
I/O
I/O

I/O

I

I/O

I/OOST

I/O

O

I/O

I/O

I

I/O

DD)

Buffer

Type

ST

—

ST

ST

CMOS

ST

ST
ST

—

ST
ST
ST

ST
ST
ST

—

ST

—

ST

ST
ST
ST

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
Enhanced CCP1 output.

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchron ous serial clock input/o utput for I

Digital I/O.
SPI data in.

2

C data I/O.

I

Digital I/O.
SPI data out.

Digital I/O.
USART asynchronous trans m it.
USART synchronous clock (see related RX/DT).

Digital I/O.
USART asynchronous receive.
USART synchronous data (see related TX/CK).

2

C mode.

DS39599C-page 16  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

T ABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/PSP0

RD0

PSP0
RD1/PSP1

RD1

PSP1
RD2/PSP2

RD2

PSP2
RD3/PSP3

RD3

PSP3
RD4/PSP4

RD4

PSP4
RD5/PSP5/P1B

RD5

PSP5

P1B
RD6/PSP6/P1C

RD6

PSP6

P1C
RD7/PSP7/P1D

RD7

PSP7

P1D
Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP TQFP QFN

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Pin

Buffer

Type

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/O

O

I/O
I/O

O

I/O
I/O

O

DD)

Type

PORTD is a bidirectional I/O port or a Parallel Slave Port
(PSP) for interfacing to a microprocessor port. These pins
have TTL input buffers when PSP module is enabled.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

ST

TTL

—

ST

TTL

—

ST

TTL

—

Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.

Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.

Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.

Description

 2003 Microchip Technology Inc. DS39599C-page 17

PIC18F2220/2320/4220/4320

TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/AN5/RD

RE0
AN5
RD

RE1/AN6/WR

RE1
AN6
WR

RE2/AN7/CS

RE2
AN7
CS

RE3 1 18 18 — — See MCLR

SS 12,

V

DD 11, 32 7, 28 7, 8,

V

NC — — 13 NC NC No connect.
Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V

Note 1: Default assignment for CCP2 wh en CCP2MX (CONFIG3H<0>) is set.

2: Alternate assignment for CCP2 when CCP2MX is cleared.

Pin Number

PDIP TQFP QFN

82525

92626

10 27 27

6, 29 6, 30, 31P — Ground reference for logic and I/O pins.

31

28, 29

Pin

Buffer

Type

DD)

Type

PORTE is a bidirectional I/O port.

I/O

I/O

I/O

ST

I

Analog

I

TTL

ST

I

Analog

I

TTL

ST

I

Analog

I

TTL

P — Positive supply for logic and I/O pins.

Digital I/O.
Analog input 5.
Read control for Parallel Slave Port
(see also WR

Digital I/O.
Analog input 6.
Write control for Parallel Slave Port
(see CS

Digital I/O.
Analog input 7.
Chip select control for Parallel Slave Port
(see related RD

and RD pins).

/VPP/RE3 pin.

Description

and CS pins).

and WR).

DS39599C-page 18  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

The PIC18F2X20 and PIC18F4X20 devices can be
operated in ten dif ferent osci llator modes . The user can
program the configuration bits, FOSC3:FOSC0, in
Configuration Register 1H to select one of these ten
modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL enabled

5. RC External Resistor/Cap ac ito r with

OSC/4 output on RA6

F

6. RCIO External Resistor/Capacito r with

I/O on RA6

7. INTIO1 Internal Oscillator with F

output on RA6 and I/O on RA7

8. INTIO2 Internal O scil lat or with I/O on RA6

and RA7

9. EC External Clock with F

10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.

The oscillator design requires the use of a parallel cut
crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturers
specifications.

OSC/4

OSC/4 output

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)

(1)

C1

(1)

C2

Note 1: See Table 2-1 and Table 2-2 for initial values

2: A series resistor (R

3: R

OSC1

To

Internal

XTAL

(2)

RS

OSC2

of C1 and C2.

strip cut crystals.

F varies with the oscillator mode chosen.

(3)

RF

PIC18FXXXX

S) may be required for AT

Logic

Sleep

T ABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz
Capacitor values are for design guidance only.
These capacitors were tested with the resonators

listed below for basic start-up and operation. These
values are not optimized.

Different cap acitor values may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes on page 20 for additional information.

Resonators Used:

455 kHz 4.0 MHz

2.0 MHz 8.0 MHz

16.0 MHz

56 pF
47 pF
33 pF

27 pF
22 pF

56 pF
47 pF
33 pF

27 pF
22 pF

 2003 Microchip Technology Inc. DS39599C-page 19

PIC18F2220/2320/4220/4320

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc T y pe

Crystal

Freq

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF

4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed

below for basic start-up and op erat ion . These values

are not optimized.

Different capa citor values may be required to produc e
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes following this table for additional

information.

32 kHz 4 MHz

200 kHz 8 MHz

1 MHz 20 MHz

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the
start-up time.

2: When operating below 3V V

using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

S may be required to avoid overdriving

4: R

crystals with low driv e lev e l spe ci fic ati on.

5: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

T ypical Cap acitor V alues

Tested:

C1 C2

Crystals Used:

DD, or when

An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS OSC
CONFIGURATION)

Clock from
Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.3 HSPLL

A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
crystal oscillator circuit, or to clock the device up to its
highest rated frequency from a crystal oscillator. This
may be useful for customers who are concerned with
EMI due to high-frequency crystals.

The HSPLL mode make s use of the HS mode osc illator
for frequencies up t o 10 MHz. A PLL then multipl ies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.

The PLL is enabled only when the oscillator configura­tion bits are programmed for HSPLL mode. If
programmed for any other mode, the PLL is not
enabled.

FIGURE 2-3: PLL BLOCK DIAGRAM

HS Osc Enable

PLL Enable

(from Configuration Register 1H)

OSC2

OSC1

HS Mode

Crystal

Osc

IN

F
FOUT

÷4

Phase

Comparator

Loop
Filter

VCO

SYSCLK

MUX

DS39599C-page 20  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

2.4 External Clock Input

The EC and ECIO Oscillator mode s require an externa l
clock source to be conn ected to the OSC1 pi n. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK INPUT

OPERATION
(EC CONFIGURATION)

Clock from
Ext. System

OSC/4

F

The ECIO Oscillator mode func ti ons li ke t he EC m od e,
except that the OSC2 pin becomes an additional gen­eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK INPUT

Clock from
Ext. System

RA6

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

OPERATION
(ECIO CONFIGURATION)

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

2.5 RC Oscillator

For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from uni t to unit due to
normal manufacturing variation. Furthermore, the dif­ference in lead frame capacitance between package
types will also affect the oscillation frequency, espe­cially for low C

EXT values. The user also needs to take

into account variation due to tolerance of external R
and C components used. Figure 2-6 shows how the
R/C combination is connected.

In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic.

FIGURE 2-6: RC OSCILLATOR MODE

VDD

REXT

CEXT

VSS

F

OSC/4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

The RCIO Oscillator mode (Figure 2-7) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).

EXT) and capacitor (CEXT) val-

OSC1

Internal

Clock

PIC18FXXXX

OSC2/CLKO

EXT > 20 pF

C

FIGURE 2-7: RCIO OSCILLATOR MODE

VDD

REXT

OSC1

CEXT

VSS

RA6

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

 2003 Microchip Technology Inc. DS39599C-page 21

I/O (OSC2)

C

EXT > 20 pF

Internal

Clock

PIC18FXXXX

PIC18F2220/2320/4220/4320

2.6 Internal Oscillator Block

The PIC18F2X20/4X20 devices include an internal
oscillator block wh ich generat es two dif ferent cl ock sig­nals. Either can be used as the system’s clock source.
This can eliminate the need for external oscillator
circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the system clock. It
also drives a postscaler which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator
(INTRC) which provides a 31 kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source or when any of the
following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Spe ed Start-up
These features are discussed in greater detail in

Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC

direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 26).

2.6.1 INTIO MODES

Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pin s
which can then be used for digital I/O. Two distinct
configurations are available:

• In INTIO1 mode, the OSC2 pin outputs F
while OSC1 functions as RA 7 fo r dig it a l in put a nd
output.

• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.

OSC/4,

2.6.2 INTRC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
This changes the frequency of the INTRC source from
its nominal 31.25 kHz. Peripherals and features that
depend on the INTRC source will be affected by this
shift in frequency.

Once set during factory calibration, the INTRC
frequency will remain within ±1% as temperature and

DD change across their full specified operating

V
ranges.

2.6.3 OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at
the factory but c an be adjusted in the user's ap plication.
This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.

When the OSCTUNE regis ter is mo di fied , the IN T O SC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new fre­quency within 8clock cycles (approximately
8*32µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code execution conti nues du ring th is shift.
There is no indicati on that th e shift ha s occurre d. Oper­ation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in frequency.

DS39599C-page 22  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits

011111 = Maximum frequency (+12.5%, approximately)

• •

• •

000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111

• •

• •
100000 = Minimum frequency (-12.5%, approximately)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS39599C-page 23

PIC18F2220/2320/4220/4320

2.7 Clock Sources and Oscillator

Switching

Like previous PIC18 devices, the PIC18F2X20 and
PIC18F4X20 devices include a feature that allows the
system clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
PIC18F2X20/4X20 devices offer two alternate clock
sources. When enabled, these give additional options
for switching to the various power managed operating
modes.

Essentially, there are three clock sources for these
devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the E xternal Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mod e is defined on POR by the content s
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.

The s econdary oscillat ors are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.

PIC18F2X20/4X20 devices offer only the Timer1
oscillator as a seco ndary oscilla tor . This oscil lator , in all
power managed modes, is often the time base for
functions such as a real-time clock.

Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/ T1CKI and RC1 /T1OSI pins.
Like the LP mode oscillator circuit, loading capacitors
are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in
Section 12.2 “Timer1 Oscillator”.

In addition to being a p rimary clock source, the internal
oscillator block is available as a power managed
mode clock source. The INTRC source is a lso us ed as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2X20/4X20 devices
are shown in Figure 2-8. See Section 12.0 “Timer1

Module” for further details of th e Timer1 os cillator . See
Section 23.1 “Configuration Bits” for Configuration

register details.

2.7.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power managed modes.

The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating
in power managed modes. The ava ilable c lock sou rces
are the primary clock (defined in Configuration
Register 1H), the secondary clock (Timer1 oscillator)
and the internal oscillator block. The clock selection
has no effect until a SLEEP instruction is executed and
the device enters a power managed mode of opera tion.
The SCS bits are cleared on all forms of Reset.

The Internal Oscill ator Select bit s, IRCF2:IRCF0, select
the frequency output of the interna l oscill ator block th at
is used to dr ive t he sys tem clo ck. Th e choi ces are t he
INTRC source, the INTOSC source (8 MHz) or one of
the six frequencies derived from the INTOSC
postscaler (125kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of thes e bits w ill ha ve an immedi ate cha nge on
the internal oscillator’s output.

The OSTS, IOFS and T1RUN bits ind icate wh ich cl oc k
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer has
timed out and the prima ry clock is providin g the system
clock in pri mary clock mode s. The IOFS b it indicates
when the internal oscillator block has stabilized and is
providing the system clock in RC Clock modes. The
T1RUN bit (T1CON<6>) indicates when the Timer1
oscillator is providing the system clock in secondary
clock modes. If none of th ese bit s are set, th e INTRC is
providing the system clock, or the internal oscillator
block has just started and is not yet stable.

The IDLEN bit controls the selective shutdown of the
controller’s CPU in power managed mo des. The use of
these bits is discussed in more detail in Section 3.0

“Power Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The
Timer1 osc illator is enabled by s etting the
T1OSCEN bit in th e T imer1 C ontrol re gis­ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any atte mpt to set the
SCS0 bit will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before
executing the SLEEP instr u ct ion or a very
long delay may occur while the Timer1
oscillator starts.

DS39599C-page 24  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

FIGURE 2-8: PIC18F2X20/4X20 CLOCK DIAGRAM

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

Secondary Oscillator

T1OSCEN
Enable
Oscillator

OSCCON<6:4>

Internal

Oscillator

Block

INTRC

Source

8 MHz

(INTOSC)

PIC18F2X20/4X20

4 x PLL

OSCCON<6:4>

8 MHz

111

4 MHz

110

2 MHz

101

1 MHz

31 kHz

100

011

010

001

000

Postscaler

500 kHz
250 kHz
125 kHz

CONFIG1H<3:0>

HSPLL

LP, XT, HS, RC, EC

Clock Source Option
for Other Modules

Internal Oscillator

MUX

T1OSC

Clock

Control

MUX

OSCCON<1:0>

Peripherals

CPU

IDLEN

WDT, FSCM

 2003 Microchip Technology Inc. DS39599C-page 25

PIC18F2220/2320/4220/4320

REGISTER 2-2: OSCCON REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

bit 7 IDLEN: Idle Enable bit

1 = Idle mode enabled; CPU core is not clocked in power managed modes
0 = Run mode enabled; CPU core is clocked in power managed modes

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (INTRC source drives clock directly)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Oscillator start-up time-out timer has expired; primary oscillator is running
0 = Oscillator start-up time-out timer is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits

1x = Internal oscillator block (RC modes)
01 = Timer1 oscillator (Secondary modes)
00 = Primary oscillator (Sleep and PRI_IDLE modes)

Note 1: Depends on state of IESO bit in Configuration Register 1H.

2: SCS0 may not be set while T1OSCEN (T1CON<3>) is clear.

(1)

(2)

(1)

R-0 R/W-0 R/W-0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39599C-page 26  2003 Microchip Technology Inc.

PIC18F2220/2320/4220/4320

2.7.2 OSCIL LAT OR TRANSITIONS

The PIC18F2X20/4X20 de vices contain ci rcuitry to pre­vent clocking “glitches” when switching between clock
sources. A short p aus e in the sy stem c lock o ccurs dur­ing the clock switch. The length of this pause is
between 8 and 9 clock pe riods of the n ew clock sourc e.
This ensures that the new clock source is stable and
that its pulse width will not be less than the shortest
pulse width of the two clock sources.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power Managed Modes”.

2.8 Effects of Power Managed Modes on the Various Clock Sources

When the device executes a SLEEP instruction, the
system is switched to one of the power managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power Managed Modes” for details.

When PRI_IDLE mode is selected, the designated pri­mary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the o scillat or) will sto p oscillat ing.

In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is op erat ing an d p ro­viding the s ystem clo ck. The T ime r1 osci llator m ay als o
run in all power managed modes if required to clock
Timer1 or Timer3.

In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power managed mode (see Section 23.2 “Watchdog

Timer (WDT)” through Section 23.4 “Fail-Safe Clock
Monitor”). The INTOSC output at 8 MHz may be used

directly to clock the system or may be divided down
first. The INTOSC out put is disabled if the sy stem clock
is provided directly from the INTRC output.

If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).

Enabling any on-chip feature that will operate during
Sleep will increase the current co nsumed duri ng Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a real­time clock. Ot her features may be operating that do n ot
require a system clock source (i.e., SSP slave, PSP,
INTn pins, A/D conversions and others).

2.9 Power-up Delays

Power-up delays are c ontrolled by two ti mers so that no
external Reset circuitry is required for most applica­tions. The delays ensure that the device is kept in
Reset until the device powe r supply i s stable under nor­mal circumstan ces and the pri mary clock is ope rating
and stable. For additional information on power-up
delays, see Section 4.1 “Power-on Reset (POR)”
through Section 4.5 “Brown-out Reset (BOR)”.

The first timer is the Power-up Timer (PWRT) which
provides a fixed delay on power-up (parameter 33,
Table 26-10), if enabled, in Configuration Register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Rese t until the crys­tal oscillator is stable (LP, XT and HS modes). The OST
does this by counting 1024 oscillator cycles before
allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, the
device is kept in Res et for an add iti onal 2ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequ enc y.

There is a delay of 5 to 10 µs, following POR, while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the only del ay that occurs when any o f the EC ,
RC or INTIO modes are used as the primary clock
source.

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC Mode OSC1 Pin OSC2 Pin

RC, INTIO1 Floating, external resistor

should pull high

RCIO, INTIO2 Floating, external resistor

should pull high
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT, and HS Feedback inverter disabled at

quiescent voltage level

Note: See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR

 2003 Microchip Technology Inc. DS39599C-page 27

At logic low (clock/4 output)

Configured as PORTA, bit 6

Feedback inverter disabled at
quiescent voltage level

Reset.

PIC18F2220/2320/4220/4320

NOTES:

DS39599C-page 28  2003 Microchip Technology Inc.