MICROCHIP PIC18F1220, PIC18F1320 DATA SHEET
PIC18F1220/1320
Data Sheet
18/20/28-Pin High-Performance,
Enhanced Flash Microcontrollers
with 10-bit A/D and nanoWatt Technology
2004 Microchip Technology Inc. DS39605C
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
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No representation or warranty is given and no liability is
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS39605C-page ii 2004 Microchip Technology Inc.
PIC18F1220/1320
18/20/28-Pin High-Performance, Enhanced Flash MCUs
with 10-bit A/D and nanoWatt Technology
Low-Power Features:
• Power Managed modes:
- Run: CP U on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Power Consumption modes:
- PRI_RUN: 150 µA, 1 MHz, 2V
- PRI_IDLE: 37 µA, 1 MHz, 2V
- SEC_RUN: 14 µA, 32 kHz, 2V
- SEC_IDLE: 5.8 µA, 32 kHz, 2V
- RC_RUN: 110 µA, 1 MHz, 2V
- RC_IDLE: 52 µA, 1 MHz, 2V
- Sleep: 0.1 µA, 1 MHz, 2V
• Timer1 Oscillator: 1.1 µA, 32 kHz, 2V
• Watchdog Timer: 2.1 µA
• Two-Speed Oscillator Start-up
Oscillators:
• Four Crystal modes:
- LP, XT, HS: up to 25 MHz
- HSPLL: 4-10 MHz (16-40 MHz internal)
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40MHz
• Internal oscillator block:
- 8 user-selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MH z
- 125 kHz to 8 MHz calibrated to 1%
- Two modes select one or two I/O pins
- OSCTUNE
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor
- Allows for safe shutdown if peripheral clock stops
– Allows user to shift frequency
Peripheral Highlight s:
• High current sink/source 25 mA/25 mA
• Three external interrupts
• Enhanced Capture/Compare/PWM (ECCP) module:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
- Capture is 16-bit, max resolution 6.25 ns (T
- Compare is 16-bit, max resolution 100 ns (T
• Compatible 10-bit, up to 13-chan nel Analog -toDigital Converter module (A/D) with programmable
acquisition time
• Enhanced USART module:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
- Auto-Baud Detect
CY/16)
CY)
Special Microcontroller Features:
• 100,000 erase/write cycl e Enhan ced Flas h
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Flash/Data EEPROM Retention: > 40 years
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
- 2% stability over V
• Single-supply 5V In-Circuit Serial Programming™
(ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
DD and Temperature
Program Memory Data Memory
Device
PIC18F1220 4K 2048 256 256 16 7 1 Y 1/3
PIC18F1320 8K 4096 256 256 16 7 1 Y 1/3
2004 Microchip Technology Inc. DS39605C-page 1
Flash
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes)
I/O
10-bit
A/D (ch)
ECCP
(PWM)
EUSART
Timers
8/16-bit
PIC18F1220/1320
Pin Diagrams
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
MCLR
/VPP/RA5
V
SS/AVSS
RA2/AN2/VREF-
RA3/AN3/V
RB0/AN4/INT0
REF+
RB1/AN5/TX/
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RB3/CCP1/P1A
RB2/P1B/INT2
OSC1/CLKI/RA7
OSC2/CLKO/RA6
DD/AVDD
V
RB7/PGD/T1OSI/
RB6/PGC/T1OSO/
RB5/PGM/KBI1
RB4/AN6/RX/
DS39605C-page 2 2004 Microchip Technology Inc.
PIC18F1220/1320
Table of Contents
1.0 Device Overview.......................................................................................................................................................................... 5
2.0 Oscillator Configurations............................................................................................................................................................ 11
3.0 Power Managed Modes ...................................... .. .. .... .. .. ..... .. .. .... .. .. .. .. ....... .. .. .. .. .. .. ....... .. .. .. ...................................................... 19
4.0 Reset..........................................................................................................................................................................................33
5.0 Memory Organization.................................................................................................................................................................41
6.0 Flash Program Memory............ ................ ................. ................. ................................................................................................57
7.0 Data EEPROM Memory.................................. ................................................ ........................................................................... 67
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 71
9.0 Interrupts.................................................................................................................................................................................... 73
10.0 I/O Ports................................... .................................................................................................................................................. 87
11.0 Timer0 Module ...........................................................................................................................................................................99
12.0 Timer1 Module ......................................................................................................................................................................... 103
13.0 Timer2 Module ......................................................................................................................................................................... 109
14.0 Timer3 Module ......................................................................................................................................................................... 111
15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 115
16.0 Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .......................................... 131
17.0 10-Bit Analog-to-Digital Converter (A/D) Module .....................................................................................................................155
18.0 Low-Voltage Detect.................................................................................................................................................................. 165
19.0 Special Features of the CPU........................................... ................. ........................................................................................ 171
20.0 Instruction Set Summary.......................................................................................................................................................... 191
21.0 Development Support............................................................................................................................................................... 233
22.0 Electrical Characteristics.......................................................................................................................................................... 239
23.0 DC and AC Characteristics Graphs and Tables............................................................................. .......................................... 269
24.0 Packaging Information................................................. ................................................. ............................................................ 287
Appendix A: Revision History............................................................................................................................................................. 293
Appendix B: Device Differences ........................................................................................................................................................293
Appendix C: Conversion Considerations ...........................................................................................................................................294
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 294
Appendix E: Migration from Mid-Range to Enhanced Devices.......................................................................................................... 295
Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 295
Index .................................................................................................................................................................................................. 297
On-Line Support.................................................................................................................................................................................305
Systems Information and Upgrade Hot Line...................................................................................................................................... 305
Reader Response.............................................................................................................................................................................. 306
PIC18F1220/1320 Product Identification System ............................................................................ .... .............................................. 307
2004 Microchip Technology Inc. DS39605C-page 3
PIC18F1220/1320
TO OUR VALUED CUSTOMERS
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DS39605C-page 4 2004 Microchip Technology Inc.
PIC18F1220/1320
1.0 DEVICE OVERVIEW
This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:
• PIC18F1220 • PIC18F1320
This family offers the advantages of all PIC18 microcontrollers – nam ely, high computationa l perfor manc e at an
economical pri ce – with the additio n of high enduran ce
Enhanced Flash program memory. On top of these features, the PIC18F1220/1320 family introduces design
enhancements that make these microcontrollers a logical
choice for many high-performance, power sensitive
applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F1220/1320 family incorporate a range of features that can significantly reduce
power consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU c ore disable d, but the pe ripherals are
still active. In these states, power consumption can
be reduced even further, to as little as 4% of normal
operation requirements.
• On-the-fly Mode Switching: The power managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
• Lower Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer have been reduced by up to 80%, with typical
values of 1.1 and 2.1 µA, respectively.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F1220/1320 family offer
nine different oscillator options, allowing users a wide
range of choices in developing application hardware.
These include:
• Four Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output), or one pin (oscillator input, with the
second pin reassigned as general I/O).
• Two External RC Oscillator modes, with the same
pin options as the External Clock modes.
• An internal oscillator block, which provides an
8 MHz clock (±2% accuracy) and an INTRC source
(approximately 31kHz, stable over temperature and
V
DD), as well as a range of 6 user-selectable clock
frequencies (from 125 kHz to 4 MHz) for a total of
8 clock frequencies.
Besides its ava ilability as a cloc k source, the intern al
oscillator block pro vid es a s t ab le re fere nce source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator . If a clock failure occurs, the controller is switched to the internal
oscillator block, allowing for continued low-speed
operation, or a safe application shutdown.
• T wo-Spe ed Start-up: This option allows the internal
oscillator to serve as the cloc k source from Powe ron Reset, or wake-up from Sleep mode, until the
primary clock source is available. This allows for
code execution during what would otherwise be the
clock start-up interval and can even allow an application to perform routine background activities and
return to Sleep without returning to full power
operation.
1.2 Other Special Features
• Memory Endurance: The Enhanced Flash cells for
both program memory and data EEPROM are rated
to last for many thousands of erase/wri te cycles –
up to 100,000 for program memory and 1,000,000
for EEPROM. Data retention without refresh is
conservatively estimated to be greater than
40 years.
• Self-programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Block at the top of program memory, it becomes possible to create an
application that can update itself in the field.
• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers. Other
features include auto-shutdown, for disabling PWM
outputs on interrupt or other select conditions and
auto-restart, to reactiv ate outpu t s onc e the condi tio n
has cleared.
• Enhanced USART: This serial communication
module features automatic wake-up on Start bit and
automatic baud rate d etecti on and supp ort s RS-23 2,
RS-485 and LIN 1.2 protocols, making it ideally
suited for use in Local Interconnect Network (LIN)
bus applications.
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This enhanced
version incorporates a 16-bit prescaler, allowing a
time-out range from 4 ms to over 2 minutes that is
stable across operating voltage and temperature.
2004 Microchip Technology Inc. DS39605C-page 5
PIC18F1220/1320
1.3 Details on Individual Family Members
Devices in the PIC18F1220/1320 family are available
in 18-pin, 20-pin an d 28-pin pack ages. A block dia gram
for this device family is shown in Figure 1-1.
The devices are differentiated from each other only in
the amount of on-chip Flash program memory
(4 Kbytes for the PIC18F1220 device, 8 Kbytes for the
PIC18F1320 device). These and other features are
summarized in Table 1-1.
A block diagram of the PIC18F1220/1320 device
architecture is provided in Figure 1-1. The pinouts for
this device family are listed in Table 1-2.
TABLE 1-1: DEVICE FEATURES
Features PIC18F1220 PIC18F1320
Operating Frequency DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 4096 8192
Program Memory (Instruction s) 2048 4096
Data Memory (Bytes) 256 256
Data EEPROM Memory (Bytes) 256 256
Interrupt Sources 15 15
I/O Ports Ports A, B Ports A, B
Timers 4 4
Enhanced Capture/Compare/PWM Modules 1 1
Serial Communications Enhanced USART Enhanced USART
10-bit Analog-to-Digital Module 7 input channels 7 input channels
POR, BOR,
Resets (and Delays)
Programmable Low-Voltage Detect Yes Yes
Programmable Brown-out Reset Yes Yes
Instruction Set 75 Instructions 75 Instructions
Packages
RESET Instruction, Stack Full,
Stac k U nde rflo w (PWRT, OST),
(optional), WDT
MCLR
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
RESET Instruction, Stack Full,
Stack Underflow (PWRT, OST),
POR, BOR,
MCLR (optional), WDT
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
DS39605C-page 6 2004 Microchip Technology Inc.
FIGURE 1-1: PIC18F1220/1320 BLOCK DIAGRAM
PIC18F1220/1320
Data Bus<8>
21
Address Latch
Program Memory
(4 Kbytes)
PIC18F1220
(8 Kbytes)
PIC18F1320
Data Latch
16
(2)
OSC1
(2)
OSC2
T1OSI
T1OSO
(1)
MCLR
DD, VSS
V
21
Table Pointer <2>
21
inc/dec logic
Table Latch
8
Instruction
Decode &
Control
Timing
Generation
INTRC
Oscillator
Low-Voltage
Programming
In-Circuit
Debugger
20
Start-up Timer
8
PCLATH
PCLATU
PCU
PCH PCL
Program Counter
31 Level Stack
ROM Latch
Instruction
Register
Power-up
Timer
Oscillator
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
8
8
8
4
BSR
Decode
BIT OP
Precision
Voltage
Reference
Address Latch
Address<12>
12 4
FSR0
FSR1
FSR2
inc/dec
3
8
8
Data Latch
Data RAM
12
Bank0, F
logic
PRODLPRODH
8 x 8 Multiply
WREG
8
ALU<8>
8
PORTA
RA0/AN0
RA1/AN1/LVDIN
(2)
12
PORTB
8
8
8
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
(1)
/VPP/RA5
MCLR
OSC2/CLKO/RA6
OSC2/CLKI/RA7
RB0/AN4/INT0
RB1/AN5/TX/CK/INT1
RB2/P1B/INT2
RB3/CCP1/P1A
RB4/AN6/RX/DT/KBI0
RB5/PGM/KBI1
RB6/PGC/T1OSO/
T13CKI/P1C/KBI2
RB7/PGD/T1OSI/
P1D/KBI3
(2)
(2)
Timer0
Enhanced
CCP
Note 1: RA5 is available only when the MCLR
2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital
I/O. Refer to Section 2.0 “Osc illa to r Configu ratio ns ” for additional information.
Timer1
Timer2
Reset is disabled.
Timer3
Enhanced
USART
A/D Converter
Data EEPROM
2004 Microchip Technology Inc. DS39605C-page 7
PIC18F1220/1320
TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
PDIP/
SOIC
SSOP QFN
Pin
Type
Buffer
Type
Description
/VPP/RA5
MCLR
MCLR
VPP
RA5
OSC1/CLKI/RA7
OSC1
CLKI
RA7
OSC2/CLKO/RA6
OSC2
CLKO
RA6
RA0/AN0
RA0
AN0
RA1/AN1/LVDIN
RA1
AN1
LVDIN
RA2/AN2/V
RA3/AN3/VREF+
RA4/T0CKI
RA5 See the MCLR
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pi n.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
REF-
RA2
AN2
V
REF-
RA3
AN3
V
REF+
RA4
T0CKI
ST = Schmitt Trigger input with CMOS levels I = Input
O=Output P =Power
OD = Op en- dr ai n ( no P di od e t o V
441
16 18 21
15 17 20
1126
2227
677
788
3328
I
ST
P
I/O
O
O
I/O
I/O
I/O
I/O
I/O
I/OIST/OD
DD)
—
I
ST
I
ST
I
CMOS
ST
—
—
ST
ISTAnalog
ST
I
Analog
I
Analog
ST
I
Analog
I
Analog
ST
I
Analog
I
Analog
ST
Master Clear (input) or programming voltage (input) .
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage inpu t.
Digital input.
Oscillator crystal or extern al cl ock in put .
Oscillator crystal input or external clock source
input. ST buffer when configured i n R C m ode,
CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
Oscillator crystal or clock output.
Oscillator crystal output. C onnects to crystal or
resonator in Crystal Oscillator mode.
In RC, EC and INTRC modes, OSC2 pin outputs
CLKO, which has 1/4 the f re quency of OSC1 and
denotes instruction cy cl e r at e.
General purpose I/O pin.
PORTA is a bidirectional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Low-Voltage Detect input.
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
/VPP/RA5 pin.
DS39605C-page 8 2004 Microchip Technology Inc.
PIC18F1220/1320
T ABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RB0/AN4/INT0
RB0
AN4
INT0
RB1/AN5/TX/CK/INT1
RB1
AN5
TX
CK
INT1
RB2/P1B/INT2
RB2
P1B
INT2
RB3/CCP1/P1A
RB3
CCP1
P1A
RB4/AN6/RX/DT/KBI0
RB4
AN6
RX
DT
KBI0
RB5/PGM/KBI1
RB5
PGM
KBI1
RB6/PGC/T1OSO/
T13CKI/P1C/KBI2
RB6
PGC
T1OSO
T13CKI
P1C
KBI2
RB7/PGD/T1OSI/
P1D/KBI3
RB7
PGD
T1OSI
P1D
KBI3
V
SS 5 5, 6 3, 5 P — Ground reference for logic and I/O pins.
VDD 14 15, 16 17, 19 P — Positive supply for logic and I/O pins.
NC — — 18 — — No connect.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O=Output P =Power
OD = Op en- dr ai n ( no P di od e t o V
PDIP/
SSOP QFN
SOIC
899
91010
17 19 23
18 20 24
10 11 12
11 12 13
12 13 15
13 14 16
Pin
Type
I/O
I
I
I/O
I
O
I/O
I
I/O
O
I
I/O
I/O
O
I/O
I
I
I/O
I
I/O
I/O
I
I/O
I/O
O
I
O
I
I/O
I/O
I
O
I
DD)
Buffer
Type
TTL
Analog
ST
TTL
Analog
—
ST
ST
TTL
—
ST
TTL
ST
—
TTL
Analog
ST
ST
TTL
TTL
ST
TTL
TTL
ST
—
ST
—
TTL
TTL
ST
CMOS
—
TTL
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
Digital I/O.
Analog input 4.
External interrupt 0.
Digital I/O.
Analog input 5.
EUSART asynchronous transmit.
EUSART synchronou s cl ock (see related RX/D T) .
External interrupt 1.
Digital I/O.
Enhanced CCP1/PW M ou tput .
External interrupt 2.
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1/PW M ou tput .
Digital I/O.
Analog input 6.
EUSART asynchronous rec eive.
EUSART synchronous da ta (see re l ated TX/CK).
Interrupt-on-chang e pi n.
Digital I/O.
Low-Voltage ICSP Programming enable pin.
Interrupt-on-chang e pi n.
Digital I/O.
In-Circuit Debugger and ICSP programming clock pin.
Timer1 oscillator output.
Timer1/Timer3 external clock output.
Enhanced CCP1/PW M ou tput .
Interrupt-on-chang e pi n.
Digital I/O.
In-Circuit Debugger and ICSP programming data pin.
Timer1 oscillator input.
Enhanced CCP1/PW M ou tput .
Interrupt-on-chang e pi n.
2004 Microchip Technology Inc. DS39605C-page 9
PIC18F1220/1320
NOTES:
DS39605C-page 10 2004 Microchip Technology Inc.
PIC18F1220/1320
2.0 OSCILLATOR CONFIGURATIONS
2.1 Oscillator Types
The PIC18F1220 and PIC18F1320 devices can be
operated in ten dif ferent osci llator modes . The user can
program the configuration bits, FOSC3:FOSC0, in
Configuration Register 1H to select one of these ten
modes:
1. LP Low-Power Crystal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator
with PLL enabled
5. RC External Resistor/Capacitor with
OSC/4 output on RA6
F
6. RCIO Ex tern al R esi st or/C apacitor with
I/O on RA6
7. INTIO1 Internal Oscillator with F
output on RA6 and I/O on RA7
8. INTIO2 Internal Oscillator with I/O on RA6
and RA7
9. EC External Clock with F
10. ECIO External Clock with I/O on RA6
2.2 Crystal Oscillator/Ceramic Resonators
In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
Note: Use of a series cut crystal may give a
frequency out of the crystal manufacturer’s
specifications.
OSC/4
OSC/4 output
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
(1)
C1
(1)
C2
Note 1: See Table 2-1 and Table 2-2 for initial
2: A series resistor (R
3: R
OSC1
To
Internal
XTAL
(2)
RS
OSC2
values of C1 and C2.
AT strip cut crystals.
F varies with the oscillator mode chosen.
(3)
RF
S) may be required for
Logic
Sleep
PIC18FXXXX
T ABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
HS 8.0 MHz
16.0 MHz
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Different cap acitor values may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
DD and temperature range for the application.
V
See the notes following Table 2-2 for additional
information.
Resonators Used:
455 kHz 4.0 MHz
2.0 MHz 8.0 MHz
16.0 MHz
56 pF
47 pF
33 pF
27 pF
22 pF
56 pF
47 pF
33 pF
27 pF
22 pF
2004 Microchip Technology Inc. DS39605C-page 11
PIC18F1220/1320
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc T y pe
Crystal
Freq
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 1 MHz 33 pF 33 pF
4 MHz 27 pF 27 pF
HS 4 MHz 27 pF 27 pF
8 MHz 22 pF 22 pF
20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation . These values
are not optimized.
Different capa citor values may be required to produc e
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
DD and temperature range for the application.
V
See the notes following this table for additional
information.
Crystals Used:
32 kHz 4 MHz
200 kHz 8 MHz
1 MHz 20 MHz
Note 1: Higher capacitance increases the stability
of oscillator, but als o increases the start-up
time.
2: When operating below 3V V
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
S may be required to avoid overdriving
4: R
crystals with low driv e lev e l spe ci fic ati on.
5: Always veri fy os ci lla tor pe rform an ce ov er
DD and temperature range that is
the V
expected for the application.
T ypical Cap acitor V alues
Tested:
C1 C2
DD, or when
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Clock from
Ext. System
Open
OSC1
OSC2
PIC18FXXXX
(HS Mode)
2.3 HSPLL
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
crystal oscillator circuit, or to clock the device up to its
highest rated frequency from a crystal oscillator. This
may be useful for customers who are concerned with
EMI due to high-frequency crystals.
The HSPLL mode make s use of the HS mode osc illator
for frequencies up t o 10 MHz. A PLL then multipl ies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.
The PLL is enabled only when the oscillator configuration bits are programmed for HSPLL mode. If
programmed for any other mode, the PLL is not
enabled.
FIGURE 2-3: PLL BLOCK DIAGRAM
HS Oscillator Enable
(from Configuration Register 1H)
OSC2
OSC1
Crystal
Osc
PLL Enable
F
IN
Comparator
FOUT
÷4
Phase
Loop
Filter
VCO
SYSCLK
MUX
DS39605C-page 12 2004 Microchip Technology Inc.
PIC18F1220/1320
2.4 External Clock Input
The EC and ECIO Oscillator mode s require an externa l
clock source to be conn ected to the OSC1 pi n. There is
no oscillator start-up time required after a Power-on
Reset, or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for te st pu rpos es , o r to s yn chroni ze oth er
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-4: EXTER NAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
Clock from
Ext. System
OSC/4
F
The ECIO Oscillator mode func ti ons li ke t he EC m od e,
except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
FIGURE 2-5: EXTER NAL CLOCK INPUT
Clock from
Ext. System
RA6
OSC1/CLKI
PIC18FXXXX
OSC2/CLKO
OPERATION
(ECIO CONFIGURATION)
OSC1/CLKI
PIC18FXXXX
I/O (OSC2)
2.5 RC Oscillator
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from uni t to unit due to
normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package
types will also affect the oscillation frequency, especially for low C
EXT values. The user also needs to take
into account variation, due to tolerance of external
R and C components used. Figure 2-6 shows how the
R/C combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for te st purposes, or to synchronize other
logic.
FIGURE 2-6: RC OSCILLATOR MODE
VDD
REXT
CEXT
VSS
F
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
The RCIO Oscillator mode (Figure 2-7) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
EXT) and capacitor (CEXT) val-
OSC1
OSC2/CLKO
OSC/4
EXT > 20 pF
C
Internal
Clock
PIC18FXXXX
FIGURE 2-7: RCIO OSCILLATOR MODE
VDD
REXT
OSC1
CEXT
VSS
RA6
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
2004 Microchip Technology Inc. DS39605C-page 13
I/O (OSC2)
EXT > 20 pF
C
Internal
Clock
PIC18FXXXX
PIC18F1220/1320
2.6 Internal Oscillator Block
The PIC18F1220/1320 devices include an internal
oscillator block, which generates two different clock
signals; either can be used as the system’s clock
source. This can eliminate the need for external
oscillator circuits on the OSC1 and/or OSC 2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the system clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC), which provides a 31kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source, or when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Spe ed Start-up
These features are discussed in greater detail in
Section 19.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register2-2).
2.6.1 INTIO MODES
Using the internal oscillator as the clock source can
eliminate the need for up t o two extern al oscilla tor pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs F
while OSC1 functions as RA 7 fo r dig it a l in put a nd
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
OSC/4,
2.6.2 INTRC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz
(see Table 22-6). This changes the frequency of the
INTRC source from its nominal 31.25 kHz. Peripherals
and features that depend on the INTRC source will be
affected by this shift in frequency.
Once set during factory calibration, the INTRC
frequency will remain within ±2% as temperature and
DD change across their full specified operating
V
ranges.
2.6.3 OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at
the factory, but can be adjusted in the user’s application. Thi s is do ne by writi ng to the OS CTUNE regi ster
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
When the OSCTUNE regis ter is mo di fied , the IN T O SC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8clock cycles (approximately
8*32µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during th is shift.
There is no indication that the shift has occurred.
Operation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in frequency.
DS39605C-page 14 2004 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 2-1: OSCTUNE: OSCILLATOR T UNING REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
• •
• •
000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111
• •
• •
100000 = Minimum frequency
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2.7 Clock Sources and Oscillator Switching
Like previous PIC18 devices, the PIC18F1220/1320
devices include a feature that allows the system clock
source to be switched from the main oscillator to an
alternate low-frequency clock source. PIC18F1220/
1320 devices offer two alternate clock sources. When
enabled, these give additional options for switching to
the various power managed operating modes.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the Ex ternal Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mod e is defined on POR by the content s
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.
The s econdary oscillat ors are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.
PIC18F1220/1320 devices offer only the Timer1
oscillator as a secon dary oscilla tor . This osc illator , in all
power managed modes, is often the time base for
functions such as a real-time cloc k.
Most often, a 32.768 kHz watch crystal is connected
between the RB6/T1OSO and RB7/T1OSI pins. Like
the LP mode oscillator circuit, loading capacitors are
also connect ed from each pin to ground . These pins
are also used during ICSP operations.
The Timer1 oscillator is discussed in greater detail in
Section 12.2 “Timer1 Oscillator”.
In addition to being a prim ary clock source, the internal
oscillator block is available as a power managed
mode clock source. T he IN TR C s ource is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
The clock sources for the PIC18F1220/1320 devices
are shown in Figure 2-8. See Section 12.0 “Timer1
Module” for further details of the Time r1 oscillator. See
Section 19.1 “Configuration Bits” for configuration
register details.
2004 Microchip Technology Inc. DS39605C-page 15
PIC18F1220/1320
2.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating in
power managed modes. The available clock sources are
the primary clock (defined in Configuration Register 1H),
the secondary clock (Timer1 oscillator) and the internal
oscillator block. The clock selection has no effect until a
SLEEP instruction is executed and the device enters a
power managed mode of operation. The SCS bits are
cleared on all forms of Reset.
The Internal Oscill ator Select bit s, IRCF2:IRCF0, select
the frequency output o f the interna l oscill ator block th at
is used to dr ive t he sys tem clo ck. Th e ch oice s are the
INTRC source, the INTOSC source (8 MHz), or one of
the six frequencies derived from the INTOSC
postscaler (125kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output.
The OSTS, IOFS and T1RUN bit s ind ic ate wh ich clock
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer has
timed out and the prima ry clock is pro viding the system
clock in Primary Clock modes. The IOFS bit indicates
when the internal oscillator block has stabilized and is
providing the system clock in RC Clock modes or
during Two-Speed Start-ups. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the syste m cloc k in Seco ndary Clock modes .
In power managed modes, only one of these three bits
will be set at any time. If none of these bits are set, the
INTRC is providing the system clock, or the internal
oscillator block has just started and is not yet stable.
The IDLEN bit controls the selective shutdown of the
controller’s CPU in power managed modes. The uses
of these bits are discussed in more detail in
Section 3.0 “Power Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 osc illator is enabled by s etting the
T1OSCEN bit in th e T imer1 C ontrol re gister (T1CON<3>). If the Timer1 oscillator
is not enabled, then any at tem pt to se lec t
a secondary clock source when
executing a SLEEP instruction will be
ignored.
2: It is recommended that the Timer1 oscil-
lator be operating and stable before executing the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
FIGURE 2-8: PIC18F1220/1320 CLOCK DIAGRAM
PIC18F1220/1320
OSCCON<6:4>
8
111
4 MHz
110
2 MHz
101
1 MHz
31 kHz
100
011
010
001
000
Postscaler
500 kHz
250 kHz
125 kHz
OSC2
OSC1
T1OSO
T1OSI
Primary Oscillator
Sleep
Secondary Oscillator
T1OSCEN
Enable
Oscillator
OSCCON<6:4>
Internal
Oscillator
Block
INTRC
Source
8 MHz
(INTOSC)
CONFIG1H<3:0>
4 x PLL
Clock Source Option
for Other Modules
MUX
HSPLL
LP, XT, HS, RC, EC
T1OSC
Internal Oscillator
Clock
Control
MUX
OSCCON<1:0>
Peripherals
CPU
IDLEN
WDT, FSCM
DS39605C-page 16 2004 Microchip Technology Inc.
REGISTER 2-2: OSCCON REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R
IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
bit 7 bit 0
bit 7 IDLEN: Idle Enable bits
1 = Idle mode enabled; CPU core is not clocked in power managed modes
0 = Run mode enabled; CPU core is clocked in Run modes, but not Sleep mode
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (INTRC source drives clock directly)
bit 3 OSTS: Oscillator Start-up Time-out Status bit
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2 IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: System Clock Select b its
1x = Internal oscillator block (RC modes)
01 = Timer1 oscillator (Secondary modes)
00 = Primary oscillator (Sleep and PRI_IDLE modes)
Note 1: Depends on state of the IESO bit in Configuration Register 1H.
PIC18F1220/1320
(1)
R-0 R/W-0 R/W-0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. DS39605C-page 17
PIC18F1220/1320
2.7.2 OSCILLATOR TRANSITIONS
The PIC18F1220/1320 devices contain circuitry to
prevent clocking “glitches” when switching between
clock sources. A short pause in the system clock
occurs during the clo ck switch. Th e length of thi s pause
is between 8 and 9 clock periods of the new clock
source. This ensures that the new clock source is
stable and that its pulse width will not be less than the
shortest pulse width of the two clock sources.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power Managed Modes”.
2.8 Effects of Power Managed Modes on the Various Clock Sources
When the device executes a SLEEP instruction, the
system is switched to one of the power managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power Managed Modes” for details.
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the o scillat or) will sto p oscillat ing.
In Secondary Clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the system clock. The Timer1 oscillator may
also run in all power managed modes if required to
clock Timer1 or Timer3.
In Internal Oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power managed mode (see Section 19.2 “Watchdog
Timer (WDT)” through Sec tion 19.4 “Fail-Safe Clock
Monitor”). The INTOSC output at 8 MHz may be used
directly to clock the system, or may be divided down
first. The INTOSC out put is disabled if the system clock
is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current cons umed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a realtime clock. Ot her features may be operating that do n ot
require a system clock source (i.e., INTn pins, A/D
conversions and others).
2.9 Power-up Delays
Power-up delays are controlled by two timers, so that
no external Rese t circ ui try is re qui red for most applications. The delays ensure that the device is kept in
Reset until the device powe r supply i s stable under normal circumstan ces and the pri mary clock is ope rating
and stable. For additional information on power-up
delays, see Sections 4.1 through 4.5.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 22-8) if enabled in Configuration Register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequ enc y.
There is a delay of 5 to 10 µs following POR while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the only del ay that occurs when any of the EC ,
RC or INTIO modes are used as the primary clock
source.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode OSC1 Pin OSC2 Pin
RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)
RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT and HS Feedback inverter disabled at quiescent
voltage level
Note: See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR
DS39605C-page 18 2004 Microchip Technology Inc.
Feedback inverter disabled at quiescent
voltage level
Reset.
PIC18F1220/1320
3.0 POWER MANAGED MODES
The PIC18F1220/1320 devic es o ffe r a tot al o f six operating modes for more efficient power management
(see Table 3-1). These provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery powered
devices).
There are three categories of power managed modes:
• Sleep mode
• Idle modes
• Run modes
These categories define which portions of the device
are clocked and some times , what sp eed. The R un and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator) and the Sleep mode offered by all
PICmicro
stopped) are both offered in the PIC18F1220/1320
devices (SEC_RUN and Sleep modes, respectively).
However, additional power managed modes are available that allow the u ser greater flexibili ty in dete rmining
what portions of the device are operating. The power
managed modes are event driven; that is, some
specific event must occur for the device to enter or
(more particularly) exit these operating modes.
®
devices (where all system clocks are
For PIC18F1220/1320 devices, the power managed
modes are invoked by using the existing SLEEP
instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset or a WDT time-out
(PRI_RUN mode is the normal full power execution
mode; the CPU and peri phe rals are cl ock ed by the p rimary oscillator source). In addition, power managed
Run modes may also exit to Sleep mode, or their
corresponding Idle mode.
3.1 Selecting Power Managed Modes
Selecting a power managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU clocking, while the
SCS1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
3.1.1 CLOCK SOURCES
The clock source is selected by setting the SCS bits of
the OSCCON register (Register 2-2). Three clock
sources are available for use in power managed Idle
modes: the primary clock (as confi gured in Configuration
Register 1H), the secondary clock (Timer1 oscillator)
and the internal oscillator block. The secondary and
internal oscillator block sources are available for the
power managed modes (PRI_RUN mode is the normal
full power execution mode; the CPU and peripherals are
clocked by the primary oscillator source).
TABLE 3-1: POWER MANAGED MODES
OSCCON Bits Module Clocking
Mode
Sleep 000 Off Off None – All clocks are disabled
PRI_RUN 000Clocked Clocked Primary – L P, XT, HS, HSPLL, RC, EC, INTRC
SEC_RUN 001Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN 01xClocked Clocked Internal Oscillator Block
PRI_IDLE 100 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 101 Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 11x Off Clocked Internal Oscillator Block
Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
IDLEN
<7>
SCS1:SCS0
<1:0>
CPU Peripherals
Available Clock and Oscillator Source
This is the normal full power execution mode.
(1)
(1)
(1)
2004 Microchip Technology Inc. DS39605C-page 19
PIC18F1220/1320
3.1.2 ENTERING POWER MANAGED
MODES
In general, entry, exit and switching between power
managed clock sources requires clock source
switching. In each case, the sequence of events is the
same.
Any change in the power managed mode begins with
loading the OSCCON register and executing a SLEEP
instruction. The SCS1:SCS0 bits select one of three
power managed clock sources; the primary clock (as
defined in Configuration R egister 1H), the s econdary
clock (the Timer1 os cillator) and the inte rnal osci llator
block (used i n RC mode s). Mo dif ying the SCS bits wi ll
have no effec t until a SLEEP instruction is executed.
Entry to the power managed mode is triggered by the
execution of a SLEEP instruction.
Figure 3-5 shows how the system is clocked while
switching from the primary clock to the Timer1 oscillator. When the SLEEP instruction is executed, clocks to
the device are stopped at the beginning of the next
instruction cycle. Eight clock cycles from the new clock
source are counted to synchronize with the new clock
source. After eight clock pulses from the new clock
source are counted, clocks from the new clock source
resume clocking the system. The actual length of the
pause is betwe en eight and nine cl ock periods from the
new clock source. This ensures that the new clock
source is stab le a nd th at its pulse width will not be less
than the shortest pulse width of the two clock sources.
Three bits in dicat e the current cloc k so urce: OSTS an d
IOFS in the OSCCON register and T1RUN in the
T1CON register. Only one of these b its will be set whil e
in a power managed mode. When the OSTS bit is set,
the primary clock is providing the system clock. When
the IOFS bit is set, the INTOSC output is providing a
stable 8 MHz clock source and is providing the system
clock. When the T1RUN bit is set, the T i mer1 oscillator
is providing the system clock. If none of these bits are
set, then either the INTRC clock source is clocking the
system, or the INTOSC source is not yet stable.
If the internal oscillator block is configured as the primary clock source in Configuration Register 1H, then
both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering an RC power managed mode
(same frequency) would clear the OSTS bit.
3.1.3 MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the
SLEEP instruction is determined by the settings of the
IDLEN and SCS bits at the time the instruction is executed. If another SLEEP instruction is executed, the
device will enter the power managed mode specif ied by
these same bits at that time. If the bits have changed,
the device will enter the new power managed mode
specified by the new bit settings.
3.1.4 COMPARISONS BETWEEN RUN AND IDLE MODES
Clock source selection for the Run modes is identical to
the corresponding Idle modes. When a SLEEP instruction is executed, the SCS bits in the OSCCON register
are used to switch to a different clock source. As a
result, if there is a ch ange of clock source at th e ti me a
SLEEP instruction is ex ecuted, a clock swi tch will occur .
In Idle modes, the CPU is not clocked and is not running. In Run mode s, the CPU is clocked a nd ex ecu tin g
code. This difference modifies the operation oe.1TJ/F7-0.9(.4ng)13I1(on )1 t66
DS39605C-page 20 2004 Microchip Technology Inc.
PIC18F1220/1320
TABLE 3-2: COMPARISON BETWEEN POWER MANAGED MODES
Power
Managed
Mode
Sleep Not clocked (not running) Wake-up Not clocked None or INTOSC multiplexer
Any Idle mode Not clocked (not running) Wake-up Primary, Secondary or
Any Run mode Primary or secondary
CPU is Clocked by ...
clocks or INTOSC
multiplexer
WDT Time-out
causes a .. .
Reset Primary or secondary
Peripherals are
Clocked by ...
INTOSC multiplexer
clocks or INTOSC
multiplexer
Clock during Wake-up
(while primary becomes
ready)
if Two-Speed Start-up or
Fail-Safe Clock Monitor are
enabled
Unchanged from Idle mode
(CPU operates as in
corresponding Run mode)
Unchanged from Run mode
3.2 Sleep Mode
The power managed Sleep mode in the PIC18F1220/
1320 devices is identical to that offered in all other
PICmicro microcontrollers. It is entered by clearing the
IDLEN and SCS1:SCS0 bits (this is the Reset state)
and executing the SLEEP instruction. This s huts down
the primary oscillator and the OSTS bit is cleared (see
Figure 3-1).
When a wake ev ent occurs i n Sleep mo de (by int errupt,
Reset or WDT time-out), the sy stem will no t be clocke d
until the primary clock source becomes ready (see
Figure 3-2), or it will be clocked from the internal
oscillator block if either the Two-Speed Start-up or the
Fail-Safe Clock Monitor are enabl ed (see Section 19.0
“Special Features of the CPU”). In either case, the
OSTS bit is set whe n t he primary clock is providin g the
system clocks. The IDLEN and SCS bits are not
affected by the wake-up.
3.3 Idle Modes
The IDLEN bi t allows the micr ocontrol ler’s C PU to be
selectively shut down while the peripherals continue to
operate. Clearing ID LEN allows t he CPU to be cl ocked.
Setting IDLEN disables clocks to the CPU, effectively
stopping program execution (see Register 2-2). The
peripherals continue to be clocked regardless of the
setting of the IDLEN bit.
There is one exception to how the IDLEN bit functions.
When all the low-power OSCCON bits are cleared
(IDLEN:SCS1:SCS0 = 000), the device enters Sleep
mode upon the exec ution of the SLEEP instruction. This
is both the Reset state of the OSCCON register and the
setting that selects Sleep mode. This maintains
compatibility with other PICmi cro devices that d o not
offer power managed modes.
If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a
‘1’ when a SLEEP instruction is executed, the
peripherals will be clocked from the clock source
selected using the SCS1 :SCS0 bits ; however, the CPU
will not be clocked. Since the CPU is not executing
instructions, the only exits from any of the Idle modes
are by interrupt, WDT time-out or a Reset.
When a wake event occurs, CPU execution is delayed
approximately 10µs while it becomes ready to e xecute
code. When the CPU begins executing code, it is
clocked by th e same clock s ource as was selected in
the power managed mode (i.e., when waking from
RC_IDLE mode, the internal oscillator block will clock
the CPU and peripherals unti l the primar y clock so urce
becomes ready – this is essentially RC_RUN mode).
This continues until the primary clock source becomes
ready. When the primary clock becomes ready, the
OSTS bit is set and the system clock source is
switched to the primary clock (see Figure 3-4). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to full power
operation.
2004 Microchip Technology Inc. DS39605C-page 21
PIC18F1220/1320
FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE
Q4Q3Q2
Q1Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
PC + 2PC
OSC1
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC
Q1 Q2 Q3 Q4 Q1 Q2
Q3 Q4 Q1 Q2
Q3 Q4
DS39605C-page 22 2004 Microchip Technology Inc.
PIC18F1220/1320
3.3.1 PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the fastest resump tion of devic e operation with its more
accurate pri mary clock source, si nce the cl ock source
does not have to “warm up” or transition from another
When a wake event occurs, the CPU is clocked from
the primary clock source. A delay of approximately
10 µs is required between the wake event and code
execution starts. This is required to allow the CPU to
become read y to ex ecut e in stru cti ons. A ft er th e wake up, the OSTS bit remai ns set. Th e IDLEN an d SCS bit s
are not affected by the wake-up (see Figure3-4).
oscillator.
PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEP instruction. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).
FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE
Q1
Q4
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
Q1
Q2
Q3
PC PC + 2
FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
Q1 Q3 Q4
CPU Start-up Delay
PC
Wake Event
Q2
PC + 2
2004 Microchip Technology Inc. DS39605C-page 23
PIC18F1220/1320
3.3.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled, but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the Idle bit,
modifying bits, SCS1:SCS0 = 01 and executing a
SLEEP instruction. When the clock source is switched
(see Figure 3-5) to the Timer1 oscillator, the primary
oscillator is shut down, th e OSTS bit is cleared and the
T1RUN bit is set.
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE mod e.
When a wake event occ urs, the pe ripherals continue to
be clocked from the Timer1 oscillator. After a 10 µs
delay following the wake event, the CPU begins executing code, be ing clocked b y the T imer1 oscillator. The
microcontroller operates in SEC_RUN mode until the
primary clock becomes ready. When the primary clock
becomes ready , a clock switchb ack to the prim ary clock
occurs (see Figure3-6). When the clock switch is c omplete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up.
The Timer1 oscillator continues to run.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the os cill at or ha s start ed; in su ch si tuations, initial oscillator operation is far
from stable and unpredictable operation
may result.
FIGURE 3-5: TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
Q4Q3Q2
Q1
Q1
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
12345678
Clock Transition
PC + 2PC
FIGURE 3-6: TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Q2
Q3 Q4
T1OSI
OSC1
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
Q1
PC PC + 2
TOST
Q2
(1)
Q3
TPLL
Q1
Q4
(1)
12345678
Clock Transition
PC + 4
Q1
Q2
PC + 6
Q3
Wake from Interrupt Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39605C-page 24 2004 Microchip Technology Inc.
OSTS bit Set
PIC18F1220/1320
3.3.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is di sabled, but the peripherals continue to b e c loc ke d fro m t he internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power cons ervation during Idl e periods.
This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before exec uti ng th e SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.
If the IRCF bits are set to a non-zero value (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
instruction was executed and the INTOSC source was
already stable, the IO FS bi t will rema in s et. If th e IRCF
bits are all clear, the INTOSC output is not enabled and
the IOFS bit will rem ain clear; there will be no ind ication
of the current clock source.
When a wake event occ urs, the pe ripherals continue to
be clocked from the INTOSC multi ple xe r. After a 10 µs
delay following the wake event, the CPU begins exe-
cuting code, being clo cked by the IN T OSC multi plexe r.
The microcontroller operates in RC_RUN mode until
the primary clock becomes ready. When the primary
clock becomes ready, a clock switchback to the primary
clock occurs (see Figu re 3-8). When the clock switch is
complete, the IOFS bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock.
The IDLEN and SCS b it s a re not affected by the wake-
up. The INTRC source will continue to run if either the
WDT or the Fail-Safe Clock Monitor is enabled.
INTOSC source stabilizes. If the IRCF bits were
previously at a non-zero value before the SLEEP
FIGURE 3-7: TIMING TRANSITION TO RC_IDLE MODE
Q4Q3Q2
Q1
INTRC
OSC1
Q1
12345678
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC + 2PC
FIGURE 3-8: TIMING TRANSITION FOR W AKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q3 Q4
Q1
Q4
INTOSC
Multiplexer
OSC1
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC PC + 2
Wake from Interrupt Event
Q1
TOST
Q2
(1)
Q3
(1)
TPLL
OSTS bit Set
12345678
Clock Transition
PC + 4
Q1
Q4
Q2
Q2
PC + 6
Q3
2004 Microchip Technology Inc. DS39605C-page 25
PIC18F1220/1320
3.4 Run Modes
If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While these operating mo des may not aff ord the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
greater than the primary clock.
Wake-up from a power managed Run mode can be
triggered by an interrupt, or any Reset, to return to full
power operation. As the CPU i s exec uti ng c od e in Run
modes, several additional exits from Run modes are
possible. They inclu de exit to Slee p mode, exit to a correspondin g Idle mode and exit by execut ing a RESET
instruction. While the device is in any of the power
managed Run modes, a WDT time-out will result in a
WDT Reset.
3.4.1 PRI_RUN MODE
The PRI_RUN mode is the normal full power execution
mode. If the SLEEP instruction is never executed, the
microcontroller opera tes in this m ode (a SLEEP instruction is executed to enter all other power managed
modes). All other power managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.
There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section 2.7.1
“Oscillator Control Register”).
3.4.2 SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the T imer1 osci llator. This gives users the
option of lower power c onsumption w hile still using a
high accuracy clock source.
SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01 and executing a SLEEP
instruction. The system clock source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
Note: The Timer1 oscillator should already be
running prior to entering SEC_RU N mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, system clocks will be delayed
until the oscillator has started; in such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
When a wake event occurs, the peripherals and CPU
continue to be clocked from the Timer1 oscillator while
the primary clock is started. When the primary clock
becomes ready , a clock switchb ack to the prim ary clock
occurs (see Figure3-6). When the clock switch is c omplete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up.
The Timer1 oscillator continues to run.
Firmware can force an exit from SEC_RUN mode. By
clearing th e T1OSCEN bit (T1CON<3>), an exit from
SEC_RUN back to normal full power operation is triggered. The Timer1 oscillator will continue to run and
provide the system clock, even though the T1OSCEN
bit is cleared. The primary clock is started. When the
primary clock becomes ready, a clock switchback to the
primary clock occurs (see Figure 3-6). When the clock
switch is compl ete, the T imer1 oscillat or is disabled , the
T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN
and SCS bits are not affected by the wake-up.
FIGURE 3-9: TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Q4Q3Q2
Q1
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
DS39605C-page 26 2004 Microchip Technology Inc.
Q1
12345678
Clock Transition
PC + 2PC
Q2
Q4Q3
Q1
Q2
Q3
PC + 2
PIC18F1220/1320
3.4.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications whic h are not h ighly tim ing sensiti ve, or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either of the INTIO1 or INTIO2 os cillator s), there
are no distinguishable differences between PRI_RUN
and RC_RUN modes during execution. However, a
clock switch delay will occur during entry to and exit
from RC_RUN mode. Therefore, if the primary clock
source is the internal oscillator block, the use of
RC_RUN mode is not recommended.
This mode is ente red by c lea rin g th e IDLEN b it, se ttin g
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The IRCF bits may select the clock
frequency before the SLEEP instruction is executed.
When the clock source is switched to the INTOSC
multiplexer (see Figure 3-10), the primary oscillator is
shut down and the OSTS bit is cleared.
The IRCF bits may be modified at any time to immediately change the system clock speed. Executing a
SLEEP instruction is not required to select a new clock
frequency from the INTOSC multiplexer.
Note: Caution should be used when modi fy ing a
single IRCF bit. If V
DD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
If the IRCF bits are all clear, the INTOSC output is not
enabled and the IOFS bit wi ll remain clear; there will be
no indication of the current clock source. The INTRC
source is providing the system clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC out put becom es stab le. Clocks to
the system continue while the INTOSC source
stabilizes, in approximately 1ms.
If the IRCF bits were previously at a non-zero value
before the SLEEP instruction was executed and the
INTOSC source was already stable, the IOFS bit will
remain set.
When a wake event occurs , the system conti nues to be
clocked from the IN TO SC multiple xer while the primar y
clock is started. When the primary clock becomes
ready, a clock switch to the primary clock occurs (see
Figure 3-8). When the clock switch is complete, the
IOFS bit is cleared, the O STS bit is se t and the prim ary
clock is providing the system clock. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enab led .
FIGURE 3-10: TIMING TRANSITION TO RC_RUN MODE
Q3Q2Q1
Q4
12345678
Clock Transition
PC + 2PC
INTRC
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Q4
Q3Q2Q1 Q4 Q2Q1 Q3
PC + 4
2004 Microchip Technology Inc. DS39605C-page 27
PIC18F1220/1320
3.4.4 EXIT TO IDLE MODE
An exit from a power managed Run mode to its
corresponding Idle mode is executed by setting the
IDLEN bit and executing a SLEEP instruction. The CPU
is halted at the beginning of the instruction follo wing the
SLEEP instruction. There are no changes to any of the
clock source status bits (OSTS, IOFS or T1RUN).
While the CPU is halte d, the periphe rals c ontin ue to b e
clocked from the previously selected clock source.
3.4.5 EXIT TO SLEEP MODE
An exit from a power managed Run mode to Sleep
mode is executed by clearing the IDLEN and
SCS1:SCS0 bits and executing a SLEEP instruction.
The code is no diff erent than the me thod used to invoke
Sleep mode from the normal operating (full power)
mode.
The primary clock and internal oscillator block are
disabled. The INTRC will continue to operate if the
WDT is enabled. The Timer1 oscillator will continue to
run, if enabled in the T1CON register (Register 12-1).
All clock source status bits are cleared (OSTS, IOFS
and T1RUN).
3.5 Wake from Power Managed Modes
An exit from any of the power managed modes is triggered by an interrupt, a Reset or a WDT time-out. This
section discusses the triggers that cause exits from
power managed modes. The clocking subsystem
actions are discussed in each of the power managed
modes (see Sections3.2 through 3.4).
Note: If application code is timing sensitive, it
should wait for the OSTS bi t to become set
before continuing. Use the interval during
the low-power exit sequence (before
OSTS is set) to perform timing insensitive
“housekeeping” tasks.
Device behavior during Low-Power mode exits is
summarized in Table 3-3.
3.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit a power managed mode and resume full
power operation. To enable this functionality, an interrupt source must be e nab le d by s etti ng its enable bit in
one of the INTCON or PIE register s. The exit sequenc e
is initiated when the corresponding interrupt flag bit is
set. On all exits from Low-Power mode by interrupt,
code execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
DS39605C-page 28 2004 Microchip Technology Inc.
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