MICROCHIP PIC18C601, PIC18C801 Technical data

PIC18C601/801

High-Performance ROM-less Microcontrollers

with External Memory Bus

High Performance RISC CPU:

• C compiler op timized architecture ins truction set

• Linear program memory addressing up to 2 Mbytes

• Linear data memory addressing to 4 Kbytes

External Program Memory

(bytes)

On-Chip

Maximum Single Word Instructions

Device

PIC18C601 256K 128K 1.5K PIC18C801 2M 1M 1.5K

• Up to 160 ns instruction cycle:

- DC - 25 MHz clock input

- 4 MHz - 6 MHz clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

• 8 x 8 Single C y cle Hardware Multiplier

Maximum

Addressing

On-Chip

RAM (bytes)

Peripheral Features:

• High current sink/source 25 mA/25 mA

• Up to 47 I/O pins with individual direction control

• Three external interrupt pins

•Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler

•Timer1 module: 16-bit timer/counter (time-base for CCP)

•Timer2 module: 8-bit timer/counter with 8-bit period register

•Timer3 module: 16-bit timer/counter

• Secondary oscillator clock option - Timer1/Timer3

• Two Capture/Compare/PWM (CCP) modules CCP pins can be configured as:

- Capture input: 16-bit, max. resolution 10 ns

- Compare is 16-bit, max. resolution 160 ns (TCY)

- PWM output: PWM resolution is 1- to 10-bit

Max. PWM freq. @:

8-bit resolution = 99 kHz 10-bit resolution = 24.4 kHz

• Master Synchronous Serial Port (MSSP) with two modes of operation:

- 3-wire SPI™ (Supports all 4 SPI modes)

-I

C™ Master and Slave mode

• Addressable USART module: Supports Interrupt on Address bit

Advanced Analog Features:

• 10-bit Analog-to-Digital Converter module (A/D) with:

- Fast sampling rate

- Conversion available during SLEEP

- DNL = ±1 LSb, INL = ±1 LSb

- Up to 12 channels available

• Programmable Low Voltage Detection (LVD) module

- Supports interrupt on Low Voltage Detection

Special Microcontroller Features:

• Power-on Reset (POR), Power-up T imer (PWRT),

and Oscillator S tart-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator

• On-chip Boot RAM for boot loader application

• 8-bit or 16-bit external memory interface modes

• Up to two software programmable chip select sig-

nals (CS1

• One programmable chip I/O select signal (CSIO

for memory mapped I/O expansion

• Power saving SLEEP mode

• Different oscillator options, including:

- 4X Phase Lock Loop (of primary oscillator)

- Secondary Oscillator (32 kHz) clock input

and CS2)

CMOS Technology:

• Low power, high speed CMOS technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

)

 2001 Microchip Technology Inc. Advance Information DS39541A-page 1

PIC18C601/801

Pin Diagrams

64-Pin TQFP

RE2/AD10

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

RE1/AD9 RE0/AD8 RG0/ALE

RG1/OE

RG2/WRL

RG3/WRH

MCLR/VPP

RG4/BA0

VDD

RF7/UB

RF6/LB

RF5/CS1

RF4/A16

RF3/CSIO

RF2/AN7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

RE3/AD11

RE4/AD12

RE5/AD13

RE6/AD14

RE7/AD15

RD0/AD0

VDDVSS

RD1/AD1

PIC18C601

RD2/AD2

RD3/AD3

RD4/AD4

RD5/AD5

RD6/AD6

RD7/AD7

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 V

OSC2/CLKO OSC1/CLKI

V RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

RF0/AN5

RF1/AN6

REF

RA2/AN2/V

RA3/AN3/V

RA1/AN1

RA0/AN0

RA4/T0CKI

RC1/T1OSI

/AN4/LVDIN

RA5/SS

RC6/TX/CK

RC0/T1OSO/T13CKI

RC7/RX/DT

DS39541A-page 2 Advance Information  2001 Microchip Technology Inc.

Pin Diagrams (Cont.’d)

68-Pin PLCC

RE1/AD9 RE0/AD8 RG0/ALE

RG1/OE

RG2/WRL

RG3/WRH

MCLR/VPP

RG4/BA0

VDD

RF7/UB

RF6/LB

RF5/CS1

RF4/A16

RF3/CSIO

RF2/AN7

RE2/AD10

RE3/AD11

RE4/AD12

RE5/AD13

RE6/AD14

RE7/AD15

9 8 7 6 5 4 3 2 1 6867666564636261

10 11

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

PIC18C601

RD0/AD0

VDDV

RD1/AD1

RD2/AD2

RD3/AD3

PIC18C601/801

RD4/AD4

RD5/AD5

RD6/AD6

RD7/AD7

60 59

58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

RB0/INT0 RB1/INT1 RB2/INT2

RB3/CCP2

RB4 RB5 RB6

OSC2/CLKO OSC1/CLKI

V RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1

2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

RF1/AN6

RF0/AN5

REF

RA1/AN1

RA2/AN2/V

RA3/AN3/V

RA0/AN0

RA4/T0CKI

RC1/T1OSI

/AN4/LVDIN

RA5/SS

RC6/TX/CK

RC0/T1OSO/T13CKI

RC7/RX/DT

 2001 Microchip Technology Inc. Advance Information DS39541A-page 3

PIC18C601/801

Pin Diagrams (Cont.’d)

80-Pin TQFP

RH0/A16

RH1/A17

RH2/A18 RH3/A19

RE1/AD9 RE0/AD8 RG0/ALE

RG1/OE

RG2/WRL

RG3/WRH

MCLR/VPP

RG4/BA0

VDD

RF7/UB

RF6/LB RF5/CS1 RF4/CS2

RF3/CSIO

RF2/AN7 RH4/AN8 RH5/AN9

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

18 19 20

RE2/AD10

RE3/AD11

77 76 75

RE4/AD12

RE5/AD13

RE6/AD14

RE7/AD15

RD0/AD0

VDDVSS

RD1/AD1

PIC18C801

RD2/AD2

RD3/AD3

RD4/AD4

RD5/AD5

RD6/AD6

RD7/AD7

RJ0/D7

RJ1/D6

68 67 66 6572 71 70 6974 73

64 63 62 61

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

RJ5/D5 RJ4/D4

RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 V

OSC2/CLKO OSC1/CLKI

V RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 RJ3/D3 RJ2/D2

21 22 23 24 25 26 27 28 29 30 31 32

RA1/AN1

RA0/AN0

RH6/AN10

RH7/AN11

AVSS

AVDD

RF0/AN5

RF1/AN6

RA2/AN2/VREF-

RA3/AN3/VREF+

33 34

VDD

35 36 38

RA4/T0CKI

/AN4/LVDIN

RA5/SS

RC1/T1OSI

RC6/TX/CK

RC0/T1OSO/T13CKI

RC7/RX/DT

RJ0/D0

RJ1/D1

DS39541A-page 4 Advance Information  2001 Microchip Technology Inc.

Pin Diagrams (Cont.’d)

84-Pin PLCC

RH1/A17

RH0/A16

RE2/AD10

RE3/AD11

RE4/AD12

RE5/AD13

RE6/AD14

RE7/AD15

RD0/AD0

VSS

PIC18C601/801

RD1/AD1

RD2/AD2

RD3/AD3

RD4/AD4

RD5/AD5

RD6/AD6

RD7/AD7

RJ7/D7

RJ6/D6

RH2/A18

RH3/A19 RE1/AD9 RE0/AD8 RG0/ALE

RG1/OE

RG2/WRL RG3/WRH MCLR/VPP

RG4/BA0

VDD

RF7/UB

RF6/LB RF5/CS1 RF4/CS2

RF3/CSIO

RF2/AN7

RH4/AN8 RH5/AN9

987654321

10 12 13 14 15 16 17 18 19 20 21 22 23 24

25 26 27 28 29 30 31 32

3435 36 37 38 39 40 41 42 43

AVSS

RF1/AN6

RH7/AN11

RF0/AN5

RH6/AN10

PIC18C801

REF-

RA2/AN2/V

RA3/AN3/VREF+

RA1/AN1

RA0/AN0

83 82 81

84 75

VDD

797877

4645

4948

RA4/T0CKI

RC1/T1OSI

/AN4/LVDIN

RA5/SS

RJ0/D0

RC6/TX/CK

RC7/RX/DT

RC0/T1OSO/T13CKI

74 73 72 71 70 69 68 67 66 65 64 63

62 61 60

59 58 57 56 55 54

5352

RJ1/D1

RJ5/D5 RJ4/D4

RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 V

OSC2/CLKO OSC1/CLKI

VDD RB7 RC5/SDO

RC4/SDI/SDA RC3/SCK/SCL

RC2/CCP1 RJ3/D3

RJ2/D2

 2001 Microchip Technology Inc. Advance Information DS39541A-page 5

PIC18C601/801

1.0 Device Overview............................................ ...... ...... ..... ...... ...... .........................................................................9

2.0 Oscillator Configurations....................................................................................................................................21

3.0 RESET...............................................................................................................................................................29

4.0 Memory Organization........................................................................................................................................39

5.0 External Memory Interface............. ..... ........................................ ..... .................................... ..............................63

6.0 Table Reads/Table Writes.................................................................................................................................73

7.0 8 X 8 Hardware Multiplier..................................................................................................................................85

8.0 Interrupts............................................................................................................................................................89

9.0 I/O Ports...........................................................................................................................................................103

10.0 Timer0 Module.................................................................................................................................................127

11.0 Timer1 Module.................................................................................................................................................130

12.0 Timer2 Module.................................................................................................................................................135

13.0 Timer3 Module.................................................................................................................................................137

14.0 Capture/Compare/PWM (CCP) Modules.........................................................................................................141

15.0 Master Synchronous Serial Port (MSSP) Module............................................................................................149

16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) .....................................177

17.0 10-bit Analog-to-Digital Converter (A/D) Module.............................................................................................193

18.0 Low Voltage Detect..........................................................................................................................................203

19.0 Special Features of the CPU...........................................................................................................................207

20.0 Instruction Set Summary .................................................................................................................................215

21.0 Development Support......................................................................................................................................259

22.0 Electrical Characteristics............... ..... ........................................ ..... ...... ..........................................................265

23.0 DC and AC Characteristics Graphs and Tables..............................................................................................295

24.0 Packaging Information.....................................................................................................................................297

Appendix A: Data Sheet Revision History..................................................................................................................303

Appendix B: Device Differences ................................................................................................................................303

Appendix C: Device Migrations..................................................................................................................................304

Appendix D: Migrating from other PICmicro Devices.................................................................................................304

Appendix E: Development Tool Version Requirements.............................................................................................305

Index ...........................................................................................................................................................................307

On-Line Support..........................................................................................................................................................315

Reader Response.......................................................................................................................................................316

Product Identification System......................................................................................................................................317

DS39541A-page 6 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

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Errata

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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Customer Notification System

 2001 Microchip Technology Inc. Advance Information DS39541A-page 7

PIC18C601/801

NOTES:

DS39541A-page 8 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r the following two devices:

1. PIC18C601

2. PIC18C801 The PIC18C601 is ava ilable in 64- pin TQFP and 6 8-pin

PLCC packages. The PIC18C801 is av ailable in 80-pin TQFP and 84-pin PLCC packages.

An overview of features is shown in Table 1-1. Device block diagrams are provided in Figure 1-1 for

the 64/68-p in confi gurati on, and Figure 1-2 fo r the 80/ 84-pin configuration. The pinouts for both packages are listed in Table 1-2.

TABLE 1-1: DEVICE FEATURES

Features PIC18C601 PIC18C801

Operating Frequency DC - 25 MHz DC - 25 MHz External

Program Memory Data Memory (Bytes) 1536 1536

Interrupt Sources 15 15 I/O Ports Ports A - G Ports A - H, J Timers 4 4 Capture/Compare/PWM modules 2 2

Serial Communications 10-bit Analog-to-Digital Module 8 input channels 12 input channels

RESETS (and Delays)

Programmable Low Voltage Detect Yes Yes 8-bit External Memory Interface Yes Yes 8-bit De-multiplexed External

Memory Interface 16-bit External Memory Interfaces Yes Yes

On-chip Chip Select Signals CS1 On-chip I/O Chip Select Signal Yes Yes Instruction Set 75 Instructions 75 Instructions

Packages

Bytes 256K 2M Max. # of Single Word

Instructions

Addressable USART

RESET Instruction, Stack Full,

Stack Underflow (PWRT, OST)

128K 1M

MSSP,

Addressable USART

POR,

RESET Instruction, Stack Full,

Stack Underflow (PWRT, OST)

No Yes

64-pin TQFP 68-pin PLCC

MSSP,

POR,

CS1, CS2

80-pin TQFP 84-pin PLCC

 2001 Microchip Technology Inc. Advance Information DS39541A-page 9

PIC18C601/801

FIGURE 1-1: PIC18C601 BLOCK DIAGRAM

AD7:AD0

Table Pointer<21>

inc/dec logic

Address Latch

Program Memory

(up to 256 Kbytes)

Data Latch

System Bus Interface

Table Latch

A16, AD15:AD8

Instruction

Decode &

Control

OSC2/CLKO OSC1/CLKI

T1OSI T1OSO

Timing

Generation

Timer0 Timer1 Timer2

PCLATU

PCLATH

PCH PCL

PCU Program Counter

31 Level Stack

ROM Latch

Power-up

Timer

Oscillator

Start-upTimer

Power-on

Reset

Watchdog

Timer

Low Voltage

Detect

MCLR

VDD, VSS

Decode

BITOP

BSR

Data Bus<8>

Data Latch

Data RAM

1 Kbyte

Address Latch

Address<12> 12 4

Bank0,F

FSR0 FSR1 FSR2

inc/dec

logic

PRODLPRODH

8 x 8 Multiply

WREG

ALU<8>

Timer3

PORTA

RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS

/LVDIN

PORTB

RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6

RB7

PORTC

RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1

PORTD

RD7:RD0/AD7:AD0

PORTE

RE7:RE0/AD15:AD8

PORTF

RF0/AN5 RF1/AN6 RF2/AN7 RF3/CSIO RF4/A16 RF5/CS1 RF6/LB RF7/UB

PORTG

RG0/ALE RG1/OE RG2/WRL RG3/WRH RG4/BA0

CCP1

CCP2

Synchronous

Serial Port

USART1

10-bit A/D

DS39541A-page 10 Advance Information  2001 Microchip Technology Inc.

FIGURE 1-2: PIC18C801 BLOCK DIAGRAM

AD7:AD0

TablePointer<21>

inc/dec logic

Address Latch

Program Memory

(up to 2 Mbytes)

Data Latch

System Bus Interface

Table Latch

A19:A16, AD15:AD0

Instruction

Decode &

Control

OSC2/CLKO OSC1/CLKI

T1OSI T1OSO

Timing

Generation

Timer0 Timer1 Timer2

CCP1

CCP2

PCLATU

PCLATH

PCH PCL

PCU

Program Counter

31 Level Stack

ROM Latch

Power-up

Timer

Oscillator

Start-upTimer

Power-on

Reset

Watchdog

Timer

Low Voltage

Detect

MCLR

VDD, VSS

Synchronous

Serial Port

Decode

BITOP

BSR

Data Bus<8>

Data Latch

Data RAM

1 Kbyte

Address Latch

Address<12> 12 4

Bank0,F

FSR0 FSR1 FSR2

inc/dec

logic

PRODLPRODH

8 x 8 Multiply

WREG

ALU<8>

Timer3

USART1

PIC18C601/801

PORTA

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

PORTH

PORTJ

RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS

RB0/INT0

RB1/INT1

RB2/INT2

RB3/CCP2

RB4

RB5

RB6 RB7

RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1

RD7:RD0/AD7:AD0

RE7:RE0/AD15:AD8

RF0/AN5 RF1/AN6 RF2/AN7 RF3/CSIO RF4/CS2 RF5/CS1 RF6/LB RF7/UB

RG0/ALE RG1/OE RG2/WRL RG3/WRH RG4/BA0

RH3:RH0/A19:A16

RH4/AN8 RH5/AN9 RH6/AN10 RH7/AN11

/LVDIN

RJ7:RJ0/D7:D0

10-bit A/D

 2001 Microchip Technology Inc. Advance Information DS39541A-page 11

PIC18C601/801

TABLE 1-2: PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

MCLR

/VPP

MCLR

VPP

OSC1/CLKI

OSC1

CLKI

OSC2/CLKO

OSC2

CLKO

Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to V

PIC18C601 PIC18C801

TQFP PLCC TQFP PLCC Description

716920

— 1, 18,

35, 52

39 50 49 62

40 51 50 63

— 1, 22,

43, 64

Type

——These pins should be left

Buffer

Type

IICMOS/ST

ST Master clear (RESET) input. This pin is

CMOS

—

an active low RESET to the device. Programming voltage in put.

unconnected.

Oscillator crystal inp ut or ex te rnal clock source input. ST buffer when in RC mode. Otherwise CMOS. External clock source inp ut. Always associated with pi n f unction OSC1 (see OSC1/CLKI, OSC2/CLKO pins).

Oscillator crystal outp ut . Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin ou tp ut s C LKO, which has 1/4 the frequency of OSC1 an d den ot es the instruction cycle rate.

DD)

DS39541A-page 12 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS

Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output

REF-

RA2 AN2

REF-

RA3 AN3

REF+

RA4

T0CKI

/LVDIN RA5 AN4 SS LVDIN

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to V

PIC18C601 PIC18C801

TQFP PLCC TQFP PLCC Description

24 34 30 42

23 33 29 41

22 32 28 40

21 31 27 39

28 39 34 47

27 38 33 46

Type

I/O

Buffer

Type

PORTA is a bi-directional I/O port.

TTL

Analog

TTL

Analog

TTL

Analog

TTL

Analog

ST/OD

I I I

TTL

Analog

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (L ow) inp ut .

Digital I/O. Analog input 3. A/D reference voltage (High) input.

Digital I/O – Open drain when configured as output. Timer0 external clock input.

Digital I/O. Analog input 4. SPI slave select input. Low voltage detect input .

DD)

 2001 Microchip Technology Inc. Advance Information DS39541A-page 13

PIC18C601/801

TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/INT0

RB0 INT0

RB1/INT1

RB1 INT1

RB2/INT2

RB2 INT2

RB3/CCP2

RB3 CCP2

RB4 44 56 54 68 I/O TTL Digital I/O, Interrupt-on- change pin. RB5 43 55 53 67 I/O TTL Digital I/O, Interrupt-on- change pin. RB6 42545266I/OITTL

RB7 37484760I/O

Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to V

PIC18C601 PIC18C801

TQFP PLCC TQFP PLCC Description

48 60 58 72

47 59 57 71

46 58 56 70

45 57 55 69

Type

I/O

I/O I/O

I/O

Buffer

Type

PORTB is a bi-directional I/O port. PORTB can be softw are programmed for internal weak pull-ups on all inputs.

TTL

Digital I/O. External interrupt 0.

Digital I/O. External interrupt 1.

Digital I/O. External interrupt 2.

Digital I/O. Capture2 input, Comp ar e2 output, PWM2 output.

Digital I/O, Interrupt-on-change pin. ICSP programming clock.

Digital I/O, Interrupt-on-change pin. ICSP programming data.

DD)

DS39541A-page 14 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC0/T1OSO/T13CKI

RC0 T1OSO T13CKI

RC1/T1OSI

RC1 T1OSI

RC2/CCP1

RC2 CCP1

RC3/SCK/SCL

RC3 SCK

SCL

RC4/SDI/SDA

RC4 SDI SDA

RC5/SDO

RC5 SDO

RC6/TX/CK

RC6 TX CK

RC7/RX/DT

RC7 RX DT

Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to V

PIC18C601 PIC18C801

TQFP PLCC TQFP PLCC Description

30 41 36 49

29 40 35 48

33 44 43 56

34 45 44 57

35 46 45 58

36 47 46 59

31 42 37 50

32 43 38 51

Type

I/O

I/O I/O

I/O

Buffer

Type

PORTC is a bi-directional I/O port.

—

CMOS

ST ST

ST ST ST

—

ST ST ST

Digital I/O. Timer1 oscillato r output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input.

Digital I/O. Capture1 input/Com par e1 output/PWM1 output .

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. SPI data in.

C data I/O.

Digital I/O. SPI data out.

Digital I/O. USART asynchronous transmit. USART synchronous clock.

Digital I/O. USART asynchronous receive. USART synchronous data.

C mode.

DD)

 2001 Microchip Technology Inc. Advance Information DS39541A-page 15

PIC18C601/801

TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RD0/AD0

RD0 AD0

RD1/AD1

RD1 AD1

RD2/AD2

RD2 AD2

RD3/AD3

RD3 AD3

RD4/AD4

RD4 AD4

RD5/AD5

RD5 AD5

RD6/AD6

RD6 AD6

RD7/AD7

RD7 AD7

Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to V

PIC18C601 PIC18C801

TQFP PLCC TQFP PLCC Description

583723

55 67 69 83

54 66 68 82

53 65 67 81

52 64 66 80

51 63 65 79

50 62 64 78

49 61 63 77

Type

I/O I/O

Buffer

Type

TTL

PORTD is a bi-directional I/O port. These pins have TTL input buffers wh en external memory is enabled.

Digital I/O. External memory address/data 0.

Digital I/O. External memory address/data 1.

Digital I/O. External memory address/data 2.

Digital I/O. External memory address/data 3.

Digital I/O. External memory address/data 4.

Digital I/O. External memory address/data 5.

Digital I/O. External memory address/data 6.

Digital I/O. External memory address/data 7.

DD)

DS39541A-page 16 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RE0/AD8

RE0 AD8

RE1/AD9

RE1 AD9

RE2/AD10

RE2 AD10

RE3/AD11

RE3 AD11

RE4/AD12

RE4 AD12

RE5/AD13

RE5 AD13

RE6/AD14

RE6 AD14

RE7/AD15

RE7 AD15

Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to V

PIC18C601 PIC18C801

TQFP PLCC TQFP PLCC Description

211415

110314

649789

638778

627767

616756

605745

594734

Type

I/O I/O

Buffer

Type

TTL

ST ST

PORTE is a bi-directional I/O port.

Digital I/O. External memory address/data 8.

Digital I/O. External memory address/data 9.

Digital I/O. External memory address/data 10.

Digital I/O. External memory address /d at a 11.

Digital I/O. External memory address/data 12.

Digital I/O. External memory address/data 13.

Digital I/O. External memory address/data 14.

Digital I/O. External memory address/data 15.

DD)

 2001 Microchip Technology Inc. Advance Information DS39541A-page 17

PIC18C601/801

TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RF0/AN5

RF0 AN5

RF1/AN6

RF1 AN6

RF2/AN7

RF2 AN7

RF3/CSIO

RF3 CSIO

RF4/A16 RF4/CS2

RF4 A16 CS2

RF5/CS1

RF5 CS1

RF6/LB

RF6 LB

RF7/UB

RF7 UB

Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to V

PIC18C601 PIC18C801

TQFP PLCC TQFP PLCC Description

18 28 24 36

17 27 23 35

16 26 18 30

15 25 17 29

—

13 23 15 27

12 22 14 26

11 21 13 25

—

Type

I/O

I/O I/O

I/O

Buffer

Type

PORTF is a bi-directional I/O port.

Analog

ST ST

TTL

Digital I/O. Analog input 5.

Digital I/O. Analog input 6.

Digital I/O. Analog input 7.

Digital I/O. System bus chip select I/O.

Digital I/O. External memory address 16. Chip select 2.

Digital I/O. Chip select 1.

Digital I/O. Low byte select signal for external memory interface.

Digital I/O. High byte select signal for external memory interface.

DD)

DS39541A-page 18 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RG0/ALE

RG0 ALE

RG1/OE

RG1 OE

RG2/WRL

RG2 WRL

RG3/WRH

RG3 WRH

RG4/BA0

RG4 BA0

RH0/A16

RH0 A16

RH1/A17

RH1 A17

RH2/A18

RH2 A18

RH3/A19

RH3 A19

RH4/AN8

RH4 AN8

RH5/AN9

RH5 AN9

RH6/AN10

RH6 AN10

RH7/AN11

RH7 AN11

Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to V

PIC18C601 PIC18C801

TQFP PLCC TQFP PLCC Description

312516

413617

514718

615819

8 171021

——79 10

——80 11

—— 112

—— 213

——19 31

——20 32

——21 33

——22 34

Type

I/O

Buffer

Type

PORTG is a bi-directional I/O port.

TTL

—

Analog

Digital I/O. Address Lat ch Enable.

Digital I/O. Output Enable.

Digital I/O. Write Low control.

Digital I/O. Write High control.

Digital I/O. System bus byte addres s 0.

PORTH is a bi-directional I/O port.

Digital I/O. External memory address 16.

Digital I/O. External memory address 17.

Digital I/O. External memory address 18.

Digital I/O. External memory address 19.

Digital I/O. Analog input 8.

Digital I/O. Analog input 9.

Digital I/O. Analog input 10.

Digital I/O. Analog input 11.

DD)

 2001 Microchip Technology Inc. Advance Information DS39541A-page 19

PIC18C601/801

TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RJ0/D0

RJ0 D0

RJ1/D1

RJ1 D1

RJ2/D2

RJ2 D2

RJ3/D3

RJ3 D3

RJ4/D4

RJ4 D4

RJ5/D5

RJ5 D5

RJ6/D6

RJ6 D6

RJ7/D7

RJ7 D7

SS 9, 25,

DD 10,26,

VSS 20 30 26 38 P — Ground reference for analog modules.

A A

VDD 19 29 25 37 P — Positive supply for analog modules.

Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to V

PIC18C601 PIC18C801

TQFP PLCC TQFP PLCC Description

——39 52

——40 53

——41 54

——42 55

——59 73

——60 74

——61 75

——62 76

41, 56

38, 57

19, 36,

53, 68

2, 20,

37, 49

11,31, 51, 70

12,32, 48, 71

23, 44,

65, 84

2, 24,

45, 61

Type

I/O I/O

Buffer

Type

PORTJ is a bi-directional I/O port.

TTL

P — Ground reference for logic and I/O pins.

P — Positive supply fo r logic and I/O pins.

Digital I/O. System bus data bit 0.

Digital I/O. System bus data bit 1.

Digital I/O. System bus data bit 2.

Digital I/O. System bus data bit 3.

Digital I/O. System bus data bit 4.

Digital I/O. System bus data bit 5.

Digital I/O. System bus data bit 6.

Digital I/O. System bus data bit 7.

DD)

DS39541A-page 20 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

PIC18C601/801 can be operated in one of four o sc ill ator modes, programmable by configuration bits FOSC1:FOSC0 in CONFIG1H register:

1. LP Low Power Crystal

2. HS High Speed Crys tal/Resonator

3. RC External Resistor/Capacitor

4. EC External Clock

2.2 Crystal Oscillator/Ceramic Resonators

In LP or HS oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. An external c lock so urce may also be connecte d to the OSC1 pin, as shown in Figure 2-3 and Figure 2-4.

PIC18C601/801 oscillator design requires the use of a parallel cut crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s specifications.

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION (HS OR LP OSC CONFIGURATION)

(1)

Note 1: See Table2-1 and Table 2-2 for recom-

2: A series resistor (R

3: R

OSC1

XTAL

(2)

OSC2

mended values of C1 and C2.

strip cut crystals.

F varies with the crystal chosen.

(3)

PIC18C601/801

S) may be required for AT

SLEEP

Internal Logic

 2001 Microchip Technology Inc. Advance Information DS39541A-page 21

PIC18C601/801

TABLE 2-1: CERAMIC RESONATORS

Ranges Tested:

Mode Freq. OSC1 OSC2

HS 8.0 MHz

16.0 MHz

20.0 MHz

25.0 MHz

10 - 68 pF 10 - 22 pF TBD TBD

HS+PLL 4.0 MHz TBD TBD

These values are for design guidance only. See notes on this page.

Resonators Used:

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5% All resonators used did not hav e bu ilt-in capacitors.

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc Type

Crystal

Freq.

LP 32.0 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

HS 4.0 MHz 15 pF 15 pF

8.0 MHz 15-33 pF 15-33 pF

20.0 MHz 15-33 pF 15-33 pF

25.0 MHz TBD TBD

HS+PLL 4.0 MHz 15 pF 15 pF

These values are for design guidance only. See notes on this page.

32.0 kHz Epson C-001R32.768K-A ± 20 PPM 200 kHz STD XTL 200.000kHz ± 20 PPM

1.0 MHz ECS ECS-10-13-1 ± 50 PPM

4.0 MHz ECS ECS-40-20-1 ± 50 PPM

8.0 MHz EPSON CA-301 8.000M-C ± 30 PPM

20.0 MHz EPSON CA-301 20.000M-C ± 30 PPM

Cap. Range C1Cap. Range

Crystals Used

Note 1: Recommended values of C1 and C2 are

identical to the ranges tested (Table 2-1).

2: Higher capacitance increases the stability

of the oscillator, but also increases the start-up time.

3: Since each resonator/crystal has its own

characteristics, the u ser shoul d consult th e resonator/crystal manufacturer for appropriate values of external components.

4: Rs may be required in HS mode to avoid

overdriving crystals with low drive level specification.

2.3 RC Oscillator

For timing insensitive applications, the "RC" oscillator mode offers additional cost savings. The RC oscillator frequency is a function of the supply volta ge, t he re sis -

EXT) and capacitor (CEXT) values and the operat-

tor (R ing temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process paramete r variatio n. Further more, the d ifference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low

EXT values. The user also needs to take into account

C variation due t o t ole ranc e of ex ter nal R an d C c om ponents used. Figu re 2-2 shows how the RC comb inatio n is connected.

In the RC oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r logic.

FIGURE 2-2: RC OSCILLATOR MODE

VDD

REXT

OSC1

CEXT

VSS

OSC/4

or I/O

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

OSC2/CLKO

EXT > 20pF

PIC18C601/801

Internal

Clock

DS39541A-page 22 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

2.4 External Clock Input

The EC oscillator mode requires an external clock source to be con nected to the OSC1 p in. The fe edback device between O S C1 a nd OSC2 is turned off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or after a recovery from SLEEP mode.

In the EC oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r logic. Figure 2-3 shows the pin connections for the EC oscillator mode.

FIGURE 2-3: EXTERNAL CLOCK INPUT

OPERATION (EC OSC CONFIGURATION)

Clock from ext. system

OSC/4

FIGURE 2-4: PLL BLOCK DIAGRAM

OSC1

PIC18C601/801

OSC2

2.5 HS4 (PLL)

A Phase Lock Loop (PLL) circuit is provided as a software programmable optio n for us ers tha t want to m ultiply the frequency of the incoming crystal oscillator signal by 4. For an input clock frequency of 6 MHz, th e internal clock frequency will be multiplied to 24 MHz. This is use ful for custom ers who are conc erned with EMI due to high frequency crystals.

The PLL is enabled by configuring HS oscillator mode and setting the PLLEN bit in the OSCON register. If HS oscillator mode is not selected, or PLLEN bit in OSCCON register is clear, the PLL is not enabled and the system clock will come directly from OSC1. HS oscillator mode i s the d efa ult fo r PIC 1 8C60 1/80 1. In all other modes, the PLLEN bit and the SCS1 bit are forced to ‘0’.

A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out, referred to as T

PLL.

OSCOUT

OSCIN

PLL Enable

Crystal

Osc

HS Osc

Phase

Comparator

FOUT

CVCO

Loop Filter

Feedback Divider

3210

VCO

SYSCLK

MUX

 2001 Microchip Technology Inc. Advance Information DS39541A-page 23

PIC18C601/801

2.6 Oscillator Switching Feature

PIC18C601/801 devices include a feature that allows the system clock source to be switched from the main oscillator t o an alternate lo w frequency clock s ource. For PIC18C601/801 devices, this alternate clock source is the Timer1 oscillator. If a low frequency crystal (32 kHz, for example) has been attached to the Timer1 oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a low power execution mode. Figure 2-5 shows a block diagram of the system clock sources.

FIGURE 2-5: DEVICE CLOCK SOURCES

PIC18C601/801

OSC2

OSC1

T1OSO

T1OSI

Main Oscillator

SLEEP

Timer 1 Oscillator

T1OSCEN Enable Oscillator

2.6.1 SYSTEM CLOCK SWITCH BIT

The system clock source switching is performed under software control. The system clock switch bit, SCS0 (OSCCON register), controls the clock switching. When the SCS0 bit is ’0’, the system clock source comes from the main oscillator, selected by the FOSC2:FOSC0 co nfiguration bits in C ONFIG1H registe r . When the SCS0 b it is set, the system clock source will come from the Timer1 oscillator . The SCS0 bit is cle ared on all forms of RESET.

Note: The Timer1 oscillator must be enabled to

switch the system clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the T imer1 c ontrol register (T1CON). If the Timer1 oscillator is not enabled, an y write to the SCS0 bi t will be ignored (SCS0 bit forced cleared) and the main oscillator will continue to be the system clock source.

OSC/4

4 x PLL

TOSC

TT1P

MUX

Clock

Source

TSCLK

Clock Source option for other modules

Note: I/O pins have diode protection to VDD and VSS.

DS39541A-page 24 Advance Information  2001 Microchip Technology Inc.

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — LOCK PLLEN SCS1 SCS0

bit 7 bit 0

bit 7-4 Unimplemented: Read as '0' bit 3 LOCK: Phase Lock Loop Lock Status bit

1 = Phase Lock Loop output is stable as system clock 0 = Phase Lock Loop output is not stable and cannot be used as system clock

bit 2 PLLEN: Phase Lock Loop Enable bit

1 = Enable Phase Lock Loop output as system clock 0 = Disable Phase Lock Loop

bit 1 SCS1: System Clock Switch bit 1

When PLLEN and LOCK bit are set:

1 = Use PLL output 0 = Use primary oscillator/clock input pin

When PLLEN bit or LOCK bit is cleared: Bit is forced clear

bit 0 SCS0: System Clock Switch bit 0

When T1OSCEN bit is set:

1 = Switch to Timer1 oscillator/clock pin 0 = Use primary oscillator/clock input pin

When T1OSCEN is cleared: Bit is forced clear

PIC18C601/801

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

2.6.2 OSCIL LA T OR TRANSITIONS

PIC18C601/801 devices contain circuitry to prevent "glitches" when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources.

A timing diagram indicati ng the transition from the main oscillator to the Timer1 oscillator is shown in Figure 2-6. The Timer1 oscillator is assumed to be running all the time. After the SCS0 bit is set, the processor is frozen at the next occurri ng Q1 c ycle . Af ter eig ht sy nchroniz ation cycles are counted from the T imer1 oscilla tor, operation resumes. No additional delays are required after the synchronization cycles.

The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. In addition to eight clock cycles of the main oscillator, additional delays may take place.

If the main oscillator is configured for an external crystal (HS, LP), the transition will ta ke pl ac e a f ter an oscillator start-up time (T diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS and LP modes is shown in Figure 2-7.

OST) has occurred. A timing

 2001 Microchip Technology Inc. Advance Information DS39541A-page 25

PIC18C601/801

FIGURE 2-6: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

T1OSI

OSC1

Internal System Clock

SCS0 (OSCCON<0>)

Program Counter

Note: Delay on internal system clock is eight oscillator cycles for synchronization.

TOSC

TDLY

TT1P

21 34 5678

TSCS

PC + 2PC

Q3Q2Q1Q4Q3Q2

Q4 Q1

Q2 Q3 Q4 Q1

PC + 4

FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, LP)

T1OSI

OSC1

OSC2

Internal System

Clock

SCS0

(OSCCON<0>)

Q3 Q4

12345678

TOST

TOSC

TT1P

TSCS

Q1 Q2 Q3 Q4 Q1 Q2

Program Counter

Note: TOST = 1024TOSC (drawing not to scale).

PC + 2

PC + 4

DS39541A-page 26 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

If the main oscillator is configured for HS4 (PLL) mode with SCS1 bit set to ‘1’, an oscillator start-up time (T

OST), plus an additional PLL time-out (TPLL) will

occur . The PLL tim e-out is typica lly 2 ms an d allows the PLL to lock to the main oscillator frequency. A timing diagram indicating the transition from the Timer1 oscillator to t he main oscill ator for HS4 m ode is shown in Figure 2-8.

If the main oscill ator is confi gured for HS4 (PLL) m ode, with SCS1 bit set to ‘0’, only oscillator start-up time

OST) will occur. Since SCS 1 bi t is se t to ‘0’, PLL out-

put is not used, so the sys te m os ci ll ator w i ll c ome from OSC1 directly and additional delay of TPLL is not required. A timing diagram indica ting the transit ion from the Timer1 oscillator to the main oscillator for HS4 mode is shown in Figure 2-9.

If the main oscillator is configured in the RC or EC modes, there is no osci llator sta rt-up t ime-out. Operation will resume af ter ei ght cycle s of the m ain osc il lator have been counted. A timing diagram indicating the transition from the T ime r1 osci llator to the main os cill ator for RC and EC modes is shown in Figure2-10.

FIGURE 2-8: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS1 = 1)

PC + 4

T1OSI

OSC1

OSC2

PLL Clock

Input

Internal System

Program Counter

Clock SCS0

(OSCCON<0>)

Q4 Q1

TOST

PC PC + 2

TPLL

TOSC

TT1P

TSCS

12345678

Q1 Q2 Q3 Q4 Q1 Q2

OST = 1024TOSC (drawing not to scale).

Note: T

FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS = 0)

T1OSI

OSC1

OSC2

PLL

Clock

Output

Internal System

Clock

SCS0

(OSCCON<0>)

Program

Counter

Note: TOST = 1024TOSC (drawing not to scale).

PC PC + 2

TOST

DLY

TT1P

TOSC

TSCS

TPLL

Q1 Q2 Q3 Q4 Q1 Q2

PC + 4

 2001 Microchip Technology Inc. Advance Information DS39541A-page 27

PIC18C601/801

FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)

Q3 Q4

TT1P

Q1 Q2 Q3 Q4 Q1 Q2 Q3

T1OSI

OSC1

OSC2

Internal System

Clock SCS0

(OSCCON<0>)

Program Counter

Note: RC oscillator mode assumed.

PC PC + 2

2.6.3 SCS0, SCS 1 PRIORITY

If both SCS0 and SCS1 are set to ‘1’ simultaneously, the SCS0 bit has priority over the SCS1 bit. This means that the low power option will t ake prece dence over the PLL option. If both bit s are cle ared si mult a neous ly, the system clock will come from OS C1, after a TOST timeout. If only the SCS0 bit is c leared, the system c lock will

OST

come from the PLL output, following T

and TPLL

time.

TABLE 2-3: SCS0, SCS1 PRIORITY

SCS1 SCS0 Clock Source

0 0 Ext Oscillator OSC1 0 1 Timer1 Oscillator 10HS + PLL 1 1 Timer1 Oscillator

2.7 Effects of SLEEP Mode on the On-Chip Oscillator

When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the os ci lla tor o f f, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor switching currents have been removed, SLEEP mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during SLEEP, will increase the cur-

TOSC

45678

TSCS

PC + 4

rent consumed during SLEEP. The user can wake from SLEEP through external RESET, Watchdog Timer Reset, or through an interrupt.

2.8 Power-up Delays

Power-up delays are controlled by two timers, so that no external RESET circuitry is required for most applications. The delays ensure that the device is kept in RESET until the device power sup ply and clock are st able. For additional information on RESET operation, see Section 3.0 RESET .

The first timer is the Power-up Ti mer (PWRT), which optionally provides a fixed delay of T #33) on power-up only. The second timer is the Oscillator St art-u p T i mer (O ST), in tended to keep the c hip in RESET until the crystal oscillator is stable.

PIC18C601/801 devices provide a configuration bit, PWRTEN

in CONFIG2L register, to enable or disable the Power-up Timer. By default, the Power-up Timer is enabled.

With the PLL enabled (HS4 osc illator mode), the time-ou t sequence fol lowing a Power-o n Reset is different fr om other oscillator modes. The time-out sequence is as follows: the PWRT time-out is invoked after a POR time delay has expired, then, the Oscillator Start-up Timer (OST) is i nvoked. However, this is still not a sufficie nt amount of time to allow the PLL to lock at high frequencies. The PWRT ti mer is used to prov ide an addition al time-out, called T

PLL (parameter #7), to allow the PLL

ample time to l oc k to the incoming cl oc k frequency.

PWRT (parameter

TABLE 2-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC Mode OSC1 Pin OSC2 Pin

RC Floating, external resistor should pull high At logic low EC Floating At logic low LP and HS Feedback inverter disabled, at quiescent voltage level Feedback inverter disabled, at quiescent voltage level

Note: See Table 3-1 in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.

DS39541A-page 28 Advance Information  2001 Microchip Technology Inc.

PIC18C601/801

3.0 RESET

Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper-

PIC18C601/801 devices differentiate between various kinds of RESET:

a) Power-on Reset (POR) b) MCLR

Reset during normal operation c) MCLR Reset during SLEEP d) Watchdog Timer (WDT) Reset during normal

operation e) RESET Instruction f) Stack Full Reset g) Stack Underflow Reset

Most registers are una ffected b y a RESET. Their status is unknown on POR and unchanged by all other

ation. Status bits from the RCON regi ster, RI and POR, are set or cleared differently in different RESET situations, as i ndicated in Table 3-2. These bits are used in software to determine the nature of the RESET. See Table 3-3 for a full description of the RESET states of all registers.

A simplified block diagram of the on-chip RESET circuit is shown in Figure 3-1.

PIC18C601/801 has a MCLR

noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.

A WDT Reset does not drive MCLR

pin low.

RESETS. The other registers are forced to a “RESET” state on Power-on Reset, MCLR

, WDT Reset, MCLR

Reset during SLEEP, and by the RESET instruction.

FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF THE ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

External Reset

, TO, PD

MCLR

WDT

Module

VDD Rise

VDD

OSC1

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

2: See Table 3-1 for time-out situations.

Detect

OST/PWRT

On-chip

RC OSC

(1)

SLEEP

WDT

Time-out Reset

Power-on Reset

OST

10-bit Ripple Counter

PWRT

10-bit Ripple Counter

Enable PWRT

Enable OST

(2)

Chip_Reset

 2001 Microchip Technology Inc. Advance Information DS39541A-page 29

PIC18C601/801

3.1 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when a

DD rise is detected. To take advantage of the POR cir-

V cuitry, connect the MCLR resistor) to V

DD. This will eliminate ext ernal RC compo-

nents usually needed to create a Power-on Reset delay . A minimum rise rat e for V eter D004). For a slow rise time, see Figure 3-2.

When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are m et . Po wer - on R e s et ma y b e us ed t o m ee t the voltage start-up condition.

FIGURE 3-2: EXTERNAL POWER-ON

Note 1: External Power-on Reset circuit is required only

2: R < 40 kΩ is recommended to make sure that

3: R1 = 100Ω to 1 kΩ will limit any current flowing

DD power-up slope is too slow. The diode

if the V D helps discharge the capacitor quickly when V

DD powers down.

the voltage drop across R does not violate the device’s electrical specification.

into MCLR event of MCLR/ Electrostatic Discharge (ESD), or Electrical Overstress (EOS).

pin directly (or through a

DD is specified (p aram-

RESET CIRCUIT (FOR SLOW V

from external capacitor C, in the

VPP pin breakdown due to

DD POWER-UP)

MCLR

PIC18C601/801

3.3 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (para meter #32). Th is ensures th at the crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for LP, HS and HS4 modes and only on Power-on Reset or wake-up from SLEEP.

3.4 PLL Lock Time-out

With the PLL enabled, the time-ou t sequen ce foll owin g a Power-on Reset is different from other oscillator modes. A portion of the Pow er-up T imer is used to provide a fixed time-out th at is suff icient for the PLL to lock to the main oscillato r frequency. This PLL lock time-out

PLL) is typically 1 ms and follows the oscillator start-

(T up time-out (OST).

3.5 Time-out Sequence

On power-up, the time-out sequence is as follows: First, PWRT time-out is invoked after the POR time delay has expired; then, OST is activated. The total time-out will vary based on oscillator configuration and the status of th e PWRT. For example, in RC mode wi th the PWRT disabled, there will be no time-out at all. Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, if MC LR is kept low long enough, the time-outs will expire. Bringing MCLR (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18C601/801 device operating in parallel.

Table 3-2 shows the RESET conditions for some Special Function Registers, while Table 3-3 shows the RESET conditions for all registers.

high will begin execution immediately

3.2 Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out (parameter #33), only on power-up from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. Th e PWRT t ime de lay al lows V acceptable level. PIC18C601/801 devices are available with PWRT enabled or disabled.

The power-up time delay wi ll vary from chip to chi p, due

DD, temperature and process variation. See DC

to V parameter #33 for details.

DS39541A-page 30 Advance Information  2001 Microchip Technology Inc.

DD to rise to an

+ 290 hidden pages

MICROCHIP PIC18C601, PIC18C801 Technical data

Pin Diagrams

Table of Contents

1.0 DEVICE OVERVIEW

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

2.2 Crystal Oscillator/Ceramic Resonators

2.3 RC Oscillator

2.4 External Clock Input

2.5 HS4 (PLL)

2.6 Oscillator Switching Feature

2.6.1 SYSTEM CLOCK SWITCH BIT

2.6.2 OSCIL LA T OR TRANSITIONS

2.6.3 SCS0, SCS 1 PRIORITY

2.8 Power-up Delays

3.0 RESET

3.1 Power-on Reset (POR)

3.3 Oscillator Start-up Timer (OST)

3.4 PLL Lock Time-out

3.5 Time-out Sequence

3.2 Power-up Timer (PWRT)