MICROCHIP PIC16F913, PIC16F914, PIC16F916, PIC16F917, PIC16F946 DATA SHEET

PIC16F913/914/916/917/946

Data Sheet

28/40/44/64-Pin Flash-Based,

8-Bit CMOS Microcontrollers with

LCD Driver and nanoWatt Technology

© 2007 Microchip Technology Inc. DS41250F

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

DS41250F-page ii © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

LCD Driver and nanoWatt Technology

High-Performance RISC CPU:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Program Memory Read (PMR) capability

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency range of
8 MHz to 125 kHz

- Software tunable

- Two-Speed Start-up mode

- External Oscillator fail detect for critical
applications

- Clock mode switching during operation for
power savings

• Software selectable 31 kHz internal oscillator

• Power-Saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended temperature range

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)

• Brown-out Reset (BOR) with software control
option

• Enhanced Low-Current Watchdog Timer (WDT)
with on-chip oscillator (software selectable
nominal 268 seconds with full prescaler) with
software enable

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

Low-Power Features:

• Standby Current:

- <100 nA @ 2.0V, typical

• Operating Current:

-11μA @ 32 kHz, 2.0V, typical

-220μA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

Peripheral Features:

• Liquid Crystal Display module:

- Up to 60/96/168 pixel drive capability on
28/40/64-pin devices, respectively

- Four commons

• Up to 24/35/53 I/O pins and 1 input-only pin:

- High-current source/sink for direct LED drive

- Interrupt-on-change pin

- Individually programmable weak pull-ups

• In-Circuit Serial Programming™ (ICSP™) via two
pins

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference

(CVREF) module (% of VDD)

- Comparator inputs and outputs externally

accessible

• A/D Converter:

- 10-bit resolution and up to 8 channels

• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Timer1 Gate (count enable)

- Option to use OSC1 and OSC2 as Timer1

oscillator if INTOSCIO or LP mode is
selected

• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler

• Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)

• Up to 2 Capture, Compare, PWM modules:

- 16-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM, max. frequency 20 kHz

• Synchronous Serial Port (SSP) with I

2

C™

© 2007 Microchip Technology Inc. DS41250F-page 1

PIC16F913/914/916/917/946

Program

Memory

Device

Flash

(words/bytes)

PIC16F913 4K/7K 256 256 24 5 16

Data Memory

SRAM
(bytes)

EEPROM

(bytes)

I/O

10-bit A/D

(ch)

LCD

(segment

drivers)

(1)

CCP

Timers

8/16-bit

12/1

PIC16F914 4K/7K 256 256 35 8 24 2 2/1

PIC16F916 8K/14K 352 256 24 5 16

(1)

12/1

PIC16F917 8K/14K 352 256 35 8 24 2 2/1

PIC16F946 8K/14K 336 256 53 8 42 2 2/1

Note 1: COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG15 is not available

when using 1/4 multiplex displays.

Pin Diagrams – PIC16F914/917, 40-Pin

40-pin PDIP

RE3/MCLR/VPP

RA0/AN0/C1-/SEG12

RA1/AN1/C2-/SEG7

RA2/AN2/C2+/V

RA3/AN3/C1+/V

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS

RA7/OSC1/CLKIN/T1OSI

RA6/OSC2/CLKOUT/T1OSO

REF-/COM2

REF+/SEG15

/SEG5
RE0/AN5/SEG21
RE1/AN6/SEG22
RE2/AN7/SEG23

V

DD

VSS

RC0/VLCD1
RC1/VLCD2
RC2/VLCD3

RC3/SEG6

RD0/COM3

RD1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PIC16F914/917

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
RB5/COM1
RB4/COM0
RB3/SEG3
RB2/SEG2
RB1/SEG1
RB0/INT/SEG0
V

DD

VSS
RD7/SEG20
RD6/SEG19
RD5/SEG18
RD4/SEG17
RC7/RX/DT/SDI/SDA/SEG8
RC6/TX/CK/SCK/SCL/SEG9
RC5/T1CKI/CCP1/SEG10
RC4/T1G
RD3/SEG16
RD2/CCP2

/SDO/SEG11

DS41250F-page 2 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

TABLE 1: PIC16F914/917 40-PIN SUMMARY

I/O Pin A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic

RA0 2 AN0 SEG12 C1- — — — — — — —

RA1 3 AN1 SEG7 C2- — — — — — — —

RA2 4 AN2/VREF- COM2 C2+ — — — — — — —

RA3 5

RA4 6 SEG4 C1OUT T0CKI — — — — — —

RA5 7 AN4 SEG5 C2OUT — — — SS

RA6 14 — — — T1OSO — — — — — OSC2/CLKOUT

RA7 13 — — — T1OSI — — — — — OSC1/CLKIN

RB0 33 — SEG0 — — — — — INT Y —

RB1 34 — SEG1 — — — — — — Y —

RB2 35 — SEG2 — — — — — — Y —

RB3 36 — SEG3 — — — — — — Y —

RB4 37 — COM0 — — — — — IOC Y —

RB5 38 — COM1 — — — — — IOC Y —

RB6 39 — SEG14 — — — — — IOC Y ICSPCLK/ICDCK

RB7 40 — SEG13 — — — — — IOC Y ICSPDAT/ICDDAT

RC0 15 — VLCD1 — — — — — — — —

RC1 16 — VLCD2 — — — — — — — —

RC2 17 — VLCD3 — — — — — — — —

RC3 18 — SEG6 — — — — — — — —

RC4 23 — SEG11 — T1G — — SDO — — —

RC5 24 — SEG10 — T1CKI CCP1 — — — — —

RC6 25 — SEG9 — — — TX/CK SCK/SCL — — —

RC7 26 — SEG8 — — — RX/DT SDI/SDA — — —

RD0 19 — COM3 — — — — — — — —

RD1 20 — — — — — — — — — —

RD2 21 — — — — CCP2 — — — — —

RD3 22 — SEG16 — — — — — — — —

RD4 27 — SEG17 — — — — — — — —

RD5 28 — SEG18 — — — — — — — —

RD6 29 — SEG19 — — — — — — — —

RD7 30 — SEG20 — — — — — — — —

RE0 8 AN5 SEG21 — — — — — — — —

RE1 9 AN6 SEG22 — — — — — — — —

RE2 10 AN7 SEG23 — — — — — — — —

RE3 1 — — — — — — — — Y

— 11 — — — — — — — — — VDD

—32 — — — — — — — — — VDD

— 12 — — — — — — — — — VSS

—31 — — — — — — — — — VSS

Note 1: Pull-up enabled only with external MCLR configuration.

AN3/V

SEG15 C1+ — — — — — —

REF+

—

—— —

(1)

MCLR/VPP

© 2007 Microchip Technology Inc. DS41250F-page 3

PIC16F913/914/916/917/946

Pin Diagrams – PIC16F913/916, 28-Pin

28-pin PDIP, SOIC, SSOP

RA3/AN3/C1+/V

RA6/OSC2/CLKOUT/T1OSO

28-pin QFN

RE3/MCLR/VPP

RA0/AN0/C1-/SEG12

RA1/AN1/C2-/SEG7

RA2/AN2/C2+/V

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS

RA7/OSC1/CLKIN/T1OSI

REF-/COM2

REF+/COM3/SEG15

/SEG5

RC0/VLCD1
RC1/VLCD2
RC2/VLCD3

RC3/SEG6

PIC16F913/916

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
RB5/COM1
RB4/COM0
RB3/SEG3
RB2/SEG2
RB1/SEG1
RB0/INT/SEG0
V

DD

VSS
RC7/RX/DT/SDI/SDA/SEG8
RC6/TX/CK/SCK/SCL/SEG9
RC5/T1CKI/CCP1/SEG10
RC4/T1G

/SDO/SEG11

1
2
3
4
5
6
7

V

SS

8
9

10
11

12
13
14

/VPP

RA2/AN2/C2+/VREF-/COM2

RA3/AN3/C1+/V

RA6/OSC2/CLKOUT/T1OSO

REF+/COM3/SEG15

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS

RA7/OSC1/CLKIN/T1OSI

/SEG5

SS

V

RA1/AN1/C2-/SEG7

282627

1

2

3

PIC16F913/916

4

5

6

7

8109

RC0/VLCD1

RA0/AN0/C1-/SEG12

RC1/VLCD2

RE3/MCLR

RB7/ICSPDAT/ICDDAT/SEG13

25

11

RC3/SEG6

RC2/VLCD3

12

RB6/ICSPCLK/ICDCK/SEG14

24

/SDO/SEG11

RC4/T1G

RB5/COM1

23

13

RC5/T1CKI/CCP1/SEG10

RB4/COM0

22

14

RC6/TX/CK/SCK/SCL/SEG9

21

20

19

18

17

16

15

RB3/SEG3

RB2/SEG2

RB1/SEG1

RB0/INT/SEG0

V

DD

VSS

RC7/RX/DT/SDI/SDA/SEG8

DS41250F-page 4 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

TABLE 2: PIC16F913/916 28-PIN (PDIP, SOIC, SSOP) SUMMARY

I/O Pin A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic

RA0 2 AN0 SEG12 C1- — — — — — — —

RA1 3 AN1 SEG7 C2- — — — — — — —

RA2 4 AN2/VREF- COM2 C2+ — — — — — — —

RA3 5

RA4 6 — SEG4 C1OUT T0CKI — — — — — —

RA5 7 — SEG5 C2OUT — — — SS

RA6 10 — — — T1OSO — — — — — OSC2/CLKOUT

RA7 9 — — — T1OSI — — — — — OSC1/CLKIN

RB0 21 — SEG0 — — — — — INT Y —

RB1 22 — SEG1 — — — — — — Y —

RB2 23 — SEG2 — — — — — — Y —

RB3 24 — SEG3 — — — — — — Y —

RB4 25 — COM0 — — — — — IOC Y —

RB5 26 — COM1 — — — — — IOC Y —

RB6 27 — SEG14 — — — — — IOC Y ICSPCLK/ICDCK

RB7 28 — SEG13 — — — — — IOC Y ICSPDAT/ICDDAT

RC0 11 — VLCD1 — — — — — — — —

RC1 12 — VLCD2 — — — — — — — —

RC2 13 — VLCD3 — — — — — — — —

RC3 14 — SEG6 — — — — — — — —

RC4 15 — SEG11 — T1G — — SDO — — —

RC5 16 — SEG10 — T1CKI CCP1 — — — — —

RC6 17 — SEG9 — — — TX/CK SCK/SCL — — —

RC7 18 — SEG8 — — — RX/DT SDI/SDA — — —

RE3 1 — — — — — — — — Y

—20————————— VDD

— 8 — — — — — — — — — VSS

—19————————— VSS

Note 1: Pull-up enabled only with external MCLR configuration.

AN3/V

REF+

SEG15/

COM3

C1+ — — — — — —

—— —

—

(1)

MCLR/VPP

© 2007 Microchip Technology Inc. DS41250F-page 5

PIC16F913/914/916/917/946

TABLE 3: PIC16F913/916 28-PIN (QFN) SUMMARY

I/O Pin A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic

RA0 27 AN0 SEG12 C1- — — — — — — —

RA1 28 AN1 SEG7 C2- — — — — — — —

RA2 1 AN2/VREF- COM2 C2+ — — — — — — —

RA3 2 AN3/V

RA4 3 — SEG4 C1OUT T0CKI — — — — — —

RA5 4 AN4 SEG5 C2OUT — — — SS

RA6 7 — — — T1OSO — — — — — OSC2/CLKOUT

RA7 6 — — — T1OSI — — — — — OSC1/CLKIN

RB0 18 — SEG0 — — — — — INT Y —

RB1 19 — SEG1 — — — — — — Y —

RB2 20 — SEG2 — — — — — — Y —

RB3 21 — SEG3 — — — — — — Y —

RB4 22 — COM0 — — — — — IOC Y —

RB5 23 — COM1 — — — — — IOC Y —

RB6 24 — SEG14 — — — — — IOC Y ICSPCLK/ICDCK

RB7 25 — SEG13 — — — — — IOC Y ICSPDAT/ICDDAT

RC0 8 — VLCD1 — — — — — — — —

RC1 9 — VLCD2 — — — — — — — —

RC2 10 — VLCD3 — — — — — — — —

RC3 11 — SEG6 — — — — — — — —

RC4 12 — SEG11 — T1G — — SDO — — —

RC5 13 — SEG10 — T1CKI CCP1 — — — — —

RC6 14 — SEG9 — — — TX/CK SCK/SCL — — —

RC7 15 — SEG8 — — — RX/DT SDI/SDA — — —

RE3 26 — — — — — — — — Y

—17—————————VDD

— 5 — — — — — — — — — VSS

—16————————— VSS

Note 1: Pull-up enabled only with external MCLR configuration.

REF+ SEG15/

COM3

C1+ — — — — — —

—— —

—

(1)

MCLR/VPP

DS41250F-page 6 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

Pin Diagrams – PIC16F914/917, 44-Pin

44-pin TQFP

/SDO/SEG11

RC6/TX/CK/SCK/SCL/SEG9

RC5/T1CKI/CCP1/SEG10

RC4/T1G

RD3/SEG16

RD2/CCP2

RD1

RD0/COM3

RC3/SEG6

RC2/VLCD3

RC1/VLCD2

NC

RC7/RX/DT/SDI/SDA/SEG8

RD4/SEG17
RD5/SEG18
RD6/SEG19
RD7/SEG20

V

RB0/SEG0/INT

VDD

RB1/SEG1
RB2/SEG2
RB3/SEG3

44-pin QFN

4443424140

1
2
3
4

SS

5
6
7
8
9
10
11

121314

NC

RC7/RX/DT/SDI/SDA/SEG8

39

PIC16F914/917

16

17

15

NC

RB4/COM0

RB5/COM1

RB6/ICSPCLK/ICDCK/SEG14

RB7/ICSPDAT/ICDDAT/SEG13

RD4/SEG17
RD5/SEG18
RD6/SEG19
RD7/SEG20

RB0/INT/SEG0

RB1/SEG1
RB2/SEG2

363435

37

38

1819202122

/VPP

REF-/COM2

RE3/MCLR

REF+/C1+/SEG15

RA1/C2-/AN1/SEG7

RA0/C1-/AN0/SEG12

RA2/AN2/C2+/V

RA3/AN3/V

SS

V
VDD
VDD

33
32
31
30
29
28
27
26
25
24

23

NC
RC0/VLCD1
RA6/OSC2/CLKOUT/T1OSO
RA7/OSC1/CLKIN/T1OSI

SS

V
VDD
RE2/AN7/SEG23
RE1/AN6/SEG22
RE0/AN5/SEG21
RA5/AN4/C2OUT/SS
RA4/C1OUT/T0CKI/SEG4

/SDO/SEG11

RC6/TX/CK/SCK/SCL/SEG9

RC5/T1CKI/CCP1/SEG10

RC4/T1G

RD3/SEG16

RD2/CCP2

RD1

RD0/COM3

RC3/SEG6

4443424140

1
2
3
4
5
6
7
8
9
10
11

121314

39

37

38

PIC16F914/917

16

17

1819202122

15

RC2/VLCD3

363435

/SEG5

RC1/VLCD2

RC0/VLDC1

33
32
31
30
29
28
27
26
25
24

23

RA6/OSC2/CLKOUT/T1OSO
RA7/OSC1/CLKIN/T1OSI

SS

V
VSS
NC
V

DD

RE2/AN7/SEG23
RE1/AN6/SEG22
RE0/AN5/SEG21
RA5/AN4/C2OUT/SS
RA4/C1OUT/T0CKI/SEG4

/SEG5

NC

RB3/SEG3

RB4/COM0

RB5/COM1

RB6/ICSPCLK/ICDCK/SEG14

RB7/ICSPDAT/ICDDAT/SEG13

REF-/COM2

RE3/MCLR/VPP

REF+/SEG15

RA1/AN1/C2-/SEG7

RA0/AN0/C1-/SEG12

RA2/AN2/C2+/V

RA3/AN3/C1+/V

© 2007 Microchip Technology Inc. DS41250F-page 7

PIC16F913/914/916/917/946

TABLE 4: PIC16F914/917 44-PIN (TQFP) SUMMARY

I/O Pin A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic

RA0 19 AN0 SEG12 C1- — — — — — — —

RA1 20 AN1 SEG7 C2- — — — — — — —

RA2 21 AN2/VREF- COM2 C2+ — — — — — — —

RA3 22 AN3/V

RA4 23 — SEG4 C1OUT T0CKI — — — — — —

RA5 24 AN4 SEG5 C2OUT — — — SS

RA6 31 — — — T1OSO — — — — — OSC2/CLKOUT

RA7 30 — — — T1OSI — — — — — OSC1/CLKIN

RB0 8 — SEG0 — — — — — INT Y —

RB1 9 — SEG1 — — — — — — Y —

RB2 10 — SEG2 — — — — — — Y —

RB3 11 — SEG3 — — — — — — Y —

RB4 14 — COM0 — — — — — IOC Y —

RB5 15 — COM1 — — — — — IOC Y —

RB6 16 — SEG14 — — — — — IOC Y ICSPCLK/ICDCK

RB7 17 — SEG13 — — — — — IOC Y ICSPDAT/ICDDAT

RC0 32 — VLCD1 — — — — — — — —

RC1 35 — VLCD2 — — — — — — — —

RC2 36 — VLCD3 — — — — — — — —

RC3 37 — SEG6 — — — — — — — —

RC4 42 — SEG11 — T1G — — SDO — — —

RC5 43 — SEG10 — T1CKI CCP1 — — — — —

RC6 44 — SEG9 — — — TX/CK SCK/SCL — — —

RC7 1 — SEG8 — — — RX/DT SDI/SDA — — —

RD0 38 — COM3 — — — — — — — —

RD1 39 — — — — — — — — — —

RD2 40 — — — — CCP2 — — — — —

RD3 41 — SEG16 — — — — — — — —

RD4 2 — SEG17 — — — — — — — —

RD5 3 — SEG18 — — — — — — — —

RD6 4 — SEG19 — — — — — — — —

RD7 5 — SEG20 — — — — — — — —

RE0 25 AN5 SEG21 — — — — — — — —

RE1 26 AN6 SEG22 — — — — — — — —

RE2 27 AN7 SEG23 — — — — — — — —

RE318————————Y

— 7 — — — — — — — — — VDD

—28—————————VDD

— 6 — — — — — — — — — VSS

—29————————— VSS

— 12 — — — — — — — — — NC

—13————————— NC

— 33 — — — — — — — — — NC

—34————————— NC

Note 1: Pull-up enabled only with external MCLR

REF+ SEG15 C1+ — — — — — —

—— —

configuration.

—

(1)

MCLR/VPP

DS41250F-page 8 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

TABLE 5: PIC16F914/917 44-PIN (QFN) SUMMARY

I/O Pin A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic

RA0 19 AN0 SEG12 C1- — — — — — — —

RA1 20 AN1 SEG7 C2- — — — — — — —

RA2 21 AN2/VREF- COM2 C2+ — — — — — — —

RA3 22 AN3/V

RA4 23 — SEG4 C1OUT T0CKI — — — — — —

RA5 24 AN4 SEG5 C2OUT — — — SS

RA6 33 — — — T1OSO — — — — — OSC2/CLKOUT

RA7 32 — — — T1OSI — — — — — OSC1/CLKIN

RB0 9 — SEG0 — — — — — INT Y —

RB1 10 — SEG1 — — — — — — Y —

RB2 11 — SEG2 — — — — — — Y —

RB3 12 — SEG3 — — — — — — Y —

RB4 14 — COM0 — — — — — IOC Y —

RB5 15 — COM1 — — — — — IOC Y —

RB6 16 — SEG14 — — — — — IOC Y ICSPCLK/ICDCK

RB7 17 — SEG13 — — — — — IOC Y ICSPDAT/ICDDAT

RC0 34 — VLCD1 — — — — — — — —

RC1 35 — VLCD2 — — — — — — — —

RC2 36 — VLCD3 — — — — — — — —

RC3 37 — SEG6 — — — — — — — —

RC4 42 — SEG11 — T1G — — SDO — — —

RC5 43 — SEG10 — T1CKI CCP1 — — — — —

RC6 44 — SEG9 — — — TX/CK SCK/SCL — — —

RC7 1 — SEG8 — — — RX/DT SDI/SDA — — —

RD0 38 — COM3 — — — — — — — —

RD1 39 — — — — — — — — — —

RD2 40 — — — — CCP2 — — — — —

RD3 41 — SEG16 — — — — — — — —

RD4 2 — SEG17 — — — — — — — —

RD5 3 — SEG18 — — — — — — — —

RD6 4 — SEG19 — — — — — — — —

RD7 5 — SEG20 — — — — — — — —

RE0 25 AN5 SEG21 — — — — — — — —

RE1 26 AN6 SEG22 — — — — — — — —

RE2 27 AN7 SEG23 — — — — — — — —

RE318————————Y

— 7 — — — — — — — — — VDD

—8————————— VDD

— 28 — — — — — — — — — VDD

—6————————— VSS

— 30 — — — — — — — — — VSS

—13————————— NC

— 29 — — — — — — — — — NC

Note 1: Pull-up enabled only with external MCLR

REF+ SEG15 C1+ — — — — — —

—— —

configuration.

—

(1)

MCLR/VPP

© 2007 Microchip Technology Inc. DS41250F-page 9

PIC16F913/914/916/917/946

Pin Diagram – PIC16F946

64-pin TQFP

/SDO/SEG11

DD

RD5/SEG18

RD4/SEG17

RC7/RX/DT/SDI/SDA/SEG8

RC6/TX/CK/SCK/SCL/SEG9

RC5/T1CKI/CCP1/SEG10

V

RC4/T1G

VSS

RD3/SEG16

RD2/CCP2

RD1

RD0/COM3

RC3/SEG6

RC0/VLCD1

RC2/VLCD3

RC1/VLCD2

RD6/SEG19

RD7/SEG20

RG0/SEG36

RG1/SEG37

RG2/SEG38

RG3/SEG39

RG4/SEG40

RG5/SEG41

V

VDD

RF0/SEG32

RF1/SEG33

RF2/SEG34

RF3/SEG35

RB0/INT/SEG0

RB1/SEG1

54 53 52 5158 57 56 5560 5964 63 62 61

1

2

3

4

5

6

7

8

SS

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26

VDD

RB2/SEG2

RB3/SEG3

VSS

PIC16F946

RB4/COM0

RB5/COM1

27 28 29 30 32

DD

AVSS

AV

REF-/COM2

50 49

31

REF+/SEG15

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

/SEG5

RF7/SEG31

RF6/SEG30

RF5/SEG29

RF4/SEG28

RE7/SEG27

RE6/SEG26

RE5/SEG25

V

SS

RA6/OSC2/CLKOUT/T1OSO

RA7/OSC1/CLKIN/T1OSI

VDD

RE4/SEG24

RE3/MCLR/VPP

RE2/AN7/SEG23

RE1/AN6/SEG22

RE0/AN5/SEG21

RA1/AN1/C2-/SEG7

RA0/AN0/C1-/SEG12

RA4/C1OUT/T0CKI/SEG4

RA3/AN3/C1+/V

RA5/AN4/C2OUT/SS

RB6/ICSPCLK/ICDCK/SEG14

RB7/ICSPDAT/ICDDAT/SEG13

RA2/AN2/C2+/V

DS41250F-page 10 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

TABLE 6: PIC16F946 64-PIN (TQFP) SUMMARY

I/O Pin A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic

RA0 27 AN0 SEG12 C1- — — — — — — —

RA1 28 AN1 SEG7 C2- — — — — — — —

RA2 29 AN2/VREF- COM2 C2+ — — — — — — —

RA3 30 AN3/V

RA4 31 — SEG4 C1OUT T0CKI — — — — — —

RA5 32 AN4 — C2OUT — — — SS

RA6 40 SEG5 — — T1OSO — — — — — OSC2/CLKOUT

RA7 39 — — — T1OSI — — — — — OSC1/CLKIN

RB0 15 — SEG0 — — — — — INT Y —

RB1 16 — SEG1 — — — — — — Y —

RB2 17 — SEG2 — — — — — — Y —

RB3 18 — SEG3 — — — — — — Y —

RB4 21 — COM0 — — — — — IOC Y —

RB5 22 — COM1 — — — — — IOC Y —

RB6 23 — SEG14 — — — — — IOC Y ICSPCLK/ICDCK

RB7 24 — SEG13 — — — — — IOC Y ICSPDAT/ICDDAT

RC0 49 — VLCD1 — — — — — — — —

RC1 50 — VLCD2 — — — — — — — —

RC2 51 — VLCD3 — — — — — — — —

RC3 52 — SEG6 — — — — — — — —

RC4 59 — SEG11 — T1G — — SDO — — —

RC5 60 — SEG10 — T1CKI CCP1 — — — — —

RC6 61 — SEG9 — — — TX/CK SCK/SCL — — —

RC7 62 — SEG8 — — — RX/DT SDI/SDA — — —

RD0 53 — COM3 — — — — — — — —

RD1 54 — — — — — — — — — —

RD2 55 — — — — CCP2 — — — — —

RD3 58 — SEG16 — — — — — — — —

RD4 63 — SEG17 — — — — — — — —

RD5 64 — SEG18 — — — — — — — —

RD6 1 — SEG19 — — — — — — — —

RD7 2 — SEG20 — — — — — — — —

RE0 33 AN5 SEG21 — — — — — — — —

RE1 34 AN6 SEG22 — — — — — — — —

RE2 35 AN7 SEG23 — — — — — — — —

RE3 36 — — — — — — — — Y

RE4 37 — SEG24 — — — — — — — —

RE5 42 — SEG25 — — — — — — — —

RE6 43 — SEG26 — — — — — — — —

RE7 44 — SEG27 — — — — — — — —

RF0 11 — SEG32 — — — — — — — —

RF1 12 — SEG33 — — — — — — — —

RF2 13 — SEG34 — — — — — — — —

Note 1: Pull-up enabled only with external MCLR

REF+ SEG15 C1+ — — — — — —

—— —

configuration.

—

(1)

MCLR/VPP

© 2007 Microchip Technology Inc. DS41250F-page 11

PIC16F913/914/916/917/946

TABLE 6: PIC16F946 64-PIN (TQFP) SUMMARY (CONTINUED)

I/O Pin A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic

RF3 14 — SEG35 — — — — — — — —

RF4 45 — SEG28 — — — — — — — —

RF5 46 — SEG29 — — — — — — — —

RF6 47 — SEG30 — — — — — — — —

RF7 48 — SEG31 — — — — — — — —

RG0 3 — SEG36 — — — — — — — —

RG1 4 — SEG37 — — — — — — — —

RG2 5 — SEG38 — — — — — — — —

RG3 6 — SEG39 — — — — — — — —

RG4 7 — SEG40 — — — — — — — —

RG5 8 — SEG41 — — — — — — — —

— 26 — — — — — — — — — AVDD

—25 — — — — — — — — — AVSS

— 10 — — — — — — — — — VDD

—19 — — — — — — — — — VDD

— 38 — — — — — — — — — VDD

—57 — — — — — — — — — VDD

— 9 — — — — — — — — — VSS

—20 — — — — — — — — — VSS

— 41 — — — — — — — — — VSS

—56 — — — — — — — — — VSS

Note 1: Pull-up enabled only with external MCLR

configuration.

DS41250F-page 12 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 15

2.0 Memory Organization ................................................................................................................................................................. 23

3.0 I/O Ports ..................................................................................................................................................................................... 43

4.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 87

5.0 Timer0 Module ........................................................................................................................................................................... 99

6.0 Timer1 Module with Gate Control............................................................................................................................................. 102

7.0 Timer2 Module ......................................................................................................................................................................... 107

8.0 Comparator Module.................................................................................................................................................................. 109

9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) ........................................................... 121

10.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 143

11.0 Programmable Low-Voltage Detect (PLVD) Module................................................................................................................ 171

12.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 175

13.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 187

14.0 SSP Module Overview ............................................................................................................................................................. 193

15.0 Capture/Compare/PWM (CCP) Module ................................................................................................................................... 211

16.0 Special Features of the CPU.................................................................................................................................................... 219

17.0 Instruction Set Summary.......................................................................................................................................................... 241

18.0 Development Support............................................................................................................................................................... 251

19.0 Electrical Specifications............................................................................................................................................................ 255

20.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 283

21.0 Packaging Information.............................................................................................................................................................. 305

Appendix A: Data Sheet Revision History .......................................................................................................................................... 315

Appendix B: Migrating From Other PIC

Appendix C: Conversion Considerations ........................................................................................................................................... 316

Index .................................................................................................................................................................................................. 317

The Microchip Web Site..................................................................................................................................................................... 325

Customer Change Notification Service .............................................................................................................................................. 325

Customer Support .............................................................................................................................................................................. 325

Reader Response .............................................................................................................................................................................. 327

Product Identification System ............................................................................................................................................................ 328

®

Devices.............................................................................................................................. 315

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

© 2007 Microchip Technology Inc. DS41250F-page 13

PIC16F913/914/916/917/946

NOTES:

DS41250F-page 14 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

1.0 DEVICE OVERVIEW

The PIC16F91X/946 devices are covered by this data
sheet. They are available in 28/40/44/64-pin packages.
Figure 1-1 shows a block diagram of the PIC16F913/916
device, Figure 1-2 shows a block diagram of the
PIC16F914/917 device, and Figure 1-3 shows a block
diagram of the PIC16F946 device. Table 1-1 shows the
pinout descriptions.

FIGURE 1-1: PIC16F913/916 BLOCK DIAGRAM

INT

Program Counter

8-Level Stack (13-bit)

(PMR)

Direct Addr

Power-up

Timer

Oscillator

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VSS

256/352 bytes

7

3

ALU

8

W Reg

Program

Bus

OSC1/CLKIN

OSC2/CLKOUT

Internal

Oscillator

Block

Configuration

Flash

4K/8K x 14

Program

Memory

14

Instruction Reg

Instruction

Decode and

Control

Timing

Generation

13

Program Memory Read

8

Start-up Timer

VDD

Data Bus

RAM

File

Registers

Addr MUX

8

FSR Reg

STATUS Reg

MUX

RAM Addr

9

Indirect

Addr

8

PORTA

RA0
RA1
RA2
RA3
RA4
RA5
RA7

PORTB

RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7

PORTC

RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7

PORTE

RE3/MCLR

Data EEPROM

Timer0

Comparators

Timer1 Timer2 10-bit A/D

CCP1 SSP

Addressable

USART

256 bytes

PLVD LCD

© 2007 Microchip Technology Inc. DS41250F-page 15

PIC16F913/914/916/917/946

FIGURE 1-2: PIC16F914/917 BLOCK DIAGRAM

INT

Program Counter

8-Level Stack (13-bit)

(PMR)

Direct Addr

Power-up

Timer

Oscillator

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VSS

Data Bus

RAM

256/352 bytes

File

Registers

9

Addr MUX

7

3

8

8

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Program

Bus

OSC1/CLKIN

OSC2/CLKOUT

Internal

Oscillator

Block

Configuration

Flash

4K/8K x 14

Program

Memory

14

Instruction Reg

Instruction

Decode and

Control

Timing

Generation

13

Program Memory Read

8

Start-up Timer

VDD

8

RAM Addr

Indirect

Addr

PORTA

RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7

PORTB

RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7

PORTC

RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7

PORTD

RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7

Timer0

Comparators

Timer1 Timer2 10-bit A/D

CCP1

CCP2 SSP

Addressable

USART

PORTE

RE0
RE1
RE2
RE3/MCLR

Data EEPROM

256 bytes

PLVD LCD

DS41250F-page 16 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

FIGURE 1-3: PIC16F946 BLOCK DIAGRAM

INT

Program

Bus

OSC1/CLKIN

OSC2/CLKOUT

Internal

Oscillator

Block

Configuration

Flash

8K x 14

Program

Memory

14

Instruction Reg

Instruction

Decode and

Control

Timing

Generation

13

Program Counter

8-Level Stack (13-bit)

Program Memory Read

(PMR)

Direct Addr

8

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

V

VSS

DD

7

3

8

Data Bus

RAM

336 x 8 bytes

File

Registers

Addr MUX

FSR Reg

STATUS Reg

MUX

ALU

W Reg

RAM Addr

9

8

Indirect

Addr

AVSSAVDD

PORTA

8

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7

RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7

RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7

RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7

RE0
RE1
RE2
RE3/MCLR
RE4
RE5
RE6
RE7

RF0
RF1
RF2
RF3
RF4
RF5
RF6
RF7

RG0
RG1
RG2
RG3
RG4
RG5

Data EEPROM

256 bytes

PLVD

LCD

Comparators

Timer0

CCP1 CCP2

Timer1 Timer2 10-bit A/D

SSP

Addressable

USART

© 2007 Microchip Technology Inc. DS41250F-page 17

PIC16F913/914/916/917/946

TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS

Name Function

RA0/AN0/C1-/SEG12 RA0 TTL CMOS General purpose I/O.

AN0 AN — Analog input Channel 0.

C1- AN — Comparator 1 negative input.

SEG12 — AN LCD analog output.

RA1/AN1/C2-/SEG7 RA1 TTL CMOS General purpose I/O.

AN1 AN — Analog input Channel 1.

C2- AN — Comparator 2 negative input.

SEG7 — AN LCD analog output.

RA2/AN2/C2+/V

RA3/AN3/C1+/V
SEG15

RA4/C1OUT/T0CKI/SEG4 RA4 TTL CMOS General purpose I/O.

RA5/AN4/C2OUT/SS

RA6/OSC2/CLKOUT/T1OSO RA6 TTL CMOS General purpose I/O.

RA7/OSC1/CLKIN/T1OSI RA7 TTL CMOS General purpose I/O.

RB0/INT/SEG0 RB0 TTL CMOS General purpose I/O. Individually enabled pull-up.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.

2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.
4: I

REF-/COM2 RA2 TTL CMOS General purpose I/O.

AN2 AN — Analog input Channel 2.

C2+ AN — Comparator 2 positive input.

REF- AN — External A/D Voltage Reference – negative.

V

COM2 — AN LCD analog output.

REF+/COM3

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal

2

C Schmitt trigger inputs have special input levels.

(1)

/

RA3 TTL CMOS General purpose I/O.

AN3 AN — Analog input Channel 3.

C1+ AN — Comparator 1 positive input.

REF+ AN — External A/D Voltage Reference – positive.

V

COM3

SEG15 — AN LCD analog output.

C1OUT — CMOS Comparator 1 output.

T0CKI ST — Timer0 clock input.

SEG4 — AN LCD analog output.

/SEG5 RA5 TTL CMOS General purpose I/O.

AN4 AN — Analog input Channel 4.

C2OUT — CMOS Comparator 2 output.

SS

SEG5 — AN LCD analog output.

OSC2 — XTAL Crystal/Resonator.

CLKOUT — CMOS T

T1OSO — XTAL Timer1 oscillator output.

OSC1 XTAL — Crystal/Resonator.

CLKIN ST — Clock input.

T1OSI XTAL — Timer1 oscillator input.

INT ST — External interrupt pin.

SEG0 — AN LCD analog output.

Input

(1)

Output

Type

TTL — Slave select input.

Typ e

— AN LCD analog output.

OSC/4 reference clock.

Description

DS41250F-page 18 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)

Input

Name Function

RB1/SEG1 RB1 TTL CMOS General purpose I/O. Individually enabled pull-up.

SEG1 — AN LCD analog output.

RB2/SEG2 RB2 TTL CMOS General purpose I/O. Individually enabled pull-up.

SEG2 — AN LCD analog output.

RB3/SEG3 RB3 TTL CMOS General purpose I/O. Individually enabled pull-up.

SEG3 — AN LCD analog output.

RB4/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled

COM0 — AN LCD analog output.

RB5/COM1 RB5 TTL CMOS General purpose I/O. Individually controlled

COM1 — AN LCD analog output.

RB6/ICSPCLK/ICDCK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled

ICSPCLK ST — ICSP™ clock.

ICDCK ST — ICD clock.

SEG14 — AN LCD analog output.

RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled inter-

ICSPDAT ST CMOS ICSP Data I/O.

ICDDAT ST CMOS ICD Data I/O.

SEG13 — AN LCD analog output.

RC0/VLCD1 RC0 ST CMOS General purpose I/O.

VLCD1 AN — LCD analog input.

RC1/VLCD2 RC1 ST CMOS General purpose I/O.

VLCD2 AN — LCD analog input.

RC2/VLCD3 RC2 ST CMOS General purpose I/O.

VLCD3 AN — LCD analog input.

RC3/SEG6 RC3 ST CMOS General purpose I/O.

SEG6 — AN LCD analog output.

RC4/T1G

RC5/T1CKI/CCP1/SEG10 RC5 ST CMOS General purpose I/O.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.

/SDO/SEG11 RC4 ST CMOS General purpose I/O.

T1G ST — Timer1 gate input.

SDO — CMOS Serial data output.

SEG11 — AN LCD analog output.

T1CKI ST — Timer1 clock input.

CCP1 ST CMOS Capture 1 input/Compare 1 output/PWM 1 output.

SEG10 — AN LCD analog output.

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal

2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.

2

4: I

C Schmitt trigger inputs have special input levels.

Type

Output

Typ e

Description

interrupt-on-change. Individually enabled pull-up.

interrupt-on-change. Individually enabled pull-up.

interrupt-on-change. Individually enabled pull-up.

rupt-on-change. Individually enabled pull-up.

© 2007 Microchip Technology Inc. DS41250F-page 19

PIC16F913/914/916/917/946

TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)

Name Function

Input

RC6/TX/CK/SCK/SCL/SEG9 RC6 ST CMOS General purpose I/O.

TX — CMOS USART asynchronous serial transmit.

CK ST CMOS USART synchronous serial clock.

SCK ST CMOS SPI clock.

SCL ST

SEG9 — AN LCD analog output.

RC7/RX/DT/SDI/SDA/SEG8 RC7 ST CMOS General purpose I/O.

RX ST — USART asynchronous serial receive.

DT ST CMOS USART synchronous serial data.

SDI ST CMOS SPI data input.

SDA ST

SEG8 — AN LCD analog output.

RD0/COM3

(1, 2)

RD0 ST CMOS General purpose I/O.

COM3 — AN LCD analog output.

(2)

RD1

RD2/CCP2

(2)

RD1 ST CMOS General purpose I/O.

RD2 ST CMOS General purpose I/O.

CCP2 ST CMOS Capture 2 input/Compare 2 output/PWM 2 output.

RD3/SEG16

(2)

RD3 ST CMOS General purpose I/O.

SEG16 — AN LCD analog output.

RD4/SEG17

(2)

RD4 ST CMOS General purpose I/O.

SEG17 — AN LCD analog output.

RD5/SEG18

(2)

RD5 ST CMOS General purpose I/O.

SEG18 — AN LCD analog output.

RD6/SEG19

(2)

RD6 ST CMOS General purpose I/O.

SEG19 — AN LCD analog output.

RD7/SEG20

(2)

RD7 ST CMOS General purpose I/O.

SEG20 — AN LCD analog output.

RE0/AN5/SEG21

(2)

RE0 ST CMOS General purpose I/O.

AN5 AN — Analog input Channel 5.

SEG21 — AN LCD analog output.

RE1/AN6/SEG22

(2)

RE1 ST CMOS General purpose I/O.

AN6 AN — Analog input Channel 6.

SEG22 — AN LCD analog output.

RE2/AN7/SEG23

(2)

RE2 ST CMOS General purpose I/O.

AN7 AN — Analog input Channel 7.

SEG23 — AN LCD analog output.

RE3/MCLR

/VPP RE3 ST — Digital input only.

MCLR ST — Master Clear with internal pull-up.

PP HV — Programming voltage.

V

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal

Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.

2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.

2

4: I

C Schmitt trigger inputs have special input levels.

Type

(4)

(4)

Output

Typ e

OD I2C™ clock.

OD I2C™ data.

Description

DS41250F-page 20 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)

Input

Name Function

RE4/SEG24

(3)

RE4 ST CMOS General purpose I/O.

SEG24 — AN LCD analog output.

RE5/SEG25

(3)

RE5 ST CMOS General purpose I/O.

SEG25 — AN LCD analog output.

RE6/SEG26

(3)

RE6 ST CMOS General purpose I/O.

SEG26 — AN LCD analog output.

RE7/SEG27

(3)

RE7 ST CMOS General purpose I/O.

SEG27 — AN LCD analog output.

RF0/SEG32

(3)

RF0 ST CMOS General purpose I/O.

SEG32 — AN LCD analog output.

RF1/SEG33

(3)

RF1 ST CMOS General purpose I/O.

SEG33 — AN LCD analog output.

RF2/SEG34

(3)

RF2 ST CMOS General purpose I/O.

SEG34 — AN LCD analog output.

RF3/SEG35

(3)

RF3 ST CMOS General purpose I/O.

SEG35 — AN LCD analog output.

RF4/SEG28

(3)

RF4 ST CMOS General purpose I/O.

SEG28 — AN LCD analog output.

RF5/SEG29

(3)

RF5 ST CMOS General purpose I/O.

SEG29 — AN LCD analog output.

RF6/SEG30

(3)

RF6 ST CMOS General purpose I/O.

SEG30 — AN LCD analog output.

RF7/SEG31

(3)

RF7 ST CMOS General purpose I/O.

SEG31 — AN LCD analog output.

RG0/SEG36

(3)

RG0 ST CMOS General purpose I/O.

SEG36 — AN LCD analog output.

RG1/SEG37

(3)

RG1 ST CMOS General purpose I/O.

SEG37 — AN LCD analog output.

RG2/SEG38

(3)

RG2 ST CMOS General purpose I/O.

SEG38 — AN LCD analog output.

RG3/SEG39

(3)

RG3 ST CMOS General purpose I/O.

SEG39 — AN LCD analog output.

RG4/SEG40

(3)

RG4 ST CMOS General purpose I/O.

SEG10 — AN LCD analog output.

RG5/SEG41

(3)

RG5 ST CMOS General purpose I/O.

SEG41 — AN LCD analog output.

(3)

DD

AV

(3)

AVSS

DD VDD P — Power supply for microcontroller.

V

AVDD P — Analog power supply for microcontroller.

AVSS P — Analog ground reference for microcontroller.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal

Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.

2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.

2

4: I

C Schmitt trigger inputs have special input levels.

Type

Output

Typ e

Description

© 2007 Microchip Technology Inc. DS41250F-page 21

PIC16F913/914/916/917/946

TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)

Name Function

VSS VSS P — Ground reference for microcontroller.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal

Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.

2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.

2

4: I

C Schmitt trigger inputs have special input levels.

Input

Type

Output

Typ e

Description

DS41250F-page 22 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F91X/946 has a 13-bit program counter
capable of addressing a 4K x 14 program memory
space for the PIC16F913/914 (0000h-0FFFh) and an
8K x 14 program memory space for the PIC16F916/
917 and PIC16F946 (0000h-1FFFh). Accessing a
location above the memory boundaries for the
PIC16F913 and PIC16F914 will cause a wrap around
within the first 4K x 14 space. The Reset vector is at
0000h and the interrupt vector is at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16F913/914

pc<12:0>

CALL, RETURN
RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

13

0000h

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16F916/917/PIC16F946

pc<12:0>

CALL, RETURN
RETFIE, RETLW

On-chip

Program

Memory

Stack Level 1
Stack Level 2

Stack Level 8

Reset Vector

Interrupt Vector

Page 0

Page 1

Page 2

Page 3

13

0000h

0004h
0005h

07FFh
0800h

0FFFh
1000h

17FFh
1800h

1FFFh

On-chip

Program

Memory

Interrupt Vector

Page 0

Page 1

0004h
0005h

07FFh
0800h

0FFFh
1000h

1FFFh

© 2007 Microchip Technology Inc. DS41250F-page 23

PIC16F913/914/916/917/946

2.2 Data Memory Organization

The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.

RP1

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.

2.2.1 GENERAL PURPOSE REGISTER

The register file is organized as 256 x 8 bits in the
PIC16F913/914, 352 x 8 bits in the PIC16F916/917 and
336 x 8 bits in the PIC16F946. Each register is accessed
either directly or indirectly through the File Select
Register (FSR) (see Section 2.5 “Indirect Addressing,
INDF and FSR Registers”).

RP0

00→ Bank 0 is selected
01→ Bank 1 is selected
10→ Bank 2 is selected
11→ Bank 3 is selected

FILE

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1, 2-2,
2-3 and 2-4). These registers are static RAM.

The Special Function Registers can be classified into
two sets: core and peripheral. The Special Function
Registers associated with the “core” are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.

DS41250F-page 24 © 2007 Microchip Technology Inc.

PIC16F913/914/916/917/946

FIGURE 2-3: PIC16F913/916 SPECIAL FUNCTION REGISTERS

File File File File
Address Address Address Address

Indirect addr.

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h WDTCON 105h

PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h LCDCON 107h 187h

PORTE 09h TRISE 89h LVDCON 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch

PIR2 0Dh PIE2 8Dh EEADRL 10Dh EECON2
TMR1L 0Eh PCON 8Eh EEDATH 10Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h LCDDATA0 110h

TMR2 11h ANSEL 91h LCDDATA1 111h

T2CON 12h PR2 92h

SSPBUF 13h SSPADD 93h LCDDATA3 113h

SSPCON 14h SSPSTAT 94h LCDDATA4 114h

CCPR1L 15h WPUB 95h

CCPR1H 16h IOCB 96h LCDDATA6 116h

CCP1CON 17h CMCON1 97h LCDDATA7 117h

RCSTA 18h TXSTA 98h
TXREG 19h SPBRG 99h LCDDATA9 119h

RCREG 1Ah

ADRESH 1Eh ADRESL 9Eh 11 E h
ADCON0 1Fh ADCON1 9Fh 11Fh

(1)

00h Indirect addr.

08h 88h LCDPS 108h 188h

1Bh 9Bh 11B h
1Ch CMCON0 9Ch LCDSE0 11Ch
1Dh VRCON 9Dh LCDSE1 11Dh

20h

(1)

80h Indirect addr.

9Ah LCDDATA10 11Ah

A0h

(1)

100h Indirect addr.

Reserved 18Eh

112h

115h

118h

Purpose

Register

96 Bytes

120h

General

(2)

(1)

(1)

180h

185h

18Dh

190h

General

General
Purpose
Register

96 Bytes

7Fh FFh 17Fh 1FFh

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: On the PIC16F913, unimplemented data memory locations, read as ‘0’.

© 2007 Microchip Technology Inc. DS41250F-page 25

Purpose
Register

80 Bytes

accesses

70h-7Fh

EFh 16Fh 1EFh
F0h accesses

General
Purpose
Register

80 Bytes

70h-7Fh

170h accesses

70h-7Fh

1F0h

PIC16F913/914/916/917/946

FIGURE 2-4: PIC16F914/917 SPECIAL FUNCTION REGISTERS

File File File File
Address Address Address Address

Indirect addr.

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h LCDCON 107h 187h
PORTD 08h TRISD 88h LCDPS 108h
PORTE 09h TRISE 89h LVDCON 109h 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch

PIR2 0Dh PIE2 8Dh EEADRL 10Dh EECON2
TMR1L 0Eh PCON 8Eh EEDATH 10Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h LCDDATA0 110h

TMR2 11h ANSEL 91h LCDDATA1 111h

T2CON 12h PR2 92h LCDDATA2 112h

SSPBUF 13h SSPADD 93h LCDDATA3 113h

SSPCON 14h SSPSTAT 94h LCDDATA4 114h

CCPR1L 15h WPUB 95h LCDDATA5 115h

CCPR1H 16h IOCB 96h LCDDATA6 116h

CCP1CON 17h CMCON1 97h LCDDATA7 117h

RCSTA 18h TXSTA 98h LCDDATA8 118h
TXREG 19h SPBRG 99h LCDDATA9 119h

RCREG 1Ah

CCPR2L 1Bh 9Bh LCDDATA11 11Bh

CCPR2H 1Ch CMCON0 9Ch LCDSE0 11Ch

CCP2CON 1Dh VRCON 9Dh LCDSE1 11Dh

ADRESH 1Eh ADRESL 9Eh LCDSE2 11Eh
ADCON0 1Fh ADCON1 9Fh

(1)

00h Indirect addr.

20h

(1)

80h Indirect addr.

9Ah LCDDATA10 11Ah

A0h

(1)

100h Indirect addr.

Reserved 18Eh

General

Purpose

Register

96 Bytes

11Fh
120h

(2)

(1)

(1)

180h

185h

188h

18Dh

190h

General

General
Purpose
Register

96 Bytes

7Fh FFh 17Fh 1FFh

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: On the PIC16F914, unimplemented data memory locations, read as ‘0’.

DS41250F-page 26 © 2007 Microchip Technology Inc.

Purpose
Register

80 Bytes

accesses

70h-7Fh

EFh 16Fh 1EFh
F0h accesses

General
Purpose
Register

80 Bytes

70h-7Fh

170h accesses

70h-7Fh

1F0h

PIC16F913/914/916/917/946

FIGURE 2-5: PIC16F946 SPECIAL FUNCTION REGISTERS

File File File File
Address Address Address Address

Indirect addr.

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h TRISF 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h LCDCON 107h TRISG 187h
PORTD 08h TRISD 88h LCDPS 108h PORTF 188h
PORTE 09h TRISE 89h LVDCON 109h PORTG 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADRL 10Dh EECON2

TMR1L 0Eh PCON 8Eh EEDATH 10Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h LCDDATA0 110h LCDDATA12 190h

TMR2 11h ANSEL 91h LCDDATA1 111h LCDDATA13 191h

T2CON 12h PR2 92h LCDDATA2 112h LCDDATA14 192h

SSPBUF 13h SSPADD 93h LCDDATA3 113h LCDDATA15 193h

SSPCON 14h SSPSTAT 94h LCDDATA4 114h LCDDATA16 194h

CCPR1L 15h WPUB 95h LCDDATA5 115h LCDDATA17 195h
CCPR1H 16h IOCB 96h LCDDATA6 116h LCDDATA18 196h

CCP1CON 17h CMCON1 97h LCDDATA7 117h LCDDATA19 197h

RCSTA 18h TXSTA 98h LCDDATA8 118h LCDDATA20 198h
TXREG 19h SPBRG 99h LCDDATA9 119h LCDDATA21 199h

RCREG 1Ah
CCPR2L 1Bh 9Bh LCDDATA11 11Bh LCDDATA23 19Bh
CCPR2H 1Ch CMCON0 9Ch LCDSE0 11Ch LCDSE3 19Ch

CCP2CON 1Dh VRCON 9Dh LCDSE1 11Dh LCDSE4 19Dh

ADRESH 1Eh ADRESL 9Eh LCDSE2 11Eh LCDSE5 19Eh
ADCON0 1Fh ADCON1 9Fh

(1)

00h Indirect addr.

20h

(1)

80h Indirect addr.

9Ah LCDDATA10 11Ah LCDDATA22 19Ah

A0h

(1)

100h Indirect addr.

Reserved 18Eh

11F h 19Fh
120h

(1)

(1)

180h

18Dh

1A0h

General

General

Purpose
Register

96 Bytes

7Fh FFh 17Fh 1FFh

Bank 0Bank 1Bank 2Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

© 2007 Microchip Technology Inc. DS41250F-page 27

Purpose
Register

80 Bytes

accesses

70h-7Fh

EFh 16Fh 1EFh
F0h accesses

General
Purpose
Register

80 Bytes

70h-7Fh

General
Purpose
Register

80 Bytes

170h accesses

70h-7Fh

1F0h

PIC16F913/914/916/917/946

TABLE 2-1: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 41,226

01h TMR0 Timer0 Module Register xxxx xxxx 99,226

02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 40,226

03h STATUS IRP RP1 RP0 TO

04h FSR Indirect Data Memory Address Pointer xxxx xxxx 41,226

05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx 44,226

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54,226

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 62,226

08h PORTD

09h PORTE RE7

0Ah PCLATH

0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 34,226

0Ch PIR1

0Dh PIR2

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 102,226

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 102,226

10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

11h T MR2

12h T2CON

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 196,226

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 195,226

15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 213,226

16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 213,226

17h CCP1CON

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 131,226

19h TXREG USART Transmit Data Register 0000 0000 130,226

1Ah RCREG USART Receive Data Register 0000 0000 128,227

(2)

1Bh

(2)

1Ch

(2)

1Dh

1Eh ADRESH A/D Result Register High Byte xxxx xxxx 182,227

1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR

(2)

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 71,226

(3)

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 40,226

EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 37,226

OSFIF C2IF C1IF LCDIF —LVDIF— CCP2IF

Timer2 Module Register 0000 0000

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 108,226

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 212,226

CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 213,227

CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx 213,227

CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 212,227

2: PIC16F914/917 and PIC16F946 only, forced ‘0’ on PIC16F913/916.
3: PIC16F946 only, forced to ‘0’ on PIC16F91X.

RE6

(3)

RE5

(3)

(3)

RE4

Reset and Watchdog Timer Reset during normal operation.

PD ZDCC0001 1xxx 32,226

RE3 RE2

(2)

(2)

RE1

TMR1CS TMR1ON 0000 0000 105,226

RE0

ADON 0000 0000 180,227

Val ue o n

POR, BOR

(2)

xxxx xxxx 76,226

(2)

0000 -0-0 38,226

Page

107,226

DS41250F-page 28 © 2007 Microchip Technology Inc.