MICROCHIP PIC16F8X Technical data
查询16F84供应商
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18-pin Flash/EEPROM 8-Bit Microcontrollers
Devices Included in this Data Sheet:
• PIC16F83
• PIC16F84
• PIC16CR83
• PIC16CR84
• Extended voltage range devices available
(PIC16 LF 8X, PIC16 LCR 8X)
High Performance RISC CPU Features:
• Only 35 single word instructions to learn
• All instructions single cycle except for program
branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
Device
PIC16F83 512 Flash 36 64 10
PIC16F84 1 K Flash 68 64 10
PIC16CR83 512 ROM 36 64 10
PIC16CR84 1 K ROM 68 64 10
• 14-bit wide instructions
• 8-bit wide data path
• 15 special function hardware registers
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Four interrupt sources:
- External RB0/INT pin
- TMR0 timer overflow
- PORTB<7:4> interrupt on change
- Data EEPROM write complete
• 1000 erase/write cycles Flash program memory
• 10,000,000 erase/write cycles EEPROM data memory
• EEPROM Data Retention > 40 years
Peripheral Features:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 20 mA source max. per pin
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
DC - 400 ns instruction cycle
Program
Memory
(words)
Data
RAM
(bytes)
Data
EEPROM
(bytes)
Max.
Freq
(MHz)
PIC16F8X
Pin Diagrams
PDIP, SOIC
RA2
RA3
RA4/T0CKI
MCLR
VSS
RB0/INT
RB1
RB2
RB3
•1
2
PIC16CR8X
3
4
5
6
7
8
9
PIC16F8X
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™) - via two
pins (ROM devices support only Data EEPROM
programming)
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Code-protection
• Power saving SLEEP mode
• Selectable oscillator options
CMOS Flash/EEPROM Technology:
• Low-power, high-speed technology
• Fully static design
• Wide operating voltage range:
- Commercial: 2.0V to 6.0V
- Industrial: 2.0V to 6.0V
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 15 µ A typical @ 2V, 32 kHz
- < 1 µ A typical standby current @ 2V
18
17
16
15
14
13
12
11
10
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
DD
V
RB7
RB6
RB5
RB4
1998 Microchip Technology Inc. DS30430C-page 1
PIC16F8X
Table of Contents
1.0 General Description...................................................................................................................................................................... 3
2.0 PIC16F8X Device Varieties.......................................................................................................................................................... 5
3.0 Architectural Overview.................................................................................................................................................................. 7
4.0 Memory Organization ................................................................................................................................................................. 11
5.0 I/O Ports...................................................................................................................................................................................... 21
6.0 Timer0 Module and TMR0 Register............................................................................................................................................ 27
7.0 Data EEPROM Memory.............................................................................................................................................................. 33
8.0 Special Features of the CPU...................................................................................................................................................... 37
9.0 Instruction Set Summary ............................................................................................................................................................ 53
10.0 Development Support................................................................................................................................................................. 69
11.0 Electrical Characteristics for PIC16F83 and PIC16F84.............................................................................................................. 73
12.0 Electrical Characteristics for PIC16CR83 and PIC16CR84........................................................................................................ 85
13.0 DC & AC Characteristics Graphs/Tables.................................................................................................................................... 97
14.0 Packaging Information.............................................................................................................................................................. 109
Appendix A: Feature Improvements - From PIC16C5X To PIC16F8X.......................................................................................... 113
Appendix B: Code Compatibility - from PIC16C5X to PIC16F8X.................................................................................................. 113
Appendix C: What’s New In This Data Sheet................................................................................................................................. 114
Appendix D: What’s Changed In This Data Sheet ......................................................................................................................... 114
Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 115
Index ................................................................................................................................................................................................. 117
On-Line Support................................................................................................................................................................................. 119
Reader Response.............................................................................................................................................................................. 120
PIC16F8X Product Identification System........................................................................................................................................... 121
Sales and Support.............................................................................................................................................................................. 121
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of
time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you
find any information that is missing or appears in error, please use the reader response f orm in the back of this data
sheet to inform us. We appreciate your assistance in making this a better document.
DS30430C-page 2
1998 Microchip Technology Inc.
PIC16F8X
1.0 GENERAL DESCRIPTION
The PIC16F8X is a group in the PIC16CXX family of
low-cost, high-performance, CMOS, fully-static, 8-bit
microcontrollers. This group contains the following
devices:
• PIC16F83
• PIC16F84
• PIC16CR83
• PIC16CR84
All PICmicro™ microcontrollers employ an advanced
RISC architecture. PIC16F8X devices have enhanced
core features, eight-level deep stack, and multiple
internal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with a separate
8-bit wide data bus. The two stage instruction pipeline
allows all instructions to execute in a single cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set is
used to achieve a very high performance level.
PIC16F8X microcontrollers typically achieve a 2:1 code
compression and up to a 4:1 speed improvement (at 20
MHz) over other 8-bit microcontrollers in their class.
The PIC16F8X has up to 68 bytes of RAM, 64 bytes of
Data EEPROM memory, and 13 I/O pins. A timer/
counter is also available.
The PIC16CXX family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power saving.
The user can wake the chip from sleep through sev eral
external and internal interrupts and resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
The devices with Flash program memory allow the
same device package to be used for prototyping and
production. In-circuit reprogrammability allows the
code to be updated without the device being removed
from the end application. This is useful in the
development of many applications where the device
may not be easily accessible, but the prototypes may
require code updates. This is also useful for remote
applications where the code may need to be updated
(such as rate information).
Table 1-1 lists the features of the PIC16F8X. A simplified block diagram of the PIC16F8X is shown in
Figure 3-1.
The PIC16F8X fits perfectly in applications ranging
from high speed automotive and appliance motor
control to low-power remote sensors, electronic locks,
security devices and smart cards. The Flash/EEPROM
technology makes customization of application
programs (transmitter codes, motor speeds, receiver
frequencies, security codes, etc.) extremely fast and
convenient. The small footprint packages make this
microcontroller series perfect for all applications with
space limitations. Low-cost, low-power, high
performance, ease-of-use and I/O flexibility make the
PIC16F8X very versatile even in areas where no
microcontroller use has been considered before
(e.g., timer functions; serial communication; capture,
compare and PWM functions; and co-processor
applications).
The serial in-system programming feature (via two
pins) offers flexibility of customizing the product after
complete assembly and testing. This feature can be
used to serialize a product, store calibration data, or
program the device with the current firmware before
shipping.
1.1 F
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X devices can be easily ported to
PIC16F8X devices (Appendix B).
1.2 De
The PIC16CXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
amily and Upward Compatibility
velopment Support
1998 Microchip Technology Inc. DS30430C-page 3
PIC16F8X
TABLE 1-1 PIC16F8X FAMILY OF DEVICES
PIC16F83
Clock
Memory
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0
Features
All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.
Maximum Frequency
of Operation (MHz)
Flash Program Memory 512 — 1K —
EEPROM Program Memory — — — —
ROM Program Memory — 512 — 1K
Data Memory (bytes) 36 36 68 68
Data EEPROM (bytes) 64 64 64 64
Interrupt Sources 4 4 4 4
I/O Pins 13 13 13 13
Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0
Packages 18-pin DIP,
10 10 10 10
SOIC
PIC16CR83 PIC16F84 PIC16CR84
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
DS30430C-page 4
1998 Microchip Technology Inc.
PIC16F8X
2.0 PIC16F8X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements the proper device option can be selected
using the information in this section. When placing
orders, please use the “PIC16F8X Product
Identification System” at the back of this data sheet to
specify the correct part number.
There are four device “types” as indicated in the device
number.
1. F , as in PIC16 F 84. These devices have Flash
program memory and operate over the standard
voltage range.
2. LF , as in PIC16 LF 84. These devices have Flash
program memory and operate over an extended
voltage range.
3. CR , as in PIC16 CR 83. These devices have
ROM program memory and operate over the
standard voltage range.
4. LCR , as in PIC16 LCR 84. These devices have
ROM program memory and operate over an
extended voltage range.
When discussing memory maps and other architectural
features, the use of F and CR also implies the LF and
LCR versions.
2.1 Flash De
These devices are offered in the lower cost plastic
package, even though the device can be erased and
reprogrammed. This allo ws the same device to be used
for prototype development and pilot programs as well
as production.
A further advantage of the electrically-erasable Flash
version is that it can be erased and reprogrammed incircuit, or by device programmers, such as Microchip's
PICSTART
2.2 Quic
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices have all Flash
locations and configuration options already programmed by the factory. Certain code and prototype
verification procedures do apply before production
shipments are available.
For information on submitting a QTP code, please
contact your Microchip Regional Sales Office.
vices
®
Plus or PRO MATE
®
II programmers.
k-Turnaround-Production (QTP)
2.3 Serializ
Microchip offers the unique programming service
where a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random
or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
For information on submitting a SQTP code, please
contact your Microchip Regional Sales Office.
2.4 R
Some of Microchip’s devices have a corresponding
device where the program memory is a ROM. These
devices give a cost savings o ver Microchip’s traditional
user programmed devices (EPROM, EEPROM).
ROM devices (PIC16CR8X) do not allow serialization
information in the program memory space. The user
may program this information into the Data EEPROM.
For information on submitting a ROM code, please
contact your Microchip Regional Sales Office.
ed Quick-Turnaround-
Production (SQTP ) Devices
SM
OM Devices
1998 Microchip Technology Inc. DS30430C-page 5
PIC16F8X
NOTES:
DS30430C-page 6
1998 Microchip Technology Inc.
PIC16F8X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CXX uses a Harvard architecture. This
architecture has the program and data accessed from
separate memories. So the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions
to be sized differently than the 8-bit wide data word.
PIC16CXX opcodes are 14-bits wide, enabling single
word instructions. The full 14-bit wide prog ram memory
bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instr uctions (Example 3-1). Consequently , all instructions ex ecute in a single cycle except for program branches.
The PIC16F83 and PIC16CR83 address 512 x 14 of
program memory, and the PIC16F84 and PIC16CR84
address 1K x 14 program memory. All program memory is internal.
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. An orthogonal (symmetrical)
instruction set makes it possible to carry out any operation on any register using any addressing mode. This
symmetrical nature and lack of ‘special optimal
situations’ make programming with the PIC16CXX
simple yet efficient. In addition, the learning curve is
reduced significantly.
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
data in the working register and any register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register), and the other operand is a file register or
an immediate constant. In single operand instructions,
the operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the ST ATUS register. The C and DC bits
operate as a borro
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
A simplified block diagram for the PIC16F8X is shown
in Figure 3-1, its corresponding pin description is
shown in Table 3-1.
w and digit borrow out bit,
1998 Microchip Technology Inc. DS30430C-page 7
PIC16F8X
FIGURE 3-1: PIC16F8X BLOCK DIAGRAM
13
Flash/ROM
Program
Memory
PIC16F83/CR83
512 x 14
PIC16F84/CR84
1K x 14
Program
14
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
5
8
Data Bus
RAM
File Registers
PIC16F83/CR83
36 x 8
PIC16F84/CR84
68 x 8
7
RAM Addr
Addr Mux
7
FSR reg
STATUS reg
8
Indirect
Addr
EEPROM Data Memory
EEDATA
TMR0
EEPROM
Data Memory
64 x 8
EEADR
RA4/T0CKI
Instruction
Decode &
Control
Timing
Generation
OSC2/CLKOUT
OSC1/CLKIN
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR
VDD, VSS
ALU
W reg
MUX
I/O Ports
8
RA3:RA0
RB7:RB1
RB0/INT
DS30430C-page 8
1998 Microchip Technology Inc.
(
PIC16F8X
TABLE 3-1 PIC16F8X PINOUT DESCRIPTION
DIP
Pin Name
OSC1/CLKIN 16 16 I ST/CMOS
OSC2/CLKOUT 15 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal
MCLR
RA0 17 17 I/O TTL
RA1 18 18 I/O TTL
RA2 1 1 I/O TTL
RA3 2 2 I/O TTL
RA4/T0CKI 3 3 I/O ST Can also be selected to be the clock input to the TMR0
RB0/INT 6 6 I/O TTL/ST
RB1 7 7 I/O TTL
RB2 8 8 I/O TTL
RB3 9 9 I/O TTL
RB4 10 10 I/O TTL Interrupt on change pin.
RB5 11 11 I/O TTL Interrupt on change pin.
RB6 12 12 I/O TTL/ST
RB7 13 13 I/O TTL/ST
V
SS
V
DD
Legend: I= input O = output I/O = Input/Output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
SOIC
No.
4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an
5 5 P — Ground reference for logic and I/O pins.
14 14 P — Positive supply for logic and I/O pins.
— = Not used TTL = TTL input ST = Schmitt Trigger input
No.
I/O/P
Type
Buffer
Type
Description
(3)
Oscillator crystal input/external clock source input.
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1, and denotes the instruction cycle
rate.
active low reset to the device.
PORTA is a bi-directional I/O port.
timer/counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
1)
RB0/INT can also be selected as an external interrupt pin.
(2)
Interrupt on change pin. Serial programming clock.
(2)
Interrupt on change pin. Serial programming data.
1998 Microchip Technology Inc. DS30430C-page 9
PIC16F8X
3.1 Clocking Scheme/Instruction Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2 Q3 Q4
OSC1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
Q1
Q1
Fetch INST (PC)
Execute INST (PC-1)
PC
Q1
Execute INST (PC)
3.2 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO )
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the f etched instruction is latched
into the “Instruction Register” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q2 Q3 Q4
PC+1 PC+2
Fetch INST (PC+1)
Q2 Q3 Q4
Q1
Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTA, BIT3
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30430C-page 10
Fetch 1 Execute 1
Fetch 2 Execute 2
Fetch 3 Execute 3
Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
1998 Microchip Technology Inc.
PIC16F8X
4.0 MEMORY ORGANIZATION
There are two memory blocks in the PIC16F8X. These
are the program memory and the data memory. Each
block has its own bus , so that access to each bloc k can
occur during the same oscillator cycle.
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into the data memory, b ut is indirectly mapped. That is,
an indirect address pointer specifies the address of the
data EEPROM memor y to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0.
4.1 Pr
The PIC16FXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. For
the PIC16F83 and PIC16CR83, the first 512 x 14
(0000h-01FFh) are physically implemented
(Figure 4-1). For the PIC16F84 and PIC16CR84, the
first 1K x 14 (0000h-03FFh) are physically implemented (Figure 4-2). Accessing a location above the
physically implemented address will cause a wraparound. For example, for the PIC16F84 locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h
will be the same instruction.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
ogram Memory Organization
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK PIC16F83/CR83
CALL, RETURN
RETFIE, RETLW
Peripheral Interrupt Vector
Space
User Memory
PC<12:0>
Stack Level 1
Stack Level 8
Reset Vector
13
•
•
•
0000h
0004h
1FFh
1FFFh
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK PIC16F84/CR84
CALL, RETURN
RETFIE, RETLW
Peripheral Interrupt Vector
PC<12:0>
Stack Level 1
Stack Level 8
Reset Vector
13
•
•
•
0000h
0004h
Space
User Memory
3FFh
1FFFh
1998 Microchip Technology Inc. DS30430C-page 11
PIC16F8X
4.2 Data Memory Organization
The data memory is partitioned into two areas. The first
is the Special Function Registers (SFR) area, while the
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device.
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general
purpose RAM. The bank ed areas of the SFR are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the STATUS Register.
Figure 4-1 and Figure 4-2 show the data memory map
organization.
Instructions MOVWF and MOVF can move values from the
W register to any location in the register file (“F”), and
vice-versa.
The entire data memory can be accessed either
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR)
(Section 4.5). Indirect addressing uses the present
value of the RP1:RP0 bits for access into the banked
areas of data memory.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (ST ATUS<5>). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are General Purpose Registers implemented as static RAM.
4.2.1 GENERAL PURPOSE REGISTER FILE
All devices have some amount of General Purpose
Register (GPR) area. Each GPR is 8 bits wide and is
accessed either directly or indirectly through the FSR
(Section 4.5).
The GPR addresses in bank 1 are mapped to
addresses in bank 0. As an example, addressing location 0Ch or 8Ch will access the same GPR.
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (Figure 4-1, Figure 4-2
and Table 4-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
The special function registers can be classified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for that specific feature.
DS30430C-page 12
1998 Microchip Technology Inc.
PIC16F8X
FIGURE 4-1: REGISTER FILE MAP -
PIC16F83/CR83
File Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
2Fh
30h
Indirect addr.
(1)
TMR0 OPTION
PCL
STATUS
FSR
PORTA
PORTB
EEDATA
EEADR
PCLATH
INTCON
36
General
Purpose
registers
(SRAM)
Indirect addr.
PCL
STATUS
FSR
TRISA
TRISB
EECON1
EECON2
PCLATH
INTCON
Mapped
(accesses)
in Bank 0
(1)
(1)
File Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
AFh
B0h
FIGURE 4-2: REGISTER FILE MAP -
PIC16F84/CR84
File Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
4Fh
50h
Indirect addr.
(1)
TMR0 OPTION
PCL
STATUS
FSR
PORTA
PORTB
EEDATA
EEADR
PCLATH
INTCON
68
General
Purpose
registers
(SRAM)
Indirect addr.
PCL
STATUS
FSR
TRISA
TRISB
EECON1
EECON2
PCLATH
INTCON
Mapped
(accesses)
in Bank 0
(1)
(1)
File Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
CFh
D0h
7Fh
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
1998 Microchip Technology Inc. DS30430C-page 13
Bank 0
Bank 1
FFh
7Fh
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
Bank 0
Bank 1
FFh
PIC16F8X
TABLE 4-1 REGISTER FILE SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
00h INDF Uses contents of FSR to address data memory (not a physical register)
01h TMR0 8-bit real-time clock/counter
02h PCL Low order 8 bits of the Program Counter (PC)
03h STATUS
04h FSR Indirect data memory address pointer 0
05h PORTA
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu
07h
08h EEDATA EEPROM data register
09h EEADR EEPROM address register
0Ah PCLATH
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Bank 1
80h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
81h
82h PCL Low order 8 bits of Program Counter (PC) 0000 0000 0000 0000
83h STATUS
84h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
85h TRISA
86h TRISB PORTB data direction register 1111 1111 1111 1111
87h
88h EECON1 — — — EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ---0Ah PCLATH — — — Write buffer for upper 5 bits of the PC
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
(2)
IRP RP1 RP0
— — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
Unimplemented location, read as '0'
— — — Write buffer for upper 5 bits of the PC
OPTION_
REG
(2)
IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
INTEDG T0CS T0SE PSA PS2 PS1 PS0
RBPU
— — — PORTA data direction register ---1 1111 ---1 1111
Unimplemented location, read as '0' ---- ---- ---- ----
O
T
PD Z DC C 0001 1xxx 000q quuu
(1)
(1)
Value on
Power-on
Reset
---- ---- ---- ---xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
---- ---xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
1111 1111 1111 1111
---0 0000 ---0 0000
Value on all
other resets
(Note3)
---- ----
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never trans-
ferred to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30430C-page 14
1998 Microchip Technology Inc.
PIC16F8X
4.2.2.1 STATUS REGISTER
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bit for
data memory.
As with any register, the STATUS register can be the
destination for any instruction. If the STA TUS register is
the destination for an instruction that affects the Z, DC
or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to device logic.
Furthermore, the T
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This lea v es the STATUS register
as 000u u1uu (where u = unchanged).
O and PD bits are not writable.
Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the ST ATUS register (T able 9-2)
because these instructions do not affect any status bit.
Note 1: The IRP and RP1 bits (STATUS<7:6>) are
not used by the PIC16F8X and should be
programmed as cleared. Use of these bits
as general purpose R/W bits is NOT
recommended, since this may affect
upward compatibility with future products.
Note 2: The C and DC bits operate as a borro
and digit borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
Note 3: When the STATUS register is the
destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
FIGURE 4-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
0 = Bank 0, 1 (00h - FFh)
1 = Bank 2, 3 (100h - 1FFh)
The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.
bit 4: T
bit 3: PD
bit 2: Z: Zero bit
bit 1: DC: Digit carry/borro
bit 0: C: Carry/borro
O: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:For borro
the second operand. For rotate ( RRF, RLF) instructions, this bit is loaded with either the high or low
order bit of the source register.
w bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)
w bit (for ADDWF and ADDLW instructions)
w the polarity is reversed. A subtraction is executed by adding the two’s complement of
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
w
1998 Microchip Technology Inc. DS30430C-page 15
PIC16F8X
4.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external INT interrupt,
Note: When the prescaler is assigned to
the WDT (PSA = '1'), TMR0 has a 1:1
prescaler assignment.
TMR0, and the weak pull-ups on PORTB.
FIGURE 4-1: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled (by individual port latch values)
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
DS30430C-page 16 1998 Microchip Technology Inc.
PIC16F8X
4.2.2.3 INTCON REGISTER
The INTCON register is a readable and writable
register which contains the various enable bits for all
interrupt sources.
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
FIGURE 4-1: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
Note: For the operation of the interrupt structure, please refer to Section 8.5.
bit 6: EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 overflow interrupt flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow
bit 1: INTF: RB0/INT Interrupt Flag bit
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
read as ‘0’
1998 Microchip Technology Inc. DS30430C-page 17
PIC16F8X
4.3 Program Counter: PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low
byte is the PCL register, which is a readable and
writable register. The high b yte of the PC (PC<12:8>) is
not directly readable nor writable and comes from the
PCLATH register. The PCLATH (PC latch high) register
is a holding register for PC<12:8>. The contents of
PCLATH are transferred to the upper byte of the
program counter when the PC is loaded with a new
value. This occurs dur ing a CALL, GOTO or a write to
PCL. The high bits of PC are loaded from PCLATH as
shown in Figure 4-1.
FIGURE 4-1: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
8 7
PCLATH<4:3>
PCLATH
4.3.1 COMPUTED GOTO
A computed GOTO is accomplished b y adding an offset
to the program counter (ADDWF PCL). When doing a tab le
read using a computed GOTO method, care should be
exercised if the table location crosses a PCL memory
boundary (each 256 word block). Ref er to the application
note
“Implementing a Table Read”
4.3.2 PROGRAM MEMORY PAGING
The PIC16F83 and PIC16CR83 have 512 words of pro-
gram memory. The PIC16F84 and PIC16CR84 have
1K of program memory. The CALL and GOTO instructions have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. For future PIC16F8X program memory
expansion, there must be another two bits to specify
the program memory page. These paging bits come
from the PCLA TH<4:3> bits (Figure 4-1). When doing a
CALL or a GOTO instruction, the user must ensure that
these page bits (PCLATH<4:3>) are programmed to
the desired program memory page. If a CALL instruction (or interrupt) is executed, the entire 13-bit PC is
“pushed” onto the stack (see next section). Therefore,
8
11
INST with PCL
as dest
ALU result
GOTO, CALL
Opcode <10:0>
(AN556).
manipulation of the PCLATH<4:3> is not required for
the return instructions (which “pops” the PC from the
stack).
Note: The PIC16F8X ignores the PCLA TH<4:3>
bits, which are used for program memory
pages 1, 2 and 3 (0800h - 1FFFh). The
use of PCLATH<4:3> as general pur pose
R/W bits is not recommended since this
may affect upward compatibility with
future products.
4.4 Stack
The PIC16FXX has an 8 deep x 13-bit wide hardware
stack (Figure 4-1). The stack space is not part of either
program or data space and the stack pointer is not
readable or writable.
The entire 13-bit PC is “pushed” onto the stac k when a
CALL instruction is executed or an interrupt is acknowledged. The stack is “popped” in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a push or a pop operation.
Note: There are no instruction mnemonics
called push or pop. These are actions that
occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address.
The stack operates as a circular buffer. That is, after the
stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. The
tenth push overwrites the second push (and so on).
If the stack is effectively popped nine times, the PC
value is the same as the value from the first pop.
Note: There are no status bits to indicate stack
overflow or stack underflow conditions.
DS30430C-page 18 1998 Microchip Technology Inc.
PIC16F8X
4.5 Indirect Addressing; INDF and FSR
Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer
). This is indirect addressing.
EXAMPLE 4-1: INDIRECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
FIGURE 4-1: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1 RP0 6
bank select location select
from opcode
0 IRP 7 (FSR) 0
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
EXAMPLE 4-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (ST ATUS<7>), as
shown in Figure 4-1. However, IRP is not used in the
PIC16F8X.
Indirect Addressing
bank select location select
00 01 10 11
00h
0Bh
0Ch
Data
(3)
Memory
Note 1: PIC16F83 and PIC16CR83 devices.
2: PIC16F84 and PIC16CR84 devices
3: For memory map detail see Figure 4-1.
1998 Microchip Technology Inc. DS30430C-page 19
2Fh
30h
4Fh
50h
7Fh
(1)
(1)
(2)
(2)
Bank 0 Bank 1 Bank 2 Bank 3
Addresses
map back
to Bank 0
not used
not used
00h
7Fh
PIC16F8X
NOTES:
DS30430C-page 20 1998 Microchip Technology Inc.
PIC16F8X
5.0 I/O PORTS
The PIC16F8X has two ports, PORTA and PORTB.
Some port pins are multiplexed with an alternate function for other features on the device.
5.1 PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. All other RA port pins
have TTL input levels and full CMOS output drivers. All
pins have data direction bits (TRIS registers) which can
configure these pins as output or input.
Setting a TRISA bit (=1) will make the corresponding
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedance mode. Clearing a TRISA bit
(=0) will make the corresponding PORTA pin an output,
i.e., put the contents of the output latch on the selected
pin.
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
The RA4 pin is multiplexed with the TMR0 clock input.
FIGURE 5-1: BLOCK DIAGRAM OF PINS
Data
bus
WR
Port
WR
TRIS
RA3:RA0
CK
Data Latch
D
CK
QD
VDD
Q
Q
Q
P
N
VSS
I/O pin
EXAMPLE 5-1: INITIALIZING PORTA
CLRF PORTA ; Initialize PORTA by
; setting output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x0F ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA4 as outputs
; TRISA<7:5> are always
; read as '0'.
FIGURE 5-2: BLOCK DIAGRAM OF PIN RA4
Data
bus
WR
PORT
WR
TRIS
RD PORT
TMR0 clock input
Note: I/O pin has protection diodes to V
QD
Q
CK
Data Latch
QD
Q
CK
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
Q D
EN
EN
N
V
RA4 pin
SS
SS only.
TRIS Latch
RD TRIS
RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
1998 Microchip Technology Inc. DS30430C-page 21
Q D
EN
TTL
input
buffer
PIC16F8X
TABLE 5-1 PORTA FUNCTIONS
Name Bit0 Buffer Type Function
RA0 bit0 TTL Input/output
RA1 bit1 TTL Input/output
RA2 bit2 TTL Input/output
RA3 bit3 TTL Input/output
RA4/T0CKI bit4 ST Input/output or external clock input for TMR0.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05h PORT A
85h TRISA
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
— — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
— — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Output is open drain type.
Value on
Power-on
Reset
Value on all
other resets
DS30430C-page 22 1998 Microchip Technology Inc.
PIC16F8X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' on
any bit in the TRISB register puts the corresponding
output driver in a hi-impedance mode. A '0' on any bit
in the TRISB register puts the contents of the output
latch on the selected pin(s).
Each of the PORTB pins have a weak internal pull-up.
A single control bit can turn on all the pull-ups. This is
done by clearing the RBPU
(OPTION_REG<7>) bit.
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The pins value in input mode
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of the pins are
OR’ed together to generate the RB port
change interrupt.
FIGURE 5-3: BLOCK DIAGRAM OF PINS
RB7:RB4
V
EN
EN
RD Port
DD and VSS.
DD
P
weak
pull-up
I/O
pin
TTL
Input
Buffer
(2)
(1)
RBPU
Data bus
WR Port
WR TRIS
Set RBIF
From other
RB7:RB4 pins
Note 1: TRISB = '1' enables weak pull-up
2: I/O pins have diode protection to V
Data Latch
QD
CK
TRIS Latch
QD
CK
RD TRIS
RD Port
= '0' in the OPTION_REG register).
(if RBPU
Latch
Q D
Q D
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Read (or write) PORTB. This will end the mis-
match condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set the RBIF bit.
Reading PORTB will end the mismatch condition, and
allow the RBIF bit to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (see AN552 in the
Embedded Control Handbook).
Note 1: For a change on the I/O pin to be
recognized, the pulse width must be at
least T
CY (4/fOSC) wide.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-4: BLOCK DIAGRAM OF PINS
RB3:RB0
DD
TTL
Input
Buffer
Q D
EN
DD and VSS.
V
weak
P
pull-up
RD Port
I/O
(2)
pin
(1)
RBPU
Data bus
WR Port
WR TRIS
RB0/INT
Note 1: TRISB = '1' enables weak pull-up
(if RBPU
2: I/O pins have diode protection to V
Data Latch
QD
CK
TRIS Latch
QD
CK
RD TRIS
RD Port
Schmitt Trigger
Buffer
= '0' in the OPTION_REG register).
1998 Microchip Technology Inc. DS30430C-page 23
PIC16F8X
EXAMPLE 5-1: INITIALIZING PORTB
CLRF PORTB ; Initialize PORTB by
; setting output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
TABLE 5-3 PORTB FUNCTIONS
Name Bit Buffer Type I/O Consistency Function
(1)
RB0/INT bit0 TTL/ST
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable
RB6 bit6 TTL/ST
RB7 bit7 TTL/ST
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
OPTION_
81h
REG
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
INTEDG T0CS T0SE PSA PS2 PS1 PS0
RBPU
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
weak pull-up.
weak pull-up.
(2)
Input/output pin (with interrupt on change). Internal software programmab le
weak pull-up. Serial programming clock.
(2)
Input/output pin (with interrupt on change). Internal software programmab le
weak pull-up. Serial programming data.
Value on
Power-on
Reset
1111 1111 1111 1111
Value on all
other resets
DS30430C-page 24 1998 Microchip Technology Inc.
PIC16F8X
5.3 I/O Programming Considerations
5.3.1 BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, ex ecute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(i.e., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the content
of the data latch is unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(i.e., BCF, BSF , etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output current may damage the chip.
5.3.2 SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-5). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such that the pin voltage stabilizes (load dependent)
before the next instruction which causes that file to be
read into the CPU is executed. Otherwise, the previous
state of that pin may be read into the CPU rather than
the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
Example 5-1 shows the effect of two sequential
read-modify-write instructions (e.g., BCF, BSF , etc.) on
an I/O port.
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial PORT settings: PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
; PORT latch PORT pins
; ---------- -------- BCF PORTB, 7 ; 01pp ppp 11pp ppp
BCF PORTB, 6 ; 10pp ppp 11pp ppp
BSF STATUS, RP0 ;
BCF TRISB, 7 ; 10pp ppp 11pp ppp
BCF TRISB, 6 ; 10pp ppp 10pp ppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
FIGURE 5-5: SUCCESSIVE I/O OPERATION
Q4
Q3
NOP
Port pin
sampled here
Q1 Q2
write to
PORTB
Q3
Q4
Q1 Q2
TPD
MOVF PORTB,W
Q4
Q3
Q1 Q2
PC PC + 1 PC + 2
PC
Instruction
RB7:RB0
Instruction
executed
1998 Microchip Technology Inc. DS30430C-page 25
fetched
MOVWF PORTB
write to
PORTB
Q1 Q2
MOVF PORTB,W
MOVWF PORTB
Q3
PC + 3
NOP
NOP
Q4
Note:
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25TCY - TPD)
where TCY = instruction cycle
TPD = propagation delay
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
PIC16F8X
NOTES:
DS30430C-page 26 1998 Microchip Technology Inc.
PIC16F8X
6.0 TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In timer mode, the Timer0 module (Figure 6-1) will increment every instruction cycle
(without prescaler). If the TMR0 register is written, the
increment is inhibited for the following two cycles
(Figure 6-2 and Figure 6-3). The user can work around
this by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode TMR0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
edge select bit, T0SE (OPTION_REG<4>). Clearing bit
T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2.
The prescaler is shared between the Timer0 Module
and the Watchdog Timer. The prescaler assignment is
controlled, in software, by control bit PSA
(OPTION_REG<3>). Clearing bit PSA will assign the
prescaler to the Timer0 Module. The prescaler is not
readable or writable. When the prescaler (Section 6.3)
is assigned to the Timer0 Module, the prescale value
(1:2, 1:4, ..., 1:256) is software selectable.
6.1 TMR0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
the T0IF bit (INTCON<2>). The interrupt can be
masked by clearing enable bit T0IE (INTCON<5>). The
T0IF bit must be cleared in software by the Timer0
Module interrupt service routine before re-enabling this
interrupt. The TMR0 interrupt (Figure 6-4) cannot wake
the processor from SLEEP since the timer is shut off
during SLEEP.
The incrementing edge is determined by the T0 source
FIGURE 6-1: TMR0 BLOCK DIAGRAM
FOSC/4
RA4/T0CKI
pin
T0SE
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
0
1
T0CS
Programmable
Prescaler
3
PS2, PS1, PS0
1
0
PSA
PSout
Sync with
Internal
clocks
(2 cycle delay)
PSout
Data bus
8
TMR0 register
Set bit T0IF
on Overflow
FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4
PC
Instruction
Fetch
TMR0
Instruction
Executed
1998 Microchip Technology Inc. DS30430C-page 27
T0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC PC+1 PC+2
MOVWF TMR0
T0+1 T0+2 NT0 NT0 NT0
MOVF TMR0,W
Write TMR0
executed
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
PC+3
Read TMR0
reads NT0
PC+4
Read TMR0
reads NT0
PC+5 PC+6
NT0+1 NT0+2
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0 + 2
T0
PIC16F8X
FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
MOVWF TMR0
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
Write TMR0
executed
PC
Instruction
Fetch
TMR0
Instruction
Execute
Q1 Q2 Q3 Q4
T0 NT0+1
FIGURE 6-4: TMR0 INTERRUPT TIMING
Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
(3)
CLKOUT
TMR0 timer
4
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
UCTION FLOW
INSTR
PC
Instruction
fetched
Instruction
executed
FEh
1
PC
Inst (PC)
Inst (PC-1)
FFh 00h 01h 02h
1
PC +1 PC +1 0004h
Inst (PC+1)
Inst (PC)
Read TMR0
reads NT0
Read TMR0
reads NT0
Interrupt Latency
NT0
Read TMR0
reads NT0
(2)
Read TMR0
reads NT0
Inst (0004h) Inst (0005h)
Read TMR0
reads NT0 + 1
0005h
Inst (0004h)Dummy cycle Dummy cycle
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.
The TMR0 register will roll over 3 Tosc cycles later.
DS30430C-page 28 1998 Microchip Technology Inc.
PIC16F8X
6.2 Using TMR0 with External Clock
When an external clock input is used for TMR0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (T
synchronization. Also, there is a delay in the actual
incrementing of the TMR0 register after
synchronization.
6.2.1 EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of pin RA4/T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2Tosc (plus a small RC delay) and low
for at least 2Tosc (plus a small RC delay). Refer to the
electrical specification of the desired device.
When a prescaler is used, the external clock input is
divided by an asynchronous ripple counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4T osc (plus a small RC dela y) divided
by the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the AC Electrical
Specifications of the desired device.
OSC)
6.2.2 TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
Module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
6.3 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 Module, or as a postscaler for the Watchdog
Timer (Figure 6-6). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that there is only one prescaler available which is
mutually exclusive between the Timer0 Module and the
Watchdog Timer. Thus, a prescaler assignment for the
Timer0 Module means that there is no prescaler for the
Watchdog Timer , and vice-versa.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 Module, all instructions
writing to the Timer0 Module (e.g., CLRF 1, MOVWF 1,
BSF 1,x ....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
1998 Microchip Technology Inc. DS30430C-page 29
PIC16F8X
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Note 1:
Ext. Clock Input or
Prescaler Out (Note 2)
Ext. Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4)
Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on TMR0 input = ± 4Tosc max.
2:
External clock if no prescaler selected, Prescaler output otherwise.
3:
The arrows ↑ indicate where sampling occurs. A small clock pulse may be missed by sampling.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TMR0
T0 T0 + 1 T0 + 2
FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER
CLKOUT (= Fosc/4)
RA4/T0CKI
pin
T0SE
0
1
M
U
X
T0CS
1
M
U
0
X
PSA
SYNC
2
Cycles
(Note 3)
Data Bus
8
TMR0 register
Set bit T0IF
on overflow
0
M
U
1
Watchdog
Timer
WDT Enable bit
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION_REG register.
DS30430C-page 30 1998 Microchip Technology Inc.
X
PSA
8-bit Prescaler
8
8 - to - 1MUX
0
M U X
WDT
time-out
PS2:PS0
1
PSA
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