MICROCHIP PIC16F87, PIC16F88 Technical data
PIC16F87/88
Data Sheet
18/20/28-Pin Enhanced Flash
Microcontrollers with
nanoWatt Technology
2005 Microchip Technology Inc. DS30487C
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The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
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© 2005, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS30487C-page ii 2005 Microchip Technology Inc.
PIC16F87/88
18/20/28-Pin Enhanced Fl ash MCUs with nanoWatt Technology
Low-Power Features:
• Power-Managed modes:
- Primary Run: RC oscillator, 76 µA, 1 MHz, 2V
- RC_RUN: 7 µA, 31.25 kHz, 2V
- SEC_RUN: 9 µA, 32 kHz, 2V
- Sleep: 0.1 µA, 2V
• Timer1 Oscillator: 1.8 µA, 32 kHz, 2V
• Watchdog Timer: 2.2 µA, 2V
• Two-Speed Oscillator Start-u p
Oscillators:
• Three Crystal modes:
- LP, XT, HS: up to 20 MHz
• Two External RC modes
• One External Clock mode:
- ECIO: up to 20 MHz
• Internal oscillator block:
- 8 user selectable frequencies: 31 kHz,
125 kHz, 250 kHz, 500 kHz, 1 M Hz, 2 MHz,
4MHz, 8MHz
Peripheral Features:
• Capture, Compare, PWM (CCP) module:
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 10-bit, 7-channel Analog-to-Digital Converter
• Synchronous Serial Port (SSP) with SPI™
(Master/Slave) and I
• Addressable Universal Synchronous
Asynchronous Receiver Transmitter
(AUSART/SCI) with 9-bit address detection:
- RS-232 operation using internal oscillator
(no extern al crystal required)
• Dual Analog Comparator module:
- Programmable on-chip voltage reference
- Programmable input mu ltiplexing f rom device
inputs and internal voltage reference
- Comparator outputs are externally accessible
2
C™ (Slave)
Pin Diagram
18-Pin PDIP, SOIC
RA2/AN2/CV
RA3/AN3/VREF+/
RA4/AN4/T0CKI/
RA5/MCLR
RB0/INT/CCP1
RB1/SDI/SDA
RB2/SDO/RX/DT
RB3/PGM/CCP1
Note 1: The CCP1 pin is determined by the CCPMX bit in
REF/
V
REF-
C1OUT
C2OUT
/VPP
VSS
(1)
(1)
Configuration Word 1 register.
1
18
2
17
3
16
4
15
5
14
6
13
PIC16F88
7
12
8
11
9
10
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
DD
V
RB7/AN6/PGD/
T1OSI
RB6/AN5/PGC/
T1OSO/T1CKI
RB5/SS
/TX/CK
RB4/SCK/SCL
Special Microcontroller Features:
• 100,000 erase/write cycles Enhanced Flash
program memory typical
• 1,000,000 typical erase/write cycles EEPROM
data memory typical
• EEPROM Data Retention: > 40 years
• In-Circuit Serial Programming™ (ICSP™)
via two pins
• Processor read/write access to program memory
• Low-Voltage Progr amming
• In-Circuit Debugging via two pins
• Extended Watchdog Timer (WDT):
- Programmable period from 1ms to 268s
• Wide operating voltage range: 2.0V to 5.5V
Program Memory Data Memory
Device
PIC16F87 7168 4096 368 256 16 N/A 1 Y 2 Y 2/1
PIC16F88 7168 4096 368 256 16 1 1 Y 2 Y 2/1
2005 Microchip Technology Inc. DS30487C-page 1
Flash
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes)
I/O
Pins
10-bit
A/D (ch)
CCP
(PWM)
AUSART Comparators SSP
Timers
8/16-bit
PIC16F87/88
Pin Diagrams
18-Pin PDIP, SOIC
RA2/AN2/CVREF
RA3/AN3/C1OUT
RA4/T0CKI/C2OUT
RA5/MCLR
RB0/INT/CCP1
RB1/SDI/SDA
RB2/SDO/RX/DT
RB3/PGM/CCP1
20-Pin SSOP
RA2/AN2/CVREF
RA3/AN3/C1OUT
RA4/T0CKI/C2OUT
RA5/MCLR
RB0/INT/CCP1
RB1/SDI/SDA
RB2/SDO/RX/DT
RB3/PGM/CCP1
18-Pin PDIP, SOIC
RA2/AN2/CVREF/VREF-
RA3/AN3/V
RA4/AN4/T0CKI/C2OUT
REF+/C1OUT
RA5/MCLR
RB0/INT/CCP1
RB1/SDI/SDA
RB2/SDO/RX/DT
RB3/PGM/CCP1
/VPP
VSS
/VPP
VSS
/VPP
VSS
1
2
3
4
(1)
(1)
5
6
7
8
9
1
2
3
4
5
6
(1)
7
8
9
(1)
10
1
2
3
4
(1)
(1)
5
6
7
8
9
PIC16F87
PIC16F87
PIC16F88
18
17
16
15
14
13
12
11
10
20
19
18
17
16
15
14
13
12
11
18
17
16
15
14
13
12
11
10
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
DD
V
RB7/PGD/T1OSI
RB6/PGC/T1OSO/T1CKI
/TX/CK
RB5/SS
RB4/SCK/SCL
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
V
DD
VDDVSS
RB7/PGD/T1OSI
RB6/PGC/T1OSO/T1CKI
RB5/SS/TX/CK
RB4/SCK/SCL
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
V
DD
RB7/AN6/PGD/T1OSI
RB6/AN5/PGC/T1OSO/T1CKI
RB5/SS
/TX/CK
RB4/SCK/SCL
20-Pin SSOP
RA2/AN2/CVREF/VREFRA3/AN3/V
RA4/AN4/T0CKI/C2OUT
REF+/C1OUT
RA5/MCLR
RB0/INT/CCP1
RB2/SDO/RX/DT
1/VPP
VSS
RB1/SDI/SDA
1
2
3
4
5
6
(1)
7
8
9
(1)
10
20
19
18
17
16
15
14
PIC16F88
13
12
11
Note 1: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.
DS30487C-page 2 2005 Microchip Technology Inc.
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
V
DD
VDDVSS
RB7/AN6/PGD/T1OSI
RB6/AN5/PGC/T1OSO/T1CKI
RB5/SS/TX/CK
RB4/SCK/SCLRB3/PGM/CCP1
Pin Diagrams (Cont’d)
28-Pin QFN
PIC16F87/88
RA5/MCLR/VPP
RB0/INT/CCP1
28-Pin QFN
NC
VSS
NC
V
NC
RA2/AN2/CVREF
(1)
RB3/PGM/CCP1
11
NC
NC
25
RA1/AN1
24
12
RB4/SCK/SCL
RA0/AN0
23
13
RB5/SS/TX/CK
14
NC
NC
22
21
20
19
18
17
16
15
RA7/OSC1/CLKI
RA6/OSC2/CLKO
V
DD
NC
V
DD
RB7/PGD/T1OSI
RB6/PGC/T1OSO/T1CKI
RA4/T0CKI/C2OUT
RA3/AN3/C1OUT
282627
1
2
3
PIC16F87
4
SS
(1)
5
6
7
8109
RB1/SDI/SDA
RB2/SDO/RX/DT
REF+/C1OUT
RA5/MCLR/VPP
RB0/INT/CCP1
NC
VSS
NC
V
NC
RA4/AN4/T0CKI/C2OUT
RA3/AN3/V
282627
1
2
3
PIC16F88
4
SS
(1)
5
6
7
8109
RB1/SDI/SDA
RB2/SDO/RX/DT
RA2/AN2/CVREF/VREF-
(1)
RB3/PGM/CCP1
NC
25
11
NC
RA1/AN1
24
12
RB4/SCK/SCL
RA0/AN0
23
13
RB5/SS/TX/CK
14
NC
NC
22
21
20
19
18
17
16
15
RA7/OSC1/CLKI
RA6/OSC2/CLKO
DD
V
NC
V
DD
RB7/AN6/PGD/T1OSI
RB6/AN5/PGC/T1OSO/T1CKI
Note 1: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.
2005 Microchip Technology Inc. DS30487C-page 3
PIC16F87/88
Table of Contents
1.0 Device Overview..........................................................................................................................................................................5
2.0 Memory Organization.................................................................................................................................................................11
3.0 Data EEPROM and Flash Program Memory.............................................................................................................................. 27
4.0 Oscillator Configurations............................................................................................................................................................ 35
5.0 I/O Ports............................ ..................... ..................... ..................... .......................................................................................... 51
6.0 Timer0 Module ........................................................................................................................................................................... 67
7.0 Timer1 Module ........................................................................................................................................................................... 71
8.0 Timer2 Module ........................................................................................................................................................................... 79
9.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 81
10.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 87
11.0 Addressable Universal Synchronous Asynchronous Receiv er Transmitter (AUS ART ) ............................................................. 97
12.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................ 113
13.0 Comparator Module...................................................................................... ......... .... .. .... .........................................................121
14.0 Comparator Voltage Reference Module................................................... .. ....... .... .. .... .. .... ....... .. .............................................. 127
15.0 Special Features of the CPU........................................................ ..................... ....................................................................... 129
16.0 Instruction Set Summary..........................................................................................................................................................149
17.0 Development Support. .............................................................................................................................................................. 157
18.0 Electrical Characteristics..........................................................................................................................................................163
19.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 193
20.0 Packaging Information.......................... ..................... ..................... .......................................................................................... 207
Appendix A: Revision History.............................................................................................................................................................213
Appendix B: Device Differences.........................................................................................................................................................213
Index .................................................................................................................................................................................................. 215
The Microchip Web Site....................................... ............................................................. ................................................................. 223
Customer Change Notification Service ..............................................................................................................................................223
Customer Support.............................................................................................................................................................................. 223
Reader Response.............................................................................................................................................................................. 224
PIC16F87/88 Product Identification System ......................................................................................................................................225
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DS30487C-page 4 2005 Microchip Technology Inc.
PIC16F87/88
1.0 DEVICE OVERVIEW
This document contains device specific information for
the operation of the PIC16F87/88 devices. Additional
information may be found in the “PICmicro® Mid-Range
MCU Family Reference Manual” (DS33023) which may
be downloaded from the Microchip web site. This
Reference Manual should be considered a complementary document to this data sheet and is highly
recommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
The PIC16F87/88 belongs to the Mid-Range family of
the PICmicro
are shown in Figure1-1 and Figure 1-2. These devices
contain features that are new to the PIC16 prod uct line:
• Low-power modes: RC_RUN allows the core and
peripherals to be clocked from the INTRC, while
SEC_RUN allows the core and peripherals to be
clocked from the low-power Timer1. Refer to
Section 4.7 “Power-Managed Modes” for
further details.
• Internal RC oscillator with eight selectable
frequencies, including 31.25 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz and
8 MHz. The INTRC can be configured as a
primary or secondary clock source. Refer to
Section 4.5 “Internal Oscillator Block” for
further details.
• The Timer1 module current consumption has
been greatly reduced from 20 µA (previous PIC16
devices) to 1.8µA typical (32 kHz at 2V), which is
ideal for real-time clock applications. Refer to
Section 7.0 “Timer1 Module” for further details.
• Extended W atchdog T imer (WD T) that can hav e a
programmable period from 1 ms to 268s. The
WDT has its own 16-bit prescaler. Refer to
Section 15.12 “Watchdog Timer (WDT)” for
further details.
• Two-Speed Start-up: When the oscillator is
configured for LP, XT or HS Oscillator mode, this
feature will cl ock t he dev ice f rom the INTRC whil e
the oscillator is warming up. This, in turn, will
enable almost immediate code execution. Refer
to Section 15.12.3 “Two-Speed Cl ock Start-up
Mode” for further details.
• Fail-Safe Clock Monitor: This feature will allow the
device to continue operation if the primary or
secondary clock source fails by switching over to
the INTRC.
• The A/D module has a new register for PIC16
devices named ANSEL. This register allows
easier configuration of analog or digital I/O pins.
®
devices. Block diagrams of the devices
TABLE 1-1: AVAILABLE MEMORY IN
PIC16F87/88 DEVICES
2
Program
Flash
C™
Device
PIC16F87/88 4K x 14 368 x 8 256 x 8
There are 16 I/O pins that are user configurable on a
pin-to-pin basis. Some pins are multiplexed with other
device functions. These functions include:
• External Interrupt
• Change on PORTB Interrupt
• Timer0 Clock Input
• Low-Power Timer1 Clock/Oscillator
• Capture/Compare/PWM
• 10-bit, 7-channel A/D Converter (PI C16F88 onl y)
• SPI™/I
• Two Analog Comparators
• AUSART
•MCLR
Table 1-2 details the pinout of the devices with
descriptions and details for each pin.
(RA5) can be configured as an input
Data
Memory
Data
EEPROM
2005 Microchip Technology Inc. DS30487C-page 5
PIC16F87/88
FIGURE 1-1: PIC16F87 DEVICE BLOCK DIAGRAM
Program
Bus
OSC1/CLKI
OSC2/CLKO
Flash
Program
Memory
4K x 14
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
Direct Addr
8
Start-up Timer
Watchdog
Brown-out
8 Level Stack
(13-bit)
Power-up
Timer
Oscillator
Power-on
Reset
Timer
Reset
RAM Addr
7
3
8
Data Bus
RAM
File
Registers
368 x 8
(1)
Addr MUX
FSR reg
STATUS reg
ALU
W reg
9
8
MUX
8
Indirect
Addr
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/CVREF
RA3/AN3/C1OUT
RA4/T0CKI/C2OUT
RA5/MCLR/VPP
RA6/OSC2/CLKO
RA7/OSC1/CLKI
RB0/INT/CCP1
RB1/SDI/SDA
RB2/SDO/RX/DT
RB3/PGM/CCP1
RB4/SCK/SCL
RB5/SS/TX/CK
RB6/PGC/T1OSO/T1CKI
RB7/PGD/T1OSI
(2)
(2)
VDD, VSS
Timer0
Data EE
256 Bytes
SSP
Comparators
Timer2
AUSART
RA5/MCLR
Timer1
CCP1
Note 1: Higher order bits are from the STATUS register.
2: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.
DS30487C-page 6 2005 Microchip Technology Inc.
FIGURE 1-2: PIC16F88 DEVICE BLOCK DIAGRAM
PIC16F87/88
Program
Bus
OSC1/CLKI
OSC2/CLKO
Flash
Program
Memory
4K x 14
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
8
Power-up
Start-up Timer
Power-on
Watchdog
Brown-out
(13-bit)
Timer
Oscillator
Reset
Timer
Reset
RAM Addr
7
3
8
Data Bus
RAM
File
Registers
368 x 8
(1)
Addr MUX
FSR reg
STATUS reg
ALU
W reg
9
8
MUX
8
Indirect
Addr
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/CVREF/VREFRA3/AN3/VREF+/C1OUT
RA4/AN4/T0CKI/C2OUT
RA5/MCLR/VPP
RA6/OSC2/CLKO
RA7/OSC1/CLKI
RB0/INT/CCP1
RB1/SDI/SDA
RB2/SDO/RX/DT
RB3/PGM/CCP1
RB4/SCK/SCL
RB5/SS/TX/CK
RB6/AN5/PGC/T1OSO/T1CKI
RB7/AN6/PGD/T1OSI
(2)
(2)
VDD, VSS
Timer0
Data EE
256 Bytes
10-bit A/D
Comparators
Timer2
AUSART
RA5/MCLR
Timer1
CCP1
Note 1: Higher order bits are from the STATUS register.
2: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.
SSP
2005 Microchip Technology Inc. DS30487C-page 7
PIC16F87/88
TABLE 1-2: PIC16F87/88 PINOUT DESCRIPTION
PDIP/
Pin Name
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/CV
RA2
AN2
CV
VREF-
RA3/AN3/V
RA3
AN3
V
C1OUT
RA4/AN4/T0CKI/C2OUT
RA4
AN4
T0CKI
C2OUT
RA5/MCLR
RA5
MCLR
VPP
RA6/OSC2/CLKO
RA6
OSC2
CLKO
RA7/OSC1/CLKI
RA7
OSC1
CLKI
Legend: I = Input O = Output I/O = Input/Output P = Power
Note 1: T his buffer is a Schmitt Trigger input when configured as the external interrupt.
REF/VREF-
REF
(4)
REF+/C1OUT
(4)
REF+
(4)
/VPP
– = Not used TTL = TTL Input ST = Schmitt Trigger Input
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
4: PIC 16F88 devices only.
5: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.
SSOP
SOIC
Pin#
17 19 23
18 20 24
1126
2227
3328
441
15 17 20
16 18 21
Pin#
QFN
Pin#
I/O/P
Type
I/O
I
I/O
I
I/O
I
O
I
I/O
I
I
O
I/O
I
I
O
I
I
P
I/O
O
O
I/O
I
I
Buffer
Type
TTL
Analog
TTL
Analog
TTL
Analog
Analog
TTL
Analog
Analog
ST
Analog
ST
ST
ST
–
ST
–
–
ST
ST/CMOS
–
Description
PORTA is a bidirectional I/O port.
Bidirectional I/O pin.
Analog input channel 0.
Bidirectional I/O pin.
Analog input channel 1.
Bidirectional I/O pin.
Analog input channel 2.
Comparator V
A/D reference voltage (Low) input.
Bidirectional I/O pin.
Analog input channel 3.
A/D reference voltage (High) input.
Comparator 1 output.
Bidirectional I/O pin.
Analog input channel 4.
Clock input to the TMR0 timer/counter.
Comparator 2 output.
Input pin.
Master Clear (Reset). Input/programming voltage
input. This pin is an active-low Reset to the device.
Programming voltage input.
Bidirectional I/O pin.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, this pin outputs CLKO signal which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
Bidirectional I/O pin.
(3)
Oscillator crystal input.
External clock source input.
REF output.
DS30487C-page 8 2005 Microchip Technology Inc.
PIC16F87/88
TABLE 1-2: PIC16F87/88 PINOUT DESCRIPTION (CONTINUED)
PDIP/
Pin Name
RB0/INT/CCP1
(5)
SSOP
SOIC
Pin#
Pin#
677
RB0
INT
CCP1
RB1/SDI/SDA
788
RB1
SDI
SDA
RB2/SDO/RX/DT
899
RB2
SDO
RX
DT
RB3/PGM/CCP1
(5)
91010
RB3
PGM
CCP1
RB4/SCK/SCL
10 11 12
RB4
SCK
SCL
RB5/SS
/TX/CK
11 12 13
RB5
SS
TX
CK
RB6/AN5/PGC/T1OSO/
12 13 15
T1CKI
RB6
(4)
AN5
PGC
T1OSO
T1CKI
RB7/AN6/PGD/T1OSI
RB7
(4)
AN6
13 14 16
PGD
T1OSI
SS 5 5, 6 3, 5 P – Ground reference for logic and I/O pins.
V
V
DD 14 15, 16 17, 19 P – Positive supply for logic and I/O pins.
Legend: I = Input O = Output I/O = Input/Output P = Power
– = Not used TTL = TTL Input ST = Schmitt Trigger Input
Note 1: T his buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
4: PIC16F88 devices only.
5: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.
QFN
Pin#
I/O/P
Type
I/O
I
I/O
I/O
I
I/O
I/O
O
I
I/O
I/O
I/O
I
I/O
I/O
I
I/O
I
O
I/O
I/O
I
I/O
O
I
I/O
I
I
I
Buffer
Type
TTL
(1)
ST
ST
TTL
ST
ST
TTL
ST
TTL
ST
ST
TTL
ST
ST
TTL
TTL
TTL
(2)
ST
ST
ST
TTL
(2)
ST
ST
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
Bidirectional I/O pin.
External interrupt pin.
Capture input, Compare output, PWM output.
Bidirectional I/O pin.
SPI™ data in.
2
C™ data.
I
Bidirectional I/O pin.
SPI data out.
AUSART asynchronous receive.
AUSART synchronous detect.
Bidirectional I/O pin.
Low-Voltage ICSP™ Programming enable pin.
Capture input, Compare output, PWM output.
Bidirectional I/O pin. Interrupt-on-change pin.
Synchronous serial clock input/output for SPI.
Synchronous serial clock Input for I
Bidirectional I/O pin. Interrupt-on-change pin.
Slave select for SPI in Slave mode.
AUSART asynchronous transmit.
AUSART synchronous clock.
Bidirectional I/O pin. Interrupt-on-change pin.
Analog input channel 5.
In-Circuit Debugger and programming clock pin.
Timer1 oscillator output.
Timer1 external clock input.
Bidirectional I/O pin. Interrupt-on-change pin.
Analog input channel 6.
In-Circuit Debugger and ICSP programming data pin.
Timer1 oscillator input.
2
C.
2005 Microchip Technology Inc. DS30487C-page 9
PIC16F87/88
NOTES:
DS30487C-page 10 2005 Microchip Technology Inc.
PIC16F87/88
2.0 MEMORY ORGANIZATION
There are two memory blocks in the PIC16F87/88
devices. Thes e are t he p rog ram m emo ry an d the d ata
memory . Each bloc k has its o wn bus, so ac cess to each
block can occur during the same oscillator cycle.
The data memory can be further broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data EEPROM
memory. This memory is not directly mapped into the
data memory but is indirectly mapped. That is, an indirect address pointer specifies the address of the data
EEPROM memory to read/write. The PIC16F87/88
device’s 256 bytes of data EEPROM memory have the
address range of 00h-FFh. More details on the
EEPROM memory can be found in Section 3.0 “Data
EEPROM and Flash Program Memory”.
Additional informa tion on devi ce memory may be found
in the “PICmicro
Manual” (DS33023).
2.1 Program Memory Organization
The PIC16F87/88 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. For the PIC16F87/88, the first 4K x 14
(0000h-0FFFh) is physically implemented (see
Figure 2-1). Accessing a location above the physically
implemented address will cause a wraparound. For
example, the same instruction will be accessed at
locations 020h, 420h, 820h, C20h, 1020h, 1420h,
1820h and 1C20h.
The Reset vector is at 0000h an d the interrupt ve ctor is
at 0004h.
®
Mid-Range MCU Family Reference
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK: PIC16F87/88
PC<12:0>
On-Chip
Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stac k Lev el 2
Stac k Lev el 8
Reset Vector
Interrupt V ec tor
Page 0
Page 1
Wraps to
0000h-03FFh
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
2.2 Data Memory Organization
The data memory is pa rtit ioned into m ultipl e ban ks th at
contain the Ge neral Purpose Reg isters and the Special
Function Registers. Bits RP1 (STATUS<6>) and RP0
(STATUS<5>) are the bank select bits.
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Abo ve the Speci al Function Re gisters are General Purpose Registers, implemented as
static RAM. All implemented banks contain SFRs.
Some “high use” SFRs from one bank may be mirrored
in another bank for code reduction and quicker access
(e.g., the STATUS register is in Banks 0-3).
Note: EEPROM data memory description can be
found in Section 3.0 “Data EEPROM and
Flash Program Memory” of this data
sheet.
2005 Microchip Technology Inc. DS30487C-page 11
PIC16F87/88
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or
indirectly, through the File Select Register (FSR).
FIGURE 2-2: PIC16F87 REGISTER FILE MAP
Address
(*)
File
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
EFh
F0h
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
General
Purpose
Register
96 Bytes
Address
(*)
File
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PIE2
PCON
OSCCON
OSCTUNE
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
CMCON
CVRCON
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
File
Address
Indirect addr.
TMR0 OPTION_REG
PCL
STATUS
FSR
WDTCON
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
General
Purpose
Register
16 Bytes
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
11Fh
120h
16Fh
170h
Indirect addr.
STATUS
STATUS
PCLATH
INTCON
EECON1
EECON2
Reserved
Reserved
General
Purpose
Register
16 Bytes
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
PCL
FSR
TRISB
(*)
(1)
(1)
File
Address
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
19Fh
1A0h
1EFh
1F0h
Bank 0
7Fh
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: This register is reserved, maintain this register clear.
DS30487C-page 12 2005 Microchip Technology Inc.
Bank 1
FFh
Bank 2
17Fh 1FFh
Bank 3
FIGURE 2-3: PIC16F88 REGISTER FILE MAP
File
Address
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
ADRESH
ADCON0 ADCON1
General
Purpose
Register
96 Bytes
Bank 0
(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
Indirect addr.
OPTION_REG
STATUS
TRISA
TRISB
PCLATH
INTCON
PCON
OSCCON
OSCTUNE
SSPADD
SSPSTAT
TXSTA
SPBRG
ANSEL
CMCON
CVRCON
ADRESL
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
Bank 1
PCL
FSR
PIE1
PIE2
PR2
File
Address
(*)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
EFh
F0h
FFh
Indirect addr.
TMR0
PCL
STATUS
FSR
WDTCON
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
General
Purpose
Register
16 Bytes
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
Bank 2
File
Address
(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
11Fh
120h
16Fh
170h
17Fh
PIC16F87/88
File
Address
(1)
(1)
(*)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
19Fh
1A0h
1EFh
1F0h
1FFh
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved
Reserved
General
Purpose
Register
16 Bytes
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
Bank 3
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: This register is reserved, maintain this register clear.
2005 Microchip Technology Inc. DS30487C-page 13
PIC16F87/88
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Addre ss Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
(2)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 26, 1 35
TMR0 Timer0 Module Register xxxx xxxx 69
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000
(2)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 17
(2)
FSR Indirect Data Memory Address Poi nter xxxx xxxx 135
PORTA PORTA Data Latch when written; PORTA pins when read (PIC16F87)
PORTB PORTB Data Latch when written; PORTB pins when read (PIC16F87)
— Unimplemented — —
— Unimplemented — —
(1,2)
(2)
— Unimplemented — —
PCLATH — — — Write Buffer for the Upper 5 bits of the Program Counter ---0 0000 135
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 19, 69,
PIR1 —ADIF
PIR2 OSFIF CMIF — EEIF — — — — 00-0 ---- 23, 34
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 77, 83
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 77, 83
T1CON — T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 72, 83
TMR2 Timer2 Module Register 0000 0000 80, 85
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 80, 85
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 90, 95
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 89, 95
CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 83, 85
CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 83, 85
CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 81, 83
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 98, 99
TXREG AUSART Transmit Data Register 0000 0000 103
RCREG AUSART Receive Data Register 0000 0000 105
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
ADRESH
ADCON0
PORTA Data Latch when written; PORTA pins when read (PIC16F88)
PORTB Data Latch when written; PORTB pins when read (PIC16F88)
(4)
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 21, 77
(4)
A/D Result Register High Byte xxxx xxxx 120
(4)
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DO NE —ADON0000 00-0 114, 120
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
4: PIC 16F88 device only.
Value on:
POR, BOR
xxxx 0000
xxx0 0000
xxxx xxxx
00xx xxxx
Details
on
page
52
58
77
DS30487C-page 14 2005 Microchip Technology Inc.
PIC16F87/88
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addre ss Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
(2)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000
(2)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx
(2)
FSR Indirect Data Memory Address Poi nter xxxx xxxx
TRISA TRISA7 TRISA6 TRISA5
TRISB PORTB Data Direction Register 1111 1111 58, 85
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
(1,2)
PCLATH — — — Write Buffer for the Upper 5 bits of the Program Counter ---0 0000
(2)
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
ADIE
(4)
PIE1
PIE2 OSFIE CMIE —EEIE — — — — 00-0 ---- 22, 34
PCON — — — — — —PORBOR ---- --0q
OSCCON — IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 -000 0000 40
OSCTUNE — — TUN5 T UN4 TUN3 TUN2 TUN1 TUN0 --00 0000 38
— Unimplemented —
PR2 Timer2 Period Register 1111 1111 80, 85
SSPADD Synchronous Serial Port (I2C™ mode) Address Register 0000 0000
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000
— Unimplemented
— Unimplemented
— Unimplemented
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 97, 99
SPBRG Baud Rate Generator Register 0000 0000 99, 103
— Unimplemented
(4)
ANSEL
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 121,
CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 126, 128
(4)
ADRESL
(4)
ADCON1
—
— ANS6 ANS5 ANS4 A NS3 ANS2 ANS1 ANS0 -111 1111
A/D Result Register Low Byte xxxx xxxx
ADFM ADCS2 VCFG1 VCFG0 — — — — 0000 ----
(3)
PORTA Data Direction Register (TRISA<4:0>) 1111 1111
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
4: PIC16F88 device only.
Value on:
POR, BOR
— —
— —
— —
— —
Details
on
page
26, 135
18, 69
135
17
135
52, 126
135
19, 69,
77
20, 80
24
—
95
88, 95
120
126, 128
120
52, 115,
120
2005 Microchip Technology Inc. DS30487C-page 15
PIC16F87/88
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addre ss Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 2
(2)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
Bank 3
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh — Reserved, maintain clear
18Fh — Reserved, maintain clear
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
TMR0 Timer0 Module Register xxxx xxxx 69
(2)
PCL Program Counter’s (PC) Least Significant Byte 0000 0000
(2)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx
(2)
FSR Indirect Data Memory Address Poi nter xxxx xxxx
WDTCON
PORTB PORTB Data Latch when written; PORTB pins when read (PIC16F87)
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
(1,2)
PCLATH — — — Write Buffer for the Upper 5 bits of the Program Counter ---0 0000
(2)
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
EEDATA EEPROM/Flash Data Register Low Byte xxxx xxxx 34
EEADR EEPROM/Flash Address Register Low Byte xxxx xxxx 34
EEDATH — — EEPROM/Flash Data Register High Byte --xx xxxx 34
EEADRH — — — — EEPROM/Flash Address Regi st er Hi gh Byte ---- xxxx
(2)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 18, 69
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000
(2)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx
(2)
FSR Indirect Data Memory Address Poi nter xxxx xxxx
— Unimplemented — —
TRISB PORTB Data Direction Register 1111 1111 58, 83
— Unimplemented — —
— Unimplemented — —
— Unimplemented — —
(1,2)
PCLATH — — — Write Buffer for the Upper 5 bits of the Program Counter ---0 0000
(2)
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
EECON1 EEPGD — — FREE WRERR WREN WR RD x--x x000 28, 34
EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 34
— — —
PORTB Data Latch when written; PORTB pins when read (PIC16F88)
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 142
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
4: PIC 16F88 device only.
Value on:
POR, BOR
xxxx xxxx
00xx xxxx
0000 0000 —
0000 0000 —
Details
on
page
26, 135
135
17
135
58
135
19, 69,
77
34
135
135
17
135
135
19, 69,
77
DS30487C-page 16 2005 Microchip Technology Inc.
PIC16F87/88
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains
the arithmetic status of the ALU, the Reset status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destinatio n may be different than
intended.
and PD bits are not
For example, CLRF STATUS will clear the up per three
bits and set t he Z bit. T his leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF
and MOVWF instructions are used to alter the STATUS
register because these instructions do not affect the Z, C
or DC bits from the STATUS register. For other
instructions not affecting any Status bits, see
Section 16.0 “Instruction Set Summary”.
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STA TUS: ARITHMETIC STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 bytes.
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)
bit 0 C: Carry/borrow
: Tim e- out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
1 = A carry-ou t from the 4 th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
PD ZDCC
(1)
(1,2)
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand.
2: For rotate (RRF, RLF) instructions, this bit is loaded w ith eit her the hi gh or low- order
bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2005 Microchip Technology Inc. DS30487C-page 17
PIC16F87/88
2.2.2.2 OPTION_REG Register
The OPTION_REG register is a readable and writable
register that contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external
INT interrupt, TMR0 and the weak pull-u ps o n POR TB.
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer. Although the prescaler can be assigne d to either the WDT or
Timer0, bu t not both, a new div ide co unter
is implemented in the WDT circuit to give
multiple WDT time-out selections. This
allows TMR0 and WDT to each have their
own scaler. Refer to Section 15.12
“Watchdog Timer (WDT)” for further
details.
REGISTER 2-2: OPTION_REG: OPTION CONTROL REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU
bit 7 bit 0
bit 7 RBPU
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI/C2OUT pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI/C2OUT pin
0 = Increment on low-to-high transition on RA4/T0CKI/C2OUT pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
INTEDG T0CS T0SE PSA PS2 PS1 PS0
: PORTB Pull-up Enable bit
Bit Value TMR0 Rate WDT Rate
000 1 : 2 1 : 1
001 1 : 4 1 : 2
010 1 : 8 1 : 4
011 1 : 16 1 : 8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS30487C-page 18 2005 Microchip Technology Inc.
PIC16F87/88
2.2.2.3 INTCON Register
The INTCON register is a readable and writable register that contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
Note: Interrupt flag bits get set when an interrupt
condition occurs, regar dless of the st ate of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INT0IE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
A mismatch conditi on will c ontinue t o set fla g bit RBI F. Reading PORTB will end the mismatc h
condition and allow flag bit RBIF to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2005 Microchip Technology Inc. DS30487C-page 19
PIC16F87/88
2.2.2.4 PIE1 Register
This register contains the individual enable bits for the
peripheral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enabled
0 = Disabled
Note 1: This bit is only implemente d on the PIC16F 88. The bit will read ‘0’ on the PIC16F87.
bit 5 RCIE: AUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TXIE: AUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
(1)
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS30487C-page 20 2005 Microchip Technology Inc.
PIC16F87/88
2.2.2.5 PIR1 Register
This register contains the individual flag bits for the
peripheral interrupts.
Note: Interrupt flag bits are set w hen an in terrupt
condition occurs , regardle ss of the st ate of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)
U-0 R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0
—ADIF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = The A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
Note 1: This bit is only implem ented on the PIC16F8 8. The bit will read ‘0’ on the PIC16F8 7.
bit 5 RCIF: AUSART Receive Interrupt Flag bit
1 = The AUSART receive buffer is full (cleared by reading RCREG)
0 = The AUSART receive buffer is not full
bit 4 TXIF: AUSART Transmit Interrupt Flag bit
1 = The AUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The AUSART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Interrupt Flag bit
1 = A TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
(1)
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2005 Microchip Technology Inc. DS30487C-page 21
PIC16F87/88
2.2.2.6 PIE2 Register
The PIE2 register contains the individual enable bit for
the EEPROM write operation interrupt.
REGISTER 2-6: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0
OSFIE CMIE — EEIE — — — —
bit 7 bit 0
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS30487C-page 22 2005 Microchip Technology Inc.
PIC16F87/88
2.2.2.7 PIR2 Register
The PIR2 register contains the fla g bit for the EEPROM
write operation interrupt.
.
Note: Interrupt flag bits are set w hen an in terrupt
condition occurs , regardle ss of the st ate of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0
OSFIF CMIF — EEIF — — — —
bit 7 bit 0
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software)
0 = System clock operating
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2005 Microchip Technology Inc. DS30487C-page 23
PIC16F87/88
2.2.2.8 PCON Register
Note: Interrupt flag bits get set when an interrupt
condition occurs , regardle ss of the st ate of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset, an external MCLR Reset
and WDT Reset.
Note: BOR is unknown on Power-on Reset. It
must then be set by the us er an d c hec ke d
on subsequent Resets to see if BOR
clear , indicating a brown-out has occurred.
The BOR status bit is a ‘don’t care’ and is
not necessarily predictable if the brownout circuit is disabled (by clearing the
BOREN bit in the Configuration Word
register).
REGISTER 2-8: PCON: POWER CONTROL REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x
— — — — — —PORBOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as ‘0’
bit 1 POR
bit 0 BOR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
is
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS30487C-page 24 2005 Microchip Technology Inc.
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register which is a readable
PIC16F87/88
2005 Microchip Technology Inc. DS30487C-page 25
PIC16F87/88
2.5 Indirect Addressing, INDF and FSR Registers
The INDF register is not a physi cal register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruc tion using the INDF register actual ly
accesses the register pointed to by the File Sele ct Register, FSR. Reading the INDF register itself, indirectly
(FSR = 0) will read 00h. Writing to the INDF register
indirectly result s in a no op era tion ( alth oug h status bits
may be affected ). An ef fective 9- bit add ress is obt ained
by concatenating the 8 -bit FSR regi ster and the IRP b it
(STATUS<7>), as shown in Figure 2-5.
FIGURE 2-5: DIRECT/INDIRECT ADDRESSING
RP1:RP 0 6
Bank Select Location Select
From Opcode
0
00 01 10 11
00h
80h
100h
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: INDIRECT ADDRESSING
MOVLW 0x20 ;initialize pointer
NEXT CLRF INDF ;clear INDF register
CONTINUE
MOVWF FSR ;to RAM
INCF FSR, F ;inc pointer
BTFSS FSR, 4 ;all done?
GOTO NEXT ;no clear next
: ;yes continue
Indirect AddressingDirect Addressing
IRP FSR Register
Bank Select
180h
7
0
Location Select
Data
(1)
Memory
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: For register file map detail, see Figure 2-2 or Figure 2-3.
FFh
17Fh
1FFh
DS30487C-page 26 2005 Microchip Technology Inc.
PIC16F87/88
3.0 DATA EEPROM AND FLASH PROGRAM MEMORY
The data EEPROM and Flash program memory are
readable and writable during normal operation (over
the full V
in the register file space. Instead, it is indirectly
addressed through the Special Function Registers.
There are six SFRs used to read and write this
memory:
• EECON1
• EECON2
• EEDATA
• EEDATH
• EEADR
• EEADRH
This section focuses on reading and writing data
EEPROM and Flash program memory during normal
operation. Refer to the appropriate device programming specification document for serial programming
information.
When interfacing the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR 0.0677 Tw[(h)12.3(o)-1(ld)12.3w1-1(t)14.3(a)a06772l0 -1.44 cods thad/wi9C.2(8yd EE77 Tw6(h )13.3(EE0-8-651.w3.3(n)0.0101 TFcc)3.5(4nrh)12.)t eo7d.3(eo7)8i1ropo0h
DD range). This memory is not directl y mapped
2005 Microchip Technology Inc. DS30487C-page 27
PIC16F87/88
REGISTER 3-1: EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch)
R/W-x U-0 U-0 R/W-x R/W-x R/W-0 R/S-0 R/S-0
EEPGD — — FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
bit 6-5 Unimplemented: Read as ‘0’
bit 4 FREE: EEPROM Forced Row Erase bit
1 = Erase the program memory row a ddressed by EEADRH:EEADR on th e next WR command
0 = Perform write only
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR
operation)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1 WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read, RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0 = Does not initiate an EEPROM read
or any WDT Reset during normal
Legend:
R = Readable bi t W = Writable bit U = Un implemented bit, read as ‘0 ’ S = Set only
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS30487C-page 28 2005 Microchip Technology Inc.
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