MICROCHIP PIC16F87XA Technical data
PIC16F87XA
Data Sheet
28/40/44-Pin Enhanced Flash
Microcontrollers
2003 Microchip Technology Inc. DS39582B
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, MPLAB, PIC, PICmic ro, PI C START,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartT el and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorpora ted in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of develop m ent
systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS39582B-page ii 2003 Microchip Technology Inc.
PIC16F87XA
28/40/44-Pin Enhanced Flash Microcontrollers
Devices Included in this Data Sheet:
• PIC16F873A
• PIC16F874A
•PIC16F876A
•PIC16F877A
High-Performance RISC CPU:
• Only 35 single-word instructions to learn
• All single- cycle instru ctions except for program
branches, which are two-cycle
• Operating speed: DC – 20 MHz clock input
DC – 200 ns instruction cycle
• Up to 8K x 14 words of Flash Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM),
Up to 256 x 8 bytes of EEPROM Data Memory
• Pinout compatible to other 28-pin or 40/44-pin
PIC16CXXX and PIC16FXXX microcontrollers
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during Sleep via extern al
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM module s
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Synchronous Serial Port (SSP) with SPI™
(Master mode) and I
• Universal Synchronous Asynchronous Receiver
Transmitter (US AR T/SCI) with 9-bi t addre ss
detection
• Parallel Slave Port (PSP) – 8 bits wide with
external RD, WR and CS co ntro ls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
2
C™ (Master/Slave)
Analog Features:
• 10-bit, up to 8-channel Analog-to-Digital
Converter (A/D)
• Brown-out Reset (BOR)
• Analog Comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
REF) module
(V
- Programmable input mu ltiplexing fr om device
inputs and internal voltage reference
- Comparator outputs are externally accessible
Special Microcontroller Features:
• 100,000 erase/write cycl e Enhan ced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Data EEPROM Retention > 40 years
• Self-reprogrammable under software control
• In-Circuit Serial Programming™ (ICSP™)
via two pins
• Single-supply 5V In-Circuit Serial Programming
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving Sleep mode
• Selectable oscil la tor opti ons
• In-Circuit Debug (ICD) via two pins
CMOS Technology:
• Low-power, high-speed Flash/EEPROM
technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low-power consumption
Program Memory
Device
PIC16F873A 7.2K 4096 192 128 22 5 2 Yes Yes Yes 2/1 2
PIC16F874A 7.2K 4096 192 128 33 8 2 Yes Yes Yes 2/1 2
PIC16F876A 14.3K 8192 368 256 22 5 2 Yes Yes Yes 2/1 2
PIC16F877A 14.3K 8192 368 256 33 8 2 Yes Yes Yes 2/1 2
2003 Microchip Technology Inc. DS39582B-page 1
Bytes
# Single Word
Instructions
Data
SRAM
(Bytes)
EEPROM
(Bytes)
I/O
10-bit
A/D (ch)
CCP
(PWM)
SPI
MSSP
Master
USART
2
C
I
Timers
8/16-bit
Comparators
PIC16F87XA
Pin Diagrams
28-Pin PDIP, SOIC, SSOP
MCLR/VPP
RA0/AN0
RA2/AN2/V
RA4/T0CKI/C1OUT
RA5/AN4/SS
RC0/T1OSO/T1CKI
RA1/AN1
REF-/CVREF
RA3/AN3/VREF+
OSC1/CLKI
OSC2/CLKO
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
/C2OUT
V
1
2
3
4
5
6
7
SS
8
9
10
11
12
13
14
PIC16F873A/876A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
V
DD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
28-Pin QFN
RA1/AN1
RA0/AN0
RB7/PGD
RB6/PGC
RB5
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
/C2OUT
V
OSC1/CLKI
OSC2/CLKO
MCLR/VPP
26
27
28
1
2
3
PIC16F873A
4
PIC16F876A
SS
5
6
7
10
8
9
25
11
23
24
121314
RB4
22
21
20
19
18
17
16
15
RB3/PGM
RB2
RB1
RB0/INT
V
DD
VSS
RC7/RX/DT
44-Pin QFN
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
SS
V
VDD
VDD
RB0/INT
RB1
RB2
RC6/TX/CK
4443424140
1
2
3
4
5
6
7
8
9
10
11
121314
NC
RB3/PGM
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
39
38
PIC16F874A
PIC16F877A
16
17
181920
15
RB5
RB4
RB6/PGC
RB7/PGD
/VPP
MCLR
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
363435
37
RA1/AN1
RA0/AN0
RC1/T1OSI/CCP2
33
32
31
30
29
28
27
26
25
24
23
22
21
REF+
REF-/CVREF
RA3/AN3/V
RA2/AN2/V
RC5/SDO
RC2/CCP1
RC1/T1OSI/CCP2
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
V
SS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR
/AN6
RE0/RD
/AN5
RA5/AN4/SS
RA4/T0CKI/C1OUT
/C2OUT
RC0/T1OSO/T1CKI
RC4/SDI/SDA
RC3/SCK/SCL
RC6/TX/CK
DS39582B-page 2 2003 Microchip Technology Inc.
Pin Diagrams (Continued)
40-Pin PDIP
MCLR/VPP
RA0/AN0
RA2/AN2/V
RA4/T0CKI/C1OUT
RA5/AN4/SS
RC0/T1OSO/T1CKI
RA1/AN1
REF-/CVREF
RA3/AN3/VREF+
/C2OUT
RE0/RD
RE1/WR
RE2/CS
OSC1/CLKI
OSC2/CLKO
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
/AN5
/AN6
/AN7
V
DD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16F87XA
40
39
38
37
36
35
34
33
32
31
30
29
28
27
PIC16F874A/877A
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
44-Pin PLCC
RA4/T0CKI/C1OUT
RA5/AN4/SS
RE0/RD
RE1/WR
RE2/CS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CK1
/C2OUT
/AN5
/AN6
/AN7
V
DD
VSS
NC
REF-/CVREF
/VPP
RA3/AN3/VREF+
RA1/AN1
RA0/AN0
MCLR
RA2/AN2/V
65432
7
8
9
10
11
PIC16F874A
12
PIC16F877A
13
14
15
16
17
181920212223242526
NC
1
RB7/PGD
44
RB6/PGC
43
RB5
42
RB4
41
27
NC
40
39
38
37
36
35
34
33
32
31
30
29
28
RB3/PGM
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
44-Pin TQFP
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
SS
V
VDD
RB0/INT
RB1
RB2
RB3/PGM
RC6/TX/CK
4443424140
1
2
3
4
5
6
7
8
9
10
11
121314
NC
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
39
PIC16F874A
PIC16F877A
15
16
17
NC
RB5
RB4
RB7/PGD
RB6/PGC
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
38
363435
37
1819202122
/VPP
RA1/AN1
RA0/AN0
MCLR
REF-/CVREF
RA2/AN2/V
NC
33
32
31
30
29
28
27
26
25
24
23
RA3/AN3/VREF+
NC
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
SS
V
VDD
RE2/CS/AN7
/AN6
RE1/WR
/AN5
RE0/RD
RA5/AN4/SS
RA4/T0CKI/C1OUT
/C2OUT
RC2/CCP1
RC1/T1OSI/CCP2
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC5/SDO
RD3/PSP3
RC4/SDI/SDA
NC
RC6/TX/CK
2003 Microchip Technology Inc. DS39582B-page 3
PIC16F87XA
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................ 15
3.0 Data EEPROM and Flash Program Memory............................................................................................................................ 33
4.0 I/O Ports.................................................................................................................................................................................... 41
5.0 Timer0 Module............................................... .. .. ....... .. .. .. .... .. .. ....... .. .. .... .. .. .. ....... .. .. .... .. ............................................................ 53
6.0 Timer1 Module............................................... .. .. ....... .. .. .. .... .. .. ....... .. .. .... .. .. .. ....... .. .. .... .. ............................................................ 57
7.0 Timer2 Module............................................... .. .. ....... .. .. .. .... .. .. ....... .. .. .... .. .. .. ....... .. .. .... .. ............................................................ 61
8.0 Capture/Compare/PWM Modules............................................................................................................................................. 63
9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 71
10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)............................................................ 111
11.0 Analog-to-Digital Converter (A/D) Module .................................................................... .... ......... ............................................. 127
12.0 Comparator Module................................................................................................................................................................ 135
13.0 Comparator Voltage Reference Module ................................................................. .... .. .... ......... ............................................. 141
14.0 Special Features of the CPU.................................................................................................................................................. 143
15.0 Instruction Set Summary.................... ............ ......................... ...................................... .......................................................... 159
16.0 Development Support............................................................. ....... .... .. .... .. ....... .... .. .... .. .... ...................................................... 167
17.0 Electrical Characteristics........................................... .............................................................................................................. 173
18.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 197
19.0 Packaging Information............................................................................................................................................................ 209
Appendix A: Revision History............................................................................................................................................................ 219
Appendix B: Device Differences........................................................................................................................................................ 219
Appendix C:Conversion Considerations........................................................ .... .. ....... .... .. .... .. .... ...................................................... 220
Index ................................................................................................................................................................................................. 221
On-Line Support.................................................................. .. .... .... .. ......... .... .. .... .... ....... .... ................................................................ 229
Systems Information and Upgrade Hot Line..................................................................................................................................... 229
Reader Response............................................................................................................................................................................. 230
PIC16F87XA Product Identification System...................................................................................................................................... 231
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DS39582B-page 4 2003 Microchip Technology Inc.
PIC16F87XA
1.0 DEVICE OVERVIEW
This document contains device specific information
about the following devices:
• PIC16F873A
• PIC16F874A
• PIC16F876A
• PIC16F877A
PIC16F873A/876A devic es are avail able on ly in 28-pi n
packages, while PIC16F874A/877A devices are available in 40-pin and 44-pin packages. All devices in the
PIC16F87XA family share common architecture with
the following differences:
• The PIC16F873A and PIC16F874A h ave one-hal f
of the total on-chip memory of the PIC16F876A
and PIC16F877A
• The 28-pin devices ha ve three I/ O ports , while the
40/44-pin devices have five
• The 28-pin device s have four teen interrupt s, while
the 40/44-pin devices have fifteen
• The 28-pin devices have five A/D input channels,
while the 40/44-pin devices have eight
• The Parallel Slave Port is implemented only on
the 40/44-pin devices
The available features are summarized in Table 1-1.
Block diagrams of the PIC16F873A/876A and
PIC16F874A/877A devices are provided in Figure 1-1
and Figure 1-2, respectively. The pinouts for these
device families are listed in Table 1-2 and Table 1-3.
Additional information may be found in the PICmicro
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The
Reference Manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device
architecture and operation of the peripheral modules.
®
TABLE 1-1: PIC16F87XA DEVICE FEATURES
Key Features PIC16F873A PIC16F874A PIC16F876A PIC16F877A
Operating Frequency DC – 20 MHz DC – 20 MHz DC – 20 MHz DC – 20 MHz
Resets (and Delays) POR, BOR
(PWRT, OST)
Flash Program Memory
(14-bit words)
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory (bytes) 128 128 256 256
Interrupts 14 15 14 15
I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E
Timers 3333
Capture/Compare/PWM modules2222
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Communications — PSP — PSP
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Analog Comparators 2222
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Packages 28-pin PDIP
4K 4K 8K 8K
28-pin SOIC
28-pin SSOP
28-pin QFN
POR, BOR
(PWRT, OST)
40-pin PDIP
44-pin PLCC
44-pin TQ FP
44-pin QFN
POR, BOR
(PWRT, OST)
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
POR, BOR
(PWRT, OST)
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QFN
2003 Microchip Technology Inc. DS39582B-page 5
PIC16F87XA
FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM
Program
Bus
OSC1/CLKI
OSC2/CLKO
Flash
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
Debugger
Low-Voltage
Programming
(13-bit)
RAM Addr
7
Timer
Reset
Timer
Reset
In-Circuit
Data Bus
RAM
File
Registers
(1)
Addr MUX
3
ALU
8
W reg
9
Indirect
8
FSR reg
Status reg
MUX
8
Addr
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
/C2OUT
MCLR
Timer0 Timer1
Data EEPROM
Device Program Flash Data Memory Data EEPROM
PIC16F873A 4K words 192 Bytes 128 Bytes
PIC16F876A 8K words 368 Bytes 256 Bytes
Note 1: Higher order bi ts are from the Status regis ter .
CCP1,2
Timer2
Synchronous
Serial Port
VDD, VSS
10-bit A/D
USART
Comparator
Voltage
Reference
DS39582B-page 6 2003 Microchip Technology Inc.
FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM
Program
Bus
OSC1/CLKI
OSC2/CLKO
Flash
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
8
Power-up
Start-up Timer
Power-on
Watchdog
Brown-out
Debugger
Low-Voltage
Programming
MCLR
(13-bit)
RAM Addr
7
Timer
Oscillator
Reset
Timer
Reset
In-Circuit
VDD, VSS
Data Bus
RAM
File
Registers
(1)
Addr MUX
3
ALU
8
W reg
9
Indirect
8
Addr
FSR reg
Status reg
MUX
PIC16F87XA
8
PORTA
PORTB
PORTC
PORTD
PORTE
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/RD
RE1/WR
RE2/CS
/C2OUT
/AN5
/AN6
/AN7
Timer0 Timer1
Data EEPROM
Device Program Flash Data Memory Data EEPROM
PIC16F874A 4K words 192 Bytes 128 Bytes
PIC16F877A 8K words 368 Bytes 256 Bytes
Note 1: Higher order bits are from the Status register.
CCP1,2
Timer2
Synchronous
Serial Por t
10-bit A/D
USART
Comparator
Parallel
Slave Port
Voltage
Reference
2003 Microchip Technology Inc. DS39582B-page 7
PIC16F87XA
TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION
Pin Name
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO
OSC2
CLKO
/VPP
MCLR
MCLR
VPP
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/V
CV
RA3/AN3/V
RA4/T0CKI/C1OUT
RA5/AN4/SS
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
REF-/
REF
RA2
AN2
V
REF-
REF
CV
REF+
RA3
AN3
REF+
V
RA4
T0CKI
C1OUT
/C2OUT
RA5
AN4
SS
C2OUT
— = Not used TTL = TTL input ST = Schmitt Trigger input
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PDIP , SOIC,
SSOP Pin#
9
10 7
126
227
328
41
52
63
74
QFN
Pin#
6
I/O/P
Type
I
I
O
O
I
P
I/O
I
I/O
I
I/O
I
I
O
I/O
I
I
I/O
I
O
I/O
I
I
O
Buffer
Type
(3)
ST/CMOS
— Oscillator crystal or clock output.
ST Master Clear (input) or programming voltage (output).
TTL
TTL
TTL
TTL
ST
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input. ST
buffer when configured in RC mode; otherwise CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
Master Clear (Reset) input. This pin is an active low Reset
to the device.
Programming voltage input.
PORTA is a bidirectional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator V
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
Digital I/O – Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
Digital I/O.
Analog input 4.
SPI slave select input.
Comparator 2 output.
Description
REF output.
DS39582B-page 8 2003 Microchip Technology Inc.
PIC16F87XA
TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED)
Pin Name
RB0/INT
RB0
INT
RB1
RB2
RB3/PGM
RB3
PGM
RB4
RB5
RB6/PGC
RB6
PGC
RB7/PGD
RB7
PGD
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
SS 8, 19 5, 6 P — Ground reference for logic and I/O pins.
V
DD 20 17 P — Positive supply for logic and I/O pins.
V
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
— = Not used TTL = TTL input ST = Schmitt Trigger input
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PDIP , SOIC,
SSOP Pin#
21 18
22 19 I/O TTL
23 20 I/O TTL
24 21
25 22 I/O TTL
26 23 I/O TTL
27 24
28 25
11 8
12 9
13 10
14 11
15 12
16 13
17 14
18 15
QFN
Pin#
I/O/P
Type
I/O
I
I/O
I
I/O
I
I/O
I/O
I/O
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
O
I/O
I/O
I
I/O
Buffer
Type
TTL/ST
TTL
TTL/ST
TTL/ST
ST
ST
ST
ST
ST
ST
ST
ST
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
(1)
Digital I/O.
External interrupt.
Digital I/O.
Digital I/O.
Digital I/O.
Low-voltage (single-supply) ICSP programming enable pin.
Digital I/O.
(2)
(2)
Digital I/O.
Digital I/O.
In-circuit debugger and ICSP programming clock.
Digital I/O.
In-circuit debugger and ICSP programming data.
PORTC is a bidirectional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
Digital I/O.
Capture1 input, Compare1 output, PWM1 output.
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
Digital I/O.
SPI data in.
2
C data I/O.
I
Digital I/O.
SPI data out.
Digital I/O.
USART asynchronous transmit.
USART1 synchronous clock.
Digital I/O.
USART asynchronous receive.
USART synchronous data.
2
C mode.
2003 Microchip Technology Inc. DS39582B-page 9
PIC16F87XA
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION
PDIP
PLCC
Pin Name
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO
OSC2
CLKO
/VPP
MCLR
MCLR
VPP
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI/C1OUT
RA5/AN4/SS
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
REF-/CVREF
RA2
AN2
V
REF-
REF
CV
REF+
RA3
AN3
REF+
V
RA4
T0CKI
C1OUT
/C2OUT
RA5
AN4
SS
C2OUT
— = Not used TTL = TTL input ST = Schmitt Trigger input
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
Pin#
13 14 30 32
14 15 31 33
1 2 18 18
2 3 19 19
3 4 20 20
4 5 21 21
5 6 22 22
6 7 23 23
7 8 24 24
Pin#
TQFP
Pin#
QFN
Pin#
I/O/P
Type
I
I
O
O
I
P
I/O
I
I/O
I
I/O
I
I
O
I/O
I
I
I/O
I
O
I/O
I
I
O
Buffer
Type
(4)
ST/CMOS
ST Master Clear (input) or programming voltage (output).
TTL
TTL
TTL
TTL
ST
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
otherwise CMOS.
External clock source input. Always associated
with pin function OSC1 (see OSC1/CLKI,
OSC2/CLKO pins).
— Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal
Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
Master Clear (Reset) input. This pin is an active
low Reset to the device.
Programming voltage input.
PORTA is a bidirectional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator V
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
Digital I/O – Open-drain when configured as
output.
Timer0 external clock input.
Comparator 1 output.
Digital I/O.
Analog input 4.
SPI slave select input.
Comparator 2 output.
Description
REF output.
DS39582B-page 10 2003 Microchip Technology Inc.
PIC16F87XA
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
PDIP
PLCC
Pin Name
RB0/INT
RB0
INT
RB1 34 37 9
RB2 35 38 10
RB3/PGM
RB3
PGM
RB4 37 41 14
RB5 38 42 15
RB6/PGC
RB6
PGC
RB7/PGD
RB7
PGD
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
Pin#
33 36 8
36 39 11
39 43 16
40 44 17
Pin#
TQFP
Pin#
QFN
Pin#
9
10 I/O
11 I/O
12
14 I/O
15 I/O
16
17
I/O/P
Type
I/O
I
I/O
I
I/O
I
I/O
I/O
Buffer
Type
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
(1)
TTL/ST
Digital I/O.
External interrupt.
TTL Digital I/O.
TTL Digital I/O.
TTL
TTL Digital I/O.
TTL Digital I/O.
TTL/ST
TTL/ST
Digital I/O.
Low-voltage ICSP programming enable pin.
(2)
Digital I/O.
In-circuit debugger and ICSP programming clock.
(2)
Digital I/O.
In-circuit debugger and ICSP programming data.
Description
2003 Microchip Technology Inc. DS39582B-page 11
PIC16F87XA
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
PDIP
PLCC
Pin Name
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
Pin#
15 16 32 34
16 18 35 35
17 19 36 36
18 20 37 37
23 25 42 42
24 26 43 43
25 27 44 44
26 29 1 1
Pin#
TQFP
Pin#
QFN
Pin#
I/O/P
Type
I/O
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
O
I/O
I/O
I
I/O
Buffer
Type
ST
ST
ST
ST
ST
ST
ST
ST
Description
PORTC is a bidirectional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture2 i nput, Comp are2 output , PWM2 output.
Digital I/O.
Capture1 i nput, Comp are1 output , PWM1 output.
Digital I/O.
Synchronous serial clock input/output for SPI
mode.
Synchronous serial clock input/output for I
mode.
Digital I/O.
SPI data in.
2
C data I/O.
I
Digital I/O.
SPI data out.
Digital I/O.
USART asynchronous transmit.
USART1 synchronous clock.
Digital I/O.
USART asynchronous receive.
USART synchronous data.
2
C
DS39582B-page 12 2003 Microchip Technology Inc.
PIC16F87XA
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
PDIP
PLCC
Pin Name
RD0/PSP0
Pin#
19 21 38 38
Pin#
TQFP
Pin#
RD0
PSP0
RD1/PSP1
20 22 39 39
RD1
PSP1
RD2/PSP2
21 23 40 40
RD2
PSP2
RD3/PSP3
22 24 41 41
RD3
PSP3
RD4/PSP4
27 30 2 2
RD4
PSP4
RD5/PSP5
28 31 3 3
RD5
PSP5
RD6/PSP6
29 32 4 4
RD6
PSP6
RD7/PSP7
30 33 5 5
RD7
PSP7
RE0/RD
/AN5
8 9 25 25
RE0
RD
AN5
RE1/WR
/AN6
9102626
RE1
WR
AN6
RE2/CS
/AN7
10 11 27 27
RE2
CS
AN7
SS 12, 31 13, 34 6, 29 6, 30,
V
DD 11, 32 12, 35 7, 28 7, 8,
V
NC — 1, 17,
28, 40
12,13,
33, 34
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port or Parallel Slave
Port when interfacing to a microprocessor bus.
(3)
ST/TTL
I/O
I/O
ST/TTL
I/O
I/O
ST/TTL
I/O
I/O
ST/TTL
I/O
I/O
ST/TTL
I/O
I/O
ST/TTL
I/O
I/O
ST/TTL
I/O
I/O
ST/TTL
I/O
I/O
Digital I/O.
Parallel Slave Port data.
(3)
Digital I/O.
Parallel Slave Port data.
(3)
Digital I/O.
Parallel Slave Port data.
(3)
Digital I/O.
Parallel Slave Port data.
(3)
Digital I/O.
Parallel Slave Port data.
(3)
Digital I/O.
Parallel Slave Port data.
(3)
Digital I/O.
Parallel Slave Port data.
(3)
Digital I/O.
Parallel Slave Port data.
PORTE is a bidirectional I/O port.
(3)
ST/TTL
I/O
I
I
ST/TTL
I/O
I
I
ST/TTL
I/O
I
I
Digital I/O.
Read control for Parallel Slave Port.
Analog input 5.
(3)
Digital I/O.
Write control for Parallel Slave Port.
Analog input 6.
(3)
Digital I/O.
Chip select control for Parallel Slave Port.
Analog input 7.
P — Ground reference for logic and I/O pins.
31
P — Positive supply for logic and I/O pins.
28, 29
13 — — These pins are not internally connected. These pins
should be left unconnected.
2003 Microchip Technology Inc. DS39582B-page 13
PIC16F87XA
NOTES:
DS39582B-page 14 2003 Microchip Technology Inc.
PIC16F87XA
2.0 MEMORY ORGANIZATION
There are three memory blocks in each of the
PIC16F87XA devices. The program memory and data
memory have separate buses so that concurrent
access can oc cur and is detailed in this section. The
EEPROM data memory blo ck is deta iled in Section 3.0
“Data EEPROM and Flash Program Memory”.
Additional informa tion on devi ce memory may be found
in the PIC micro
Manual (DS33023).
FIGURE 2-1: PIC16F876A/877A
CALL, RETURN
RETFIE, RETLW
®
Mid-Range MCU Family Reference
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
Stack Level 1
Stack Level 2
2.1 Program Memory Organization
The PIC16F87XA devices have a 13-bit program
counter capable of addressing an 8K word x 14 bit
program memory space. The PIC16F876A/877A
devices have 8K words x 14 bits of Flash program
memory, while PIC16F873A/874A devices have
4K words x 14 bits. Accessing a location above the
physically implemented address will cause a
wraparound.
The Reset vector is at 0000h an d the interrupt vec tor is
at 0004h.
FIGURE 2-2: PIC16F873A/874A
PROGRAM MEMO RY MAP
AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
13
On-Chip
Program
Memory
Stack Level 8
Reset Vector
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
On-Chip
Program
Memory
Stack Level 8
Reset Vector
Interrupt Vector
Page 0
Page 1
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
2003 Microchip Technology Inc. DS39582B-page 15
PIC16F87XA
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (Status<6>) and
RP0 (Status<5>) are the bank select bits.
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Ab ove the Speci al Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
Note: The EEPROM data memory description can
be found in Section 3.0 “Data EEPROM
and Flash Program Memory” of this data
sheet.
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or
indirectly, through the File Select Register (FSR).
DS39582B-page 16 2003 Microchip Technology Inc.
FIGURE 2-3: PIC16F876A/877A REGISTER FI LE MAP
PIC16F87XA
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
(1)
(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
General
Purpose
Register
96 Bytes
Bank 0
File
Address
(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
(1)
TRISD
(1)
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
CMCON
CVRCON
ADRESL
ADCON1
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
Bank 1
File
Address
(*)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
EFh
F0h
FFh
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
General
Purpose
Register
16 Bytes
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
Bank 2
File
Address
(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
16Fh
170h
17Fh
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved
Reserved
(2)
(2)
General
Purpose
Register
16 Bytes
General
Purpose
Register
80 Bytes
accesses
70h - 7Fh
Bank 3
File
Address
(*)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
1EFh
1F0h
1FFh
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F876A.
2: These registers are reserved; maintain these registers clear.
2003 Microchip Technology Inc. DS39582B-page 17
PIC16F87XA
FIGURE 2-4: PIC16F873A/874A REGISTER FI LE MAP
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
(1)
(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
File
Address
(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
(1)
TRISD
(1)
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
CMCON
CVRCON
ADRESL
ADCON1
File
Address
(*)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.
TMR0
PCL
STAT US
FSR
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
File
Address
(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
120h
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved
Reserved
(2)
(2)
File
Address
(*)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
1A0h
General
Purpose
Register
96 Bytes
7Fh
Bank 0
General
Purpose
Register
96 Bytes
Bank 1
FFh
accesses
20h-7Fh
Bank 2
16Fh
170h
17Fh
accesses
A0h - FFh
1EFh
1F0h
1FFh
Bank 3
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F873A.
2: These registers are reserved; maintain these r egisters clear.
DS39582B-page 18 2003 Microchip Technology Inc.
PIC16F87XA
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
(3)
00h
01h TMR0 Timer0 Mo dule Register xxxx xxxx 55, 150
02h
03h
04h
05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 45, 150
07h PORTC PORTC Data Latch when written: POR TC pins when read xxxx xxxx 47, 150
08h
09h
0Ah
0Bh
0Ch PIR1 PSPIF
0Dh PIR2
0Eh TMR1L Holding Register for th e Least Sign ifican t Byte of the 16-bit TMR1 Register xxxx xxxx 60, 150
0Fh TMR1H Holding Register for the Most Significant Byte of t he 16-bi t TMR1 Register xxxx xxxx 60, 150
10h T1CON
11h TMR2 Timer2 Module Register 0000 0000 62, 150
12h T2CON
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 79, 150
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 82, 82,
15h CCPR1L Capture/Compare/P WM Register 1 (LSB ) xxxx xxxx 63, 150
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 63, 150
17h CCP1CON
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 112, 150
19h TXREG USART Transmit Data Register 0000 0000 118 , 150
1Ah RCREG USART Receive Data Register 0000 0000 118 , 150
1Bh CCPR2L Capture/Compar e/PWM Regist er 2 (LSB) xxxx xxxx 63, 150
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx 63, 150
1Dh CCP2CON
1Eh ADRESH A/D Result Register High Byte xxxx xxxx 133, 150
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 127, 150
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLA TH is a holding register for the PC<12:8>, whose
INDF Addressing this location uses contents of FSR to address data memory (not a physical regist er) 0000 0000 31, 150
(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 30, 150
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22, 150
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 31, 150
— — PORTA Dat a Latch when written: PO R TA pins when read --0x 0000 43, 150
(4)
PORTD PORTD Data Latch when written: POR TD pins when read xxxx xxxx 48, 150
(4)
PORTE — — — — — RE2 RE1 RE0 ---- -xxx 49, 150
(1,3)
PCLAT H — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150
(3)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRI SE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 26, 150
—CMIF—EEIFBCLIF— —CCP2IF-0-0 0--0 28, 150
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 57, 150
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 61, 150
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 64, 150
— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 64, 150
Value on:
POR, BOR
Details
on page:
150
2003 Microchip Technology Inc. DS39582B-page 19
PIC16F87XA
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
(3)
80h
81h OPTION_R EG RBPU
82h
83h
84h
85h TRISA
86h TRISB PORTB Data Direction Register 1111 1111 45, 150
87h TRISC PORTC Data Direction Register 1111 1111 47, 150
88h
89h
8Ah
8Bh
8Ch PIE1 PSPIE
8Dh PIE2
8Eh PCON
8Fh — Unimplemented — —
90h — Unimplemented — —
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 83, 151
92h PR2 Timer2 Period Register 1111 1111 62, 151
93h SSPADD Synchronous Serial Port (I
94h SSPSTAT SMP CKE D/A
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC
99h SPBRG Baud Rate Generator Register 0000 0000 113, 151
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 135, 151
9Dh CVRCON CVREN CVROE CVRR
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 133, 151
9Fh ADCON1 ADFM ADCS2
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = rese rved.
Note 1: The upper byte of the program counter is not directly accessible. PCLA TH is a holding register for the PC<12:8>, whose
INDF Addressing this location uses contents of FSR to address data memory (not a physical regist er) 0000 0000 31, 150
(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 30, 150
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22, 150
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 31, 150
(4)
TRISD PORTD Data Direction Register 1111 1111 48, 151
(4)
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 50, 151
(1,3)
PCLAT H — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150
(3)
INTCON GIE PEIE TMR0IE INTE RBIE TMR 0IF INTF RBIF 0000 000x 24, 150
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRI SE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23, 150
— — PORTA Data Direction Register --11 1111 43, 150
(2)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 25, 151
—CMIE— EEIE BCLIE — — CCP2IE -0-0 0--0 27, 151
— — — — — —PORBOR ---- --qq 29, 151
2
C mode) Address Register 0000 0000 79, 151
PSR/WUA BF 0000 0000 79, 151
— BRGH TRMT TX9D 0000 -010 111, 151
— CVR3 CVR2 CVR1 CVR0 000- 0000 141, 151
— — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 128, 151
Value on:
POR, BOR
Details
on page:
DS39582B-page 20 2003 Microchip Technology Inc.
PIC16F87XA
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Bank 2
(3)
100h
INDF Addressing this location uses contents of FSR to address data memory (not a physical regist er) 0000 0000 31, 150
101h TMR0 Timer0 Module Register xxxx xxxx 55, 150
(3)
102h
103h
104h
PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30, 150
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22, 150
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 31, 150
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 45, 150
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
(1,3)
10Ah
10Bh
PCLAT H — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150
(3)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150
10Ch EEDATA EEPROM Data Register Low Byte xxxx xxxx 39, 151
10Dh EEADR EEPROM Address Register Low Byte xxxx xxxx 39, 151
10Eh EEDATH
10Fh EEADRH
— — EEPROM Data Register High Byte --xx xxxx 39, 151
— — — —
(5)
EEPROM Address Register High Byte ---- xxxx 39, 151
Bank 3
(3)
180h
181h OPTION_REG RBPU
182h
183h
184h
INDF Addressing this location uses contents of FSR to address data memory (not a physical regist er) 0000 0000 31, 150
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23, 150
(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 30, 150
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22, 150
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 31, 150
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 45, 150
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
(1,3)
18Ah
18Bh
18Ch EECON1 EEPGD
PCLAT H — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150
(3)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150
— — — WRERR WREN WR RD x--- x000 34, 151
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 39, 151
18Eh — Reserved; maintain cle ar 0000 0000 —
18Fh — Reserved; maintain clear 0000 0000 —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLA TH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRI SE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
Details
on page:
2003 Microchip Technology Inc. DS39582B-page 21
PIC16F87XA
2.2.2.1 Status Register
The St atus reg ister co ntai ns the ar ithmetic st atu s of the
ALU, the Reset st atu s an d th e ba nk sel ec t bi ts for data
memory.
The Status register can be the destination for any
instruction, as with any othe r regi st er. If the Status re gister is the destinat ion for an instruction that affects the
Z, DC or C bits, then the writ e to these three bits is disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable, therefore, the result of an instruction with the
Status register as destination may be different than
intended.
and PD bits are not
For example, CLRF STATUS, will c lea r the up per three
bits and set the Z bit. Thi s leaves the Status register as
000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Stat us regist er because the se inst ructions do not af fect
the Z, C or DC bits from the Status register. For other
instructions not affecting any status bits, see
Section 15.0 “Instruction Set Summary”.
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO
bit 7 bit 0
bit 7 IRP: Register Bank Sele ct bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 bytes.
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow
bit 0 C: Carry/borrow
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow
, the polarity is reversed)
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high, or low order bit of the source register.
PD ZDCC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39582B-page 22 2003 Microchip Technology Inc.
PIC16F87XA
2.2.2.2 OPTION_RE G Regi st er
The OPTION_R EG Regis ter i s a readabl e an d writ abl e
register , which cont ains various contr ol bits to conf igure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external
INT interrupt, TMR0 and the weak pull-u ps o n POR TB.
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU
bit 7 bit 0
bit 7 RBPU
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA 4/T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
INTEDG T0CS T0SE PSA PS2 PS1 PS0
: PORTB Pull-up Enable bit
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: When using Low-V olta ge ICSP Programm ing (LVP) and the pull-ups on PORTB ar e
enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3
and ensure the proper operation of the device
2003 Microchip Technology Inc. DS39582B-page 23
PIC16F87XA
2.2.2.3 INTCON Register
The INTCON register is a readable and writable register, which contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of its
corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software
should ensure the appropriate interrupt flag
bits are clear prior to enabling an interrupt.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIETMR0IEINTE RBIETMR0IFINTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: TMR0 Overfl ow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 regis ter has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins ch ang ed s t a te; a mismatch condi tion will continue to s et
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39582B-page 24 2003 Microchip Technology Inc.
PIC16F87XA
2.2.2.4 PI E1 Regi st er
The PIE1 register cont ains the ind ividual enab le bits for
the periph eral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIE
bit 7 bit 0
bit 7 PSPIE: Parallel Slav e Port Read/ W r i te Interru pt Enab le bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
Note 1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overfl ow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
enable any peripheral interrupt.
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS39582B-page 25
PIC16F87XA
2.2.2.5 PIR1 Register
The PIR1 register contains the individual flag bits for
the periph eral interrupts.
Note: Interrupt flag bits are set when an interrupt
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIF
bit 7 bit 0
bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software before retu rning
from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI – A transmission/reception has taken place.
• I
•I
- A transmission/reception has taken place.
- The initiated Start condition was completed by the SSP module.
- The initiated Stop condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A Start cond ition occ urred whil e the SSP modul e was Idl e (mult i-master s ystem).
- A Stop con dit ion o ccurre d whil e the SSP module was I dle (m ul ti-mas ter s ys tem ).
0 = No SSP interrupt condition has occurred
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 regist er capture occurred (must be cleared in software)
0 = No TMR1 regi ster capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
2
C Slave – A transmission/reception has taken place.
2
C Master
condition occurs regardless of the state of its
corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software
should ensure the appropriate interrupt bits
are clear prior to enabling an interrupt.
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39582B-page 26 2003 Microchip Technology Inc.
PIC16F87XA
2.2.2.6 PI E2 Regi st er
The PIE2 register cont ains the ind ividual enab le bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, EEPROM write operation interrupt and the
comparator interrupt.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
—CMIE— EEIE BCLIE — — CCP2IE
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disable the comparator interrupt
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt
0 = Disable bus collision interrupt
bit 2-1 Unimplemented: Read as ‘0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS39582B-page 27
PIC16F87XA
2.2.2.7 PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt, EEPROM
write operation interrupt and the comparator interrupt.
Note: Interrupt flag bits are set when an in terrupt
condition occurs regardle ss of the sta te of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
—CMIF— EEIF BCLIF — — CCP2IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 CMIF: Comparator Interrupt Flag bit
1 = The comparator input has changed (must be cleared in software)
0 = The comparator input has not changed
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP when configured for I
0 = No bus collision has occurred
bit 2-1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 regist er capture occurred (must be cleared in software)
0 = No TMR1 regi ster capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused.
2
C Master mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39582B-page 28 2003 Microchip Technology Inc.
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