MICROCHIP PIC16F87X Technical data
PIC16F87X
Data Sheet
28/40-Pin 8-Bit CMOS FLASH
Microcontrollers
2001 Microchip Technology Inc. DS30292C
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Trademarks
The Microchip name, logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, K
EELOQ, SEEVAL, MPLAB and The
Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM,
MPLINK, MPLIB, PICDEM, ICEPIC, Migratable Memory,
FanSense, ECONOMONITOR and SelectMode are trademarks of Microchip Technology Incorporated in the U.S.A.
Serialized Quick T erm Programming (SQTP) is a service mark
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All other trademarks mentioned herein are property of their
respective companies.
© 2001, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hoppin g
DS30292C - page ii 2001 Microchip Technology Inc.
PIC16F87X
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
• PIC16F873
• PIC16F874
• PIC16F876
• PIC16F877
Microcontroller Core Features:
• High performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 8K x 14 words of FLASH Program M em ory,
Up to 368 x 8 bytes of Data Memory (RAM)
Up to 256 x 8 bytes of EEPROM Data Memory
• Pinout compatible to the PIC16C73B/74B/76/77
• Interrupt capability (up to 14 sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable opera tion
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low power, high speed CMOS FLASH/EEPROM
technology
• Fully static design
• In-Circuit Serial Programming (ICSP) via two
pins
• Single 5V In-Circuit Seria l Programming capabi lit y
• In-Circuit Debugging via two pins
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial, Industria l and Extended temp erature
ranges
• Low-power consumption:
- < 0.6 mA typical @ 3V, 4 MHz
-20 µA typical @ 3V, 32 kHz
-< 1 µA typical standby current
Pin Diagram
PDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16F877/874
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 10-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI
mode) and I
2C
(Master/Slave)
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
• Parallel Slave Port (PSP) 8-bits wide, with
external RD
, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
(Master
2001 Microchip Technology Inc. DS30292C-page 1
PIC16F87X
Pin Diagrams
PDIP, SOIC
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/V
RA3/AN3/V
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC3/SCK/SCL
REF-
REF+
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
RC2/CCP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC16F876/873
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
V
DD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
REF-
/VPP
PLCC
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR
/AN6
RE2/CS
/AN7
V
DD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
RA3/AN3/VREF+
65432
7
8
9
10
11
12
13
14
15
16
17
181920212223242526
NC
RA1/AN1
RA0/AN0
RB7/PGD
MCLR
1
44
RA2/AN2/V
PIC16F877
PIC16F874
RB6/PGC
43
RB5
42
RB4
41
27
NC
40
39
38
37
36
35
34
33
32
31
30
29
28
RB3/PGM
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
V
VDD
RB0/INT
RB1
RB2
RB3/PGM
NC
RC5/SDO
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
QFP
SS
RC6/TX/CK
4443424140
1
2
3
4
5
6
7
8
9
10
11
121314
NC
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
39
38
PIC16F877
PIC16F874
16
17
1819202122
15
NC
RB5
RB4
RB6/PGC
RB7/PGD
/VPP
MCLR
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
363435
37
REF-
RA1/AN1
RA0/AN0
RA2/AN2/V
NC
33
32
31
30
29
28
27
26
25
24
23
RA3/AN3/VREF+
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
SS
V
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
RC2/CCP1
RC3/SCK/SCL
RC1/T1OSI/CCP2
RC6/TX/CK
RC4/SDI/SDA
DS30292C-page 2 2001 Microchip Technology Inc.
PIC16F87X
Key Features
PICmicro™ Mid-Range Reference
Manual (DS33023)
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz
RESETS (and Delays) POR, BOR
FLASH Program Memory
(14-bit words)
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory 128 128 256 256
Interrupts 13 14 13 14
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Timers 3333
Capture/Compa re/PW M Modules 2 2 2 2
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Communications — PSP — PSP
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Instruction Set 35 instructions 35 instructions 35 instructions 35 instructions
PIC16F873 PIC16F874 PIC16F876 PIC16F877
POR, BOR
(PWRT, OST)
4K 4K 8K 8K
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
2001 Microchip Technology Inc. DS30292C-page 3
PIC16F87X
Table of Contents
1.0 Device Overview................................................................................................................................................... 5
2.0 Memory Organization.......................................................................................................................................... 11
3.0 I/O Ports.............................................................................................................................................................. 29
4.0 Data EEPROM and FLASH Program Memory.................................................................................................... 41
5.0 Timer0 Module.................................................................................................................................................... 47
6.0 Timer1 Module.................................................................................................................................................... 51
7.0 Timer2 Module.................................................................................................................................................... 55
8.0 Capture/Compare/PWM Modules....................................................................................................................... 57
9.0 Master Synchronous Serial Port (MSSP) Module............................................................................................... 65
10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........................................ 95
11.0 Analog-to-Digital Converter (A/D) Module......................................................................................................... 111
12.0 Special Features of the CPU............................................................................................................................. 119
13.0 Instruction Set Summary ................................................................................................................................... 135
14.0 Development Support ....................................................... ...... ...... ..... ............................................................... 143
15.0 Electrical Characteristics................................................................................................................................... 149
16.0 DC and AC Characteristics Graphs and Tables................................................................................................ 177
17.0 Packaging Information ...................................................................................................................................... 189
Appendix A: Revision History .................................................................................................................................... 197
Appendix B: Device Differences ................................................................................................................................ 197
Appendix C: Conversion Considerations................................................................................................................... 198
Index .......................................................................................................................................................................... 199
On-Line Support......................................................................................................................................................... 207
Reader Response...................................................................................................................................................... 208
PIC16F87X Product Identification System................................................................................................................. 209
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DS30292C-page 4 2001 Microchip Technology Inc.
PIC16F87X
1.0 DEVICE OVERVIEW
There are four devices (PIC16F873, PIC16F874,
PIC16F876 and PIC16F877) covered by this data
This document contains device specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The
Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device
architecture and operation of the peripheral modules.
sheet. The PIC16F876/873 devices come in 28-pin
packages and the PIC16F877/874 devices come in
40-pin packages. The Parallel Slave Port is not
implemented on the 28-pin devic es .
The following device block diagrams are s orted by pin
number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2.
The 28-pin and 40-pin pin outs are listed in Table 1- 1
and Table 1-2, respectively.
FIGURE 1-1: PIC16F873 AND PIC16F876 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
PIC16F873 4K 192 Bytes 128 Bytes
PIC16F876 8K 368 Bytes 256 Bytes
13
Program Counter
FLASH
Program
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
Direct Addr
8
8 Level Stack
(13-bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
In-Circuit
Debugger
Low Voltage
Programming
Data
EEPROM
RAM Addr
7
8
Data Bus
(1)
3
RAM
File
Registers
9
Addr MUX
8
FSR reg
STATUS reg
MUX
ALU
W reg
8
Indirect
Addr
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MCLR
Data EEPROM
Note 1: Higher order bits are from the STATUS register.
CCP1,2
VDD, VSS
Synchronous
Serial Port
10-bit A/DTimer0 Timer1 Timer2
USART
2001 Microchip Technology Inc. DS30292C-page 5
PIC16F87X
FIGURE 1-2: PIC16F874 AND PIC16F877 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
Data
EEPROM
PIC16F874 4K 192 Bytes 128 Bytes
PIC16F877 8K 368 Bytes 256 Bytes
13
Program Counter
8 Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
In-Circuit
Debugger
Low-Voltage
Programming
MCLR
(13-bit)
RAM Addr
7
Timer
Reset
Timer
Reset
VDD, VSS
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
FLASH
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
Data Bus
RAM
File
Registers
(1)
Addr MUX
3
ALU
8
W reg
Parallel Slave Port
9
Indirect
8
Addr
FSR reg
STATUS reg
MUX
10-bit A/DTimer0 Timer1 Timer2
8
PORTA
PORTB
PORTC
PORTD
PORTE
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
Data EEPROM
Note 1: Higher order bits are from the STATUS register.
CCP1,2
Synchronous
Serial Port
USART
DS30292C-page 6 2001 Microchip Technology Inc.
TABLE 1-1: PIC16F873 AND PIC16F876 PINOUT DESCRIPTION
PIC16F87X
Pin Name
DIP
Pin#
OSC1/CLKIN 9 9 I ST/CMOS
SOIC
Pin#
I/O/P
Type
Buffer
Type
Description
(3)
Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
/VPP 1 1 I/P ST Master Clear (Reset) input or programming voltage input. This
MCLR
pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0.
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1.
RA2/AN2/V
REF- 4 4 I/O TTL RA2 can also be analog input2 or negative analog
reference voltage.
RA3/AN3/V
REF+ 5 5 I/O TTL RA3 can also be analog input3 or positive analog
reference voltage.
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0
module. Output is open drain type.
/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select
RA5/SS
for the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST
(1)
RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3/PGM 24 24 I/O TTL RB3 can also be the low voltage programming input.
RB4 25 25 I/O TTL Interrupt-on-change pin.
RB5 26 26 I/O TTL Interrupt-on-change pin.
RB6/PGC 27 27 I/O TTL/ST
(2)
Interrupt-on-change pin or In-Circuit Debugger pin. Serial
programming clock.
RB7/PGD 28 28 I/O TTL/ST
(2)
Interrupt-on-change pin or In-Circuit Debugger pin. Serial
programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I
2
C mode).
2
C modes.
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Rece ive or
Synchronous Data.
SS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
V
DD 20 20 P — Positive supply for logic and I/O pins.
V
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2001 Microchip Technology Inc. DS30292C-page 7
PIC16F87X
TABLE 1-2: PIC16F874 AND PIC16F877 PINOUT DESCRIPTION
DIP
Pin Name
OSC1/CLKIN 13 14 30 I ST/CMOS
OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator
/VPP 1 2 18 I/P ST Master Clear (Reset) input or programming voltage input.
MCLR
RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0.
RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1.
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/
RA5/SS/
RB0/INT 33 36 8 I/O TTL/ST
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3/PGM 36 39 11 I/O TTL RB3 can also be the low voltage programming input.
RB4 37 41 14 I/O TTL Interrupt-on-change pin.
RB5 38 42 15 I/O TTL Interrupt-on-change pin.
RB6/PGC 39 43 16 I/O TTL/ST
RB7/PGD 40 44 17 I/O TTL/ST
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
REF- 4 5 21 I/O TTL RA2 can also be analog input2 or negative
REF+ 5 6 22 I/O TTL RA3 can also be analog input3 or positive
AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
PLCC
Pin#
— = Not used TTL = TTL input ST = Schmitt Trigger input
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Description
(4)
Oscillator crystal input/external clock source input.
in crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
This pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
analog reference voltage.
analog reference voltage.
counter. Output is open drain type.
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
(1)
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt-on-change pin or In-Circuit Debugger pin.
Serial programming clock.
Interrupt-on-change pin or In-Circuit Debugger pin.
Serial programming data.
DS30292C-page 8 2001 Microchip Technology Inc.
PIC16F87X
TABLE 1-2: PIC16F874 AND PIC16F877 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin Name
Pin#
PLCC
Pin#
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a
RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1
RC3/SCK/SCL 18 20 37 I/O S T RC3 can also be the synchronous serial clock input/
RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit
RC7/RX/DT 26 29 1 I/O S T RC7 can also be the USART Asynchronous Receive
RD0/PSP0 19 21 38 I/O ST/TTL
RD1/PSP1 20 22 39 I/O ST/TTL
RD2/PSP2 21 23 40 I/O ST/TTL
RD3/PSP3 22 24 41 I/O ST/TTL
RD4/PSP4 27 30 2 I/O ST/TTL
RD5/PSP5 28 31 3 I/O ST/TTL
RD6/PSP6 29 32 4 I/O ST/TTL
RD7/PSP7 30 33 5 I/O ST/TTL
/AN5 8 9 25 I/O ST/TTL
RE0/RD
RE1/WR
RE2/CS
V
V
/AN6 9 10 26 I/O ST/TTL
/AN7 10 11 27 I/O ST/TTL
SS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
DD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
NC — 1,17,28,4012,13,
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
QFP
Pin#
33,34
I/O/P
Type
Buffer
Type
Description
PORTC is a bi-directional I/O port.
Timer1 clock input.
Capture2 input/Compare2 output/PWM2 output.
output/PWM1 output.
2
output for both SPI and I
2
data I/O (I
C mode).
C modes.
or Synchronous Clock.
or Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
PORTE is a bi-directional I/O port.
(3)
RE0 can also be read control for the parallel slave
port, or analog input5.
(3)
RE1 can also be write control for the parallel slave
port, or analog input6.
(3)
RE2 can also be select control for the parallel slave
port, or analog input7.
— These pins are not internally connected. These pins
should be left unconnected.
2001 Microchip Technology Inc. DS30292C-page 9
PIC16F87X
NOTES:
DS30292C-page 10 2001 Microchip Technology Inc.
PIC16F87X
2.0 MEMORY ORGANIZATION
There are three memory blocks in each of the
PIC16F87X MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can oc cur and is detailed in this section. The
EEPROM data memory block is detailed in Se ction 4.0.
Additional informa tion on devi ce memory may be found
in the PICmicro Mid-Range Reference Manual,
(DS33023).
FIGURE 2-1: PIC16F877/876 PROGRAM
MEMORY MAP AND
STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
13
2.1 Program Memory Organization
The PIC16F87X devic es have a 13-bit p rogram count er
capable of addressing an 8K x 14 program memory
space. The PIC16F877/876 devices have 8K x 14
words of FLASH program memory, and the
PIC16F873/874 devices have 4K x 14. Accessing a
location above the ph ysicall y implem ented addres s will
cause a wraparound.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-2: PIC16F874/873 PROGRAM
MEMORY MAP AND
STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
13
On-Chip
Program
Memory
Stack Level 8
RESET Vector
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
On-Chip
Program
Memory
Stack Level 8
RESET Vector
Interrupt Vector
Page 0
Page 1
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
2001 Microchip Technology Inc. DS30292C-page 11
PIC16F87X
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
Note: EEPROM Data Memory de scription can b e
found in Section 4.0 of this data sheet.
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be acces sed either directly, or indirectly through the File Select Register (FSR).
DS30292C-page 12 2001 Microchip Technology Inc.
FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP
PIC16F87X
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
(1)
(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
File
File
Address
Address
(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
(1)
TRISD
(1)
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADRESL
ADCON1
Address
(*)
File
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
General
Purpose
Register
16 Bytes
Address
(*)
File
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved
Reserved
(2)
(2)
General
Purpose
Register
16 Bytes
Address
(*)
File
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
96 Bytes
Bank 0
7Fh
General
Purpose
Register
80 Bytes 80 Bytes 80 Bytes
EFh
accesses
F0h
70h-7Fh
FFh
Bank 1
General
Purpose
Register
accesses
70h-7Fh
Bank 2
16Fh
170h
17Fh
General
Purpose
Register
accesses
70h - 7Fh
Bank 3
1EFh
1F0h
1FFh
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F876.
2: These registers are reserved, maintain these registers clear.
2001 Microchip Technology Inc. DS30292C-page 13
PIC16F87X
FIGURE 2-4: PIC16F874/873 REGISTER FILE MAP
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
(1)
(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
File
Address
(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
(1)
TRISD
(1)
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADRESL
ADCON1
File
Address
(*)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
Address
(*)
File
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
120h
Indirect addr.
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved
Reserved
(2)
(2)
Address
(*)
File
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
1A0h
General
Purpose
Register
96 Bytes
7Fh
Bank 0
General
Purpose
Register
96 Bytes
Bank 1
FFh
accesses
20h-7Fh
Bank 2
16Fh
170h
17Fh
accesses
A0h - FFh
1EFh
1F0h
1FFh
Bank 3
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F873.
2: These registers are reserved, maintain these registers clear.
DS30292C-page 14 2001 Microchip Technology Inc.
PIC16F87X
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
(3)
00h
01h TMR0 Timer 0 Module Register
02h
03h
04h
05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read
07h PORTC PORTC Data Latch when written: PORTC pins when read
08h
09h
0Ah
0Bh
0Ch PIR1 PSPIF
0Dh PIR2
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register
10h T1CON
11h TMR2 Timer2 Module Regis ter
12h T2CON
13h SSPBUF Synchronous Serial Port Rece i ve Buffer/Transmit Regi ste r
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
15h CCPR1L Capture/Compare/PWM Register1 (LSB)
16h CCPR1H Capture/Compare/PWM Register1 (MSB)
17h CCP1CON
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
19h TXREG USART Transmit Data Register
1Ah RCREG USART Receive Data Register
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB)
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB)
1Dh CCP2CON
1Eh ADRESH A/D Result Register High Byte
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
Legend:
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 26
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 27
— — PORTA Data Latch when written: PORTA pins when read --0x 0000 29
(4)
PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 35
(4)
PORTE — — — — — RE2 RE1 RE0 ---- -xxx 36
(1,3)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
(3)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 22
— (5) — EEIF BCLIF — — CCP2IF -r-0 0--0 24
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 51
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 55
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 58
— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 58
— ADON 0000 00-0 111
Value on:
POR,
BOR
xxxx xxxx 47
xxxx xxxx 31
xxxx xxxx 33
xxxx xxxx 52
xxxx xxxx 52
0000 0000 55
xxxx xxxx 70, 73
0000 0000 67
xxxx xxxx 57
xxxx xxxx 57
0000 000x 96
0000 0000 99
0000 0000 101
xxxx xxxx 57
xxxx xxxx 57
xxxx xxxx 116
Details
on
page:
2001 Microchip Technology Inc. DS30292C-page 15
PIC16F87X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
(3)
80h
81h OPTION_REG RBPU
82h
83h
84h
85h TRISA
86h TRISB PORTB Data Direction Register
87h TRISC PORTC Data Direction Register
88h
89h
8Ah
8Bh
8Ch PIE1 PSPIE
8Dh PIE2
8Eh PCON
8Fh — Unimplemented — —
90h — Unimplemented — —
91h S SPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
92h PR2 Timer2 Period Register
93h SSPADD Synchronous Serial Port (I
94h SSPSTAT SMP CKE D/A
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC
99h SPBRG Baud Rate Generator Register
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh ADRESL A/D Result Register Low Byte
9Fh ADCON1 ADFM
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 26
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 27
(4)
TRISD PORTD Data Direction Register 1111 1111 35
(4)
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 37
(1,3)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
(3)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19
— — PORTA Data Direction Register --11 1111 29
(2)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 21
— (5) — EEIE BCLIE — — CCP2IE -r-0 0--0 23
— — — — — — POR BOR ---- --qq 25
2
C mode) Address Register 0000 0000 73, 74
PSR/WUA BF 0000 0000 66
— BRGH TRMT TX9D 0000 -010 95
— — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 112
Value on:
POR,
BOR
1111 1111 31
1111 1111 33
0000 0000 68
1111 1111 55
0000 0000 97
xxxx xxxx 116
Details
on
page:
DS30292C-page 16 2001 Microchip Technology Inc.
PIC16F87X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 2
(3)
100h
101h TMR0 Timer0 Module Register
102h
103h
104h
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah
10Bh
10Ch EEDATA EEPROM Da ta Register Low By te
10Dh EEADR EEPROM Address Register Low Byte
10Eh EEDATH
10Fh EEADRH
Bank 3
180h
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
182h
183h
184h
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah
18Bh
18Ch EECON1 EEPGD
18Dh EECON2 EEPROM Control Register2 (not a physical register)
18Eh — Reserved maintain clear 0000 0000 —
18Fh — Reserved maintain clear 0000 0000 —
Legend:
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
(3)
PCL Program Counter’s (PC) Least Significant Byte 0000 0000 26
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 27
(1,3)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
(3)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
— — EEPROM Data Register High Byte xxxx xxxx 41
— — — EEPROM Address Register High Byte xxxx xxxx 41
(3)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 26
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 27
(1,3)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
(3)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
— — — WRERR WREN WR RD x--- x000 41, 42
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
Value on:
POR,
BOR
xxxx xxxx 47
xxxx xxxx 31
xxxx xxxx 41
xxxx xxxx 41
1111 1111 19
1111 1111 31
---- ---- 41
Details
on
page:
2001 Microchip Technology Inc. DS30292C-page 17
PIC16F87X
2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the RESET statu s and the b ank sele ct bit s for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable, therefore, the result of an instruction with the
STATUS register as dest ination may be di fferent than
intended.
and PD bits are not
For example, CLRF STATUS will clear the upper three
bits and set t he Z bit. T his leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the ST ATUS register. For
other instructions not affecting any status bits, see the
“Instruction Set Summary."
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow
bit 0 C: Carry/borrow
: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high, or low order bit of the source register.
, the polarity is reversed. A subtraction is executed by adding the two’s
PD ZDCC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30292C-page 18 2001 Microchip Technology Inc.
PIC16F87X
2.2.2.2 OPTION_REG Register
The OPTION_R EG Regis ter i s a readabl e an d writ abl e
register , which cont ains various contr ol bits to conf igure
the TMR0 prescaler/WDT postscaler (single assignable register k nown als o as th e presca ler), t he Externa l
INT Interrupt, TMR0 and the w eak pull-up s on POR TB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
bit 7 RBPU
bit 6 INTEDG: Interrupt Edge Select bit
bit 5 T0CS: TMR0 Clock Source Select bit
bit 4 T0SE: TMR0 Source Edge Select bit
bit 3 PSA: Prescaler Assignment bit
bit 2-0 PS2:PS0: Prescaler Rate Select bits
: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
1 = Transition on RA 4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: When using low volt age ICSP p rogramming (LVP) and the pull-ups on PORTB are enabled , bit 3
in the TRISB register m ust be cleared to disa ble th e pull -up on R B3 and ensu re the p roper op eration of th e device
2001 Microchip Technology Inc. DS30292C-page 19
PIC16F87X
2.2.2.3 INTCON Register
The INTCON Register is a readabl e and writ able register, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
Note: Interrupt flag bits are set when an interru pt
condition occurs, re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has ov erflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in softwar e)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB 7:RB4 pins changed state ; a m is m atc h c ond iti on will continue to set
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30292C-page 20 2001 Microchip Technology Inc.
2.2.2.4 PIE1 Register
The PIE1 register cont ains the ind ividual enab le bits for
the periph eral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIE
bit 7 bit 0
bit 7 PSPIE
bit 6 ADIE: A/D Converter Interrupt Enable bit
bit 5 RCIE: USART Receive Interrupt Enable bit
bit 4 TXIE: USART Transmit Interrupt Enable bit
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
bit 2 CCP1IE: CCP1 Interrupt Enable bit
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
1 = Enables the USART receive interrupt
0 = Disables the USART receiv e interrupt
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
: Parallel Slave Port Read/Write Interrupt Enable bit
PIC16F87X
Note 1: PSPIE is reserved on PIC16F873/876 devices; always maintain this bit clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. DS30292C-page 21
PIC16F87X
2.2.2.5 PIR1 Register
The PIR1 register contains the individual flag bits for
the periph eral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIF
bit 7 bit 0
bit 7 PSPIF
bit 6 ADIF: A/D Converte r Interrupt Flag bit
bit 5 RCIF: USART Receive Interrupt Flag bit
bit 4 TXIF: USART Transmit Interrupt Flag bit
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
bit 2 CCP1IF: CCP1 Interrupt Flag bit
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
1 = An A/D conversion completed
0 = The A/D conversion is not complete
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
1 = The SSP interrupt condition has occurred, and must be cleared in software b efore returning
from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI
• I
2
• I
0 = No SSP interrupt condition has occurred.
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compar e match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PSPIF is reserved on PIC16F873/876 devices; always maintain this bit clear.
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
: Parallel Slave Port Read/Write Interrupt Flag bit
- A transmission/reception has taken place.
2
C Slave
- A transmission/reception has taken place.
C Master
- A transmission/reception has taken place.
- The initiated START condition was completed by the SSP module.
- The initiated STOP condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A START con dition occurre d while the SSP module was idle (Multi-Master system).
- A STOP condition o ccurre d w h ile th e S SP m odu le w as i dle (M ulti-Master system).
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should en sure the approp riate interrup t
bits are cle ar pri or to en ab li ng an i nte rru pt.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30292C-page 22 2001 Microchip Technology Inc.
2.2.2.6 PIE2 Register
The PIE2 register cont ains the ind ividual enab le bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, and the EEPROM write operation interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
— Reserved — EEIE BCLIE — — CCP2IE
bit 7 bit 0
bit 7 Unimplemented: Read as '0'
bit 6 Reserved: Always maintain this bit clear
bit 5 Unimplemented: Read as '0'
bit 4 EEIE: EEPROM Write Operation Interrupt Enable
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3 BCLIE: Bus Collision Interrupt Enable
1 = Enable Bus Collision Interrupt
0 = Disable Bus Collision Interrupt
bit 2-1 Unimplemented: Read as '0'
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
PIC16F87X
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. DS30292C-page 23
PIC16F87X
2.2.2.7 PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
.
Note: Interrupt flag bits are set when an interru pt
condition occurs, re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
— Reserved — EEIF BCLIF — — CCP2IF
bit 7 bit 0
bit 7 Unimplemented: Read as '0'
bit 6 Reserved: Always maintain this bit clear
bit 5 Unimplemented: Read as '0'
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I2C Master mode
0 = No bus collision has occurred
bit 2-1 Unimplemented: Read as '0'
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 regist er capture occurred (must be cleared in software)
0 = No TMR1 regi ster capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30292C-page 24 2001 Microchip Technology Inc.
PIC16F87X
2.2.2.8 PCON Register
The Power Control (PCON) Register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT), and an external MCLR
Reset.
Note: BOR is unknown on P OR. It mus t be set by
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurre d. The BOR st atus
bit is a “don’t care” and is n ot pre dictable if
the brown-out circuit is disabled (by clearing the BODEN bit in the configuration
word).
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
— — — — — —PORBOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as '0'
bit 1 POR
bit 0 BOR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. DS30292C-page 25
PIC16F87X
2.3 PCL and PCLATH
The program counter (PC) is 13-bits wid e. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLA TH reg is ter. On any RESET, the upper bits of the
PC will be cleared. Fig ure2-5 shows the two situations
for the loading of the PC. The up per ex ample in th e figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower exampl e i n th e fi gure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
87
PCLATH<4:3>
PCLATH
11
2.3.1 COMPUTED GOTO
A computed GOTO is accomplish ed by adding an offset
to the progr am counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercise d i f the t able loca tio n cros ses a PCL
memory boundary (each 256 byte block). Refer to the
application note, “Implementing a Table Read"
(AN556).
2.3.2 STACK
The PIC16F87X family has an 8-level deep x 13-bit wide
hardware stack. The stack sp ace is not part of either program or data space and the stack pointer is not readable
or writable. The PC is PUSHed onto the stack when a
CALL instruction is executed, or an interrupt causes a
branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLA TH is not affected by a PUSH or POP operation.
The stack opera tes as a circular buf fer . This means that
after the st ack h as be en PUSHed ei ght ti mes, th e nin th
push overwrites the v alue tha t was stored fro m the first
push. The tenth pus h ov erwri t es the se co nd p us h (an d
so on).
8
Instruction with
PCL as
Destination
ALU
GOTO,CALL
Opcode <10:0>
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an interrupt address.
2.4 Program Memory Paging
All PIC16F87X devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensu re tha t the p age select bits are
programmed so that the desired program memory
page is addressed. If a return from a CALL instruction
(or interrupt) is execute d, the entire 13-bit PC is popped
off the stack. Therefore, manipulation of the
PCLA TH<4:3> bits is not required for the return instructions (which POPs the address from the stack).
Note: The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH register for any subsequent subroutine calls or
GOTO instructions.
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory . Thi s example as sumes
that PCLATH is saved and restored by the Interrupt
Service Routine
EXAMPLE 2-1: CALL OF A SUBROUTINE
SUB1_P1
(if interrupts are used).
IN PAGE 1 FROM PAGE 0
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
: ;called subroutine
;page 1 (800h-FFFh)
:
RETURN ;return to
;Call subroutine
;in page 0
;(000h-7FFh)
DS30292C-page 26 2001 Microchip Technology Inc.
PIC16F87X
2.5 Indirect Addressing, INDF and FSR Registers
The INDF register is not a physi cal register. Addressin g
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruc tion using the INDF register actual ly
accesses the register pointed to by the File Sele ct Register, FSR. Reading the INDF register itself, indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly result s in a no op era tion ( alth oug h status bits
may be affected ). An ef fective 9- bit add ress is obt ained
by concatenating the 8 -bit FSR regi ster and the IRP b it
(STATUS<7>), as shown in Figure 2-6.
FIGURE 2-6: DIRECT/INDI RECT ADDRE SSING
RP1:RP 0 6
Bank Select Location Select
From Opcode
0
00 01 10 11
00h
80h
100h
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: INDIRECT ADDRESSING
MOVLW 0x20 ;initialize pointer
NEXT CLRF INDF ;clear INDF register
CONTINUE
MOVWF FSR ;to RAM
INCF FSR,F ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
: ;yes continue
Indirect AddressingDirect Addressing
IRP F SR regist er
Bank Select
180h
7
0
Location Select
Data
(1)
Memory
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: For register file map detail, see Figure 2-3.
FFh
17Fh
1FFh
2001 Microchip Technology Inc. DS30292C-page 27
PIC16F87X
NOTES:
DS30292C-page 28 2001 Microchip Technology Inc.
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