MICROCHIP PIC16F872 Technical data

PIC16F872

Data Sheet

28-Pin, 8-Bit CMOS Flash

Microcontroller with 10-Bit A/D

© 2006 Microchip Technology Inc. DS30221C

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are
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SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
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All other trademarks mentioned herein are property of their
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© 2006, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its
PICmicro
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEEL

®

OQ

code hopping devices, Serial

DS30221C-page ii © 2006 Microchip Technology Inc.

PIC16F872

28-Pin, 8-Bit CMOS FLASH Microcontroller

with 10-bit A/D

High Performance RISC CPU:

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches, which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• 2K x 14 words of FLASH Program Memory

• 128 bytes of Data Memory (RAM)

• 64 bytes of EEPROM Data Memory

• Pinout compatible to the PIC16C72A

• Interrupt capability (up to 10 sources)

• Eight level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Peripheral Features:

• High Sink/Source Current: 25 mA

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler,

can be incremented during SLEEP via external
crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period

register, prescaler and postscaler

• One Capture, Compare, PWM module

- Capture is 16-bit, max. resolution is 12.5 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM max. resolution is 10-bit

• 10-bit, 5-channel Analog-to-Digital converter (A/D)

• Synchronous Serial Port (SSP) with SPI™ (Master

mode) and I

• Brown-out detection circuitry for

Brown-out Reset (BOR)

2C™

(Master/Slave)

Pin Diagram

DIP, SOIC, SSOP

PIC16F872

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
V

DD

VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

MCLR/VPP

RA0/AN0
RA1/AN1

RA2/AN2/V

RA3/AN3/V

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC3/SCK/SCL

REF-

REF+

RA4/T0CKI

RA5/AN4/SS

VSS

OSC1/CLKIN

RC2/CCP1

1
2
3
4
5
6
7
8
9

10
11

12
13
14

Special Microcontroller Features:

• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• In-Circuit Serial Programming™ (ICSP™) via two
pins

• Single 5V In-Circuit Serial Programming capability

• In-Circuit Debugging via two pins

• Processor read/write access to program memory

CMOS Technology:

• Low power, high speed CMOS FLASH/EEPROM
technology

• Wide operating voltage range: 2.0V to 5.5V

• Fully static design

• Commercial, Industrial and Extended temperature
ranges

• Low power consumption:

- < 2 mA typical @ 5V, 4 MHz

-20 μA typical @ 3V, 32 kHz

-< 1 μA typical standby current

© 2006 Microchip Technology Inc. DS30221C-page 1

PIC16F872

Table of Contents

1.0 Device Overview......................................................................................................................................................................... 3

2.0 Memory Organization.................................................................................................................................................................. 7

3.0 Data EEPROM and FLASH Program Memory ......................................................................................................................... 23

4.0 I/O Ports.................................................................................................................................................................................... 29

5.0 Timer0 Module .......................................................................................................................................................................... 35

6.0 Timer1 Module .......................................................................................................................................................................... 39

7.0 Timer2 Module .......................................................................................................................................................................... 43

8.0 Capture/Compare/PWM Module ............................................................................................................................................... 45

9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 51

10.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 79

11.0 Special Features of the CPU .................................................................................................................................................... 87

12.0 Instruction Set Summary......................................................................................................................................................... 103

13.0 Development Support ............................................................................................................................................................. 111

14.0 Electrical Characteristics......................................................................................................................................................... 117

15.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 139

16.0 Packaging Information ............................................................................................................................................................ 151

Appendix A: Revision History ........................................................................................................................................................... 155

Appendix B: Conversion Considerations........................................................................................................................................... 155

Index ................................................................................................................................................................................................. 157

On-Line Support................................................................................................................................................................................ 163

Reader Response ............................................................................................................................................................................. 164

PIC16F872 Product Identification System ........................................................................................................................................ 165

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DS30221C-page 2 © 2006 Microchip Technology Inc.

PIC16F872

1.0 DEVICE OVERVIEW

This document contains device specific information
about the PIC16F872 microcontroller. Additional infor­mation may be found in the PICmicro™ Mid-Range
Reference Manual (DS33023), which may be obtained
from your local Microchip Sales Representative or
downloaded from the Microchip website. The Refer­ence Manual should be considered a complementary

document to this data sheet, and is highly recom­mended reading for a better understanding of the
device architecture and operation of the peripheral
modules.

The block diagram of the PIC16F872 architecture is
shown in Figure 1-1. A pinout description is provided in
Table 1-2.

TABLE 1-1: KEY FEATURES OF THE PIC16F872

Operating Frequency DC - 20 MHz

RESETS (and Delays) POR, BOR (PWRT, OST)

FLASH Program Memory (14-bit words) 2K

Data Memory (bytes) 128

EEPROM Data Memory (bytes) 64

Interrupts 10

I/O Ports Ports A, B, C

Timers 3

Capture/Compare/PWM module 1

Serial Communications MSSP

10-bit Analog-to-Digital Module 5 input channels

Instruction Set 35 Instructions

Packaging 28-lead PDIP

28-lead SOIC

28-lead SSOP

© 2006 Microchip Technology Inc. DS30221C-page 3

PIC16F872

FIGURE 1-1: PIC16F872 BLOCK DIAGRAM

Program

Bus

OSC1/CLKIN
OSC2/CLKOUT

FLASH

Program

Memory

14

Instruction reg

Instruction

Decode &

Control

Timing

Generation

13

Program Counter

8 Level Stack

Direct Addr

8

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

Brown-out

In-Circuit

Debugger

Low Voltage

Programming

(13-bit)

Timer

Reset

Timer

Reset

RAM Addr (1)

7

8

Data Bus

3

RAM

File

Registers

9

Addr MUX

8

FSR reg

STATUS reg

MUX

ALU

W reg

8

Indirect

Addr

PORTA

PORTB

PORTC

RA0/AN0
RA1/AN1
RA2/AN2/VREF­RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS

RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1

RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7

MCLR

VDD, VSS

Timer0 Timer1 Timer2

Data EEPROM

Note 1: Higher order bits are from the STATUS register.

CCP

Synchronous

Serial Port

10-bit A/D

DS30221C-page 4 © 2006 Microchip Technology Inc.

TABLE 1-2: PIC16F872 PINOUT DESCRIPTION

PIC16F872

Pin Name Pin#

OSC1/CLKI

OSC1

CLKI

OSC2/CLKO

OSC2

CLKO

/VPP

MCLR

MCLR

VPP

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
V

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI

RA4
T0CKI

RA5/SS/

RA5
SS
AN4

Legend: I = input O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

REF-

REF-

REF+

REF+

AN4

— = Not used TTL = TTL input ST = Schmitt Trigger input

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

9 I ST/CMOS Oscillator crystal or external clock input.

10 O — Oscillator crystal or clock output.

1 I/P ST Master Clear (input) or programming voltage (output).

2 I/O TTL

3 I/O TTL

4 I/O TTL

5 I/O TTL

6I/O ST

7 I/O TTL

I/O/P
Type

Buffer

Type

Description

Oscillator crystal input or external clock source input. ST

buffer when configured in RC mode. Otherwise CMOS.

External clock source input. Always associated with pin

function OSC1 (see OSC2/CLKO pin).

Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.

Master Clear (Reset) input. This pin is an active low
RESET to the device.
Programming voltage input.

PORTA is a bi-directional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
Negative analog reference voltage.

Digital I/O.
Analog input 3.
Positive analog reference voltage.

Digital I/O; open drain when configured as output.
Timer0 clock input.

Digital I/O.
Slave Select for the Synchronous Serial Port.
Analog input 4.

© 2006 Microchip Technology Inc. DS30221C-page 5

PIC16F872

TABLE 1-2: PIC16F872 PINOUT DESCRIPTION (CONTINUED)

Pin Name Pin#

RB0/INT

RB0
INT

RB1 22 I/O TTL Digital I/O.

RB2 23 I/O TTL Digital I/O.

RB3/PGM

RB3
PGM

RB4 25 I/O TTL Digital I/O.

RB5 26 I/O TTL Digital I/O.

RB6/PGC

RB6
PGC

RB7/PGD

RB7
PGD

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI

RC1
T1OSI

RC2/CCP1

RC2
CCP1

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6 17 I/O ST Digital I/O.

RC7 18 I/O ST Digital I/O.

SS 8, 19 P — Ground reference for logic and I/O pins.

V

VDD 20 P — Positive supply for logic and I/O pins.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

21 I/O TTL/ST

24 I/O TTL

27 I/O TTL/ST

28 I/O TTL/ST

11 I/O ST

12 I/O ST

13 I/O ST

14 I/O ST

15 I/O ST

16 I/O ST

I/O/P
Type

Buffer

Type

Description

PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.

(1)

Digital I/O.
External interrupt pin.

Digital I/O.
Low voltage ICSP programming enable pin.

(2)

Digital I/O.
In-Circuit Debugger and ICSP programming clock.

(2)

Digital I/O.
In-Circuit Debugger and ICSP programming data.

PORTC is a bi-directional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1 clock input.

Digital I/O.
Timer1 oscillator input.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.

Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
SPI Data In pin (SPI mode).
SPI Data I/O pin (I

Digital I/O.
SPI Data Out pin (SPI mode).

2

C mode).

2

C mode.

DS30221C-page 6 © 2006 Microchip Technology Inc.

PIC16F872

2.0 MEMORY ORGANIZATION

There are three memory blocks in the PIC16F872. The
Program Memory and Data Memory have separate
buses so that concurrent access can occur. Data mem­ory is covered in this section; the EEPROM data mem­ory and FLASH program memory blocks are detailed in
Section 3.0.

Additional information on device memory may be found
in the PICmicro™ Mid-Range Reference Manual
(DS33023).

2.1 Program Memory Organization

The PIC16F872 has a 13-bit program counter capable
of addressing an 8K word x 14 bit program memory
space. The PIC16F872 device actually has 2K words of
FLASH program memory. Accessing a location above
the physically implemented address will cause a wrap­around.

The RESET vector is at 0000h and the interrupt vector
is at 0004h.

FIGURE 2-1: PIC16F872 PROGRAM

MEMORY MAP AND
STACK

PC<12:0>

CALL, RETURN
RETFIE, RETLW

13

2.2 Data Memory Organization

The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.

RP1:RP0 Bank

00 0

01 1

10 2

11 3

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis­ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.

Note: EEPROM Data Memory description can be

found in Section 4.0 of this data sheet.

2.2.1 GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indi­rectly through the File Select Register (FSR).

On-Chip

Program

Memory

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

Interrupt Vector

Page 0

0000h

0004h
0005h

07FFh

1FFFh

© 2006 Microchip Technology Inc. DS30221C-page 7

PIC16F872

FIGURE 2-2: PIC16F872 REGISTER FILE MAP

File

Address

Indirect addr.

TMR0

PCL

STATUS

FSR

PORTA
PORTB
PORTC

PCLATH
INTCON

PIR1
PIR2

TMR1L
TMR1H
T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

ADRESH
ADCON0 ADCON1

General
Purpose
Register

96 Bytes

Bank 0

(*)

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh

20h

7Fh

Indirect addr.

OPTION_REG

STATUS

PCLATH
INTCON

SSPCON2

SSPADD

SSPSTAT

ADRESL

General
Purpose
Register

32 Bytes

accesses

70h-7Fh

Bank 1

PCL

FSR
TRISA
TRISB
TRISC

PIE1
PIE2

PCON

PR2

Address

(*)

File

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

BFh
C0h

EFh
F0h

FFh

Indirect addr.

TMR0

PCL

STATUS

FSR

PORTB

PCLATH
INTCON

EEDATA

EEADR

EEDATH

EEADRH

accesses

20h-7Fh

accesses

70h-7Fh

Bank 2

Address

(*)

File

100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah

10Bh
10Ch
10Dh
10Eh
10Fh
110 h

120h

16Fh
170h

17Fh

Indirect addr.

OPTION_REG

PCL

STATUS

FSR

TRISB

PCLATH

INTCON
EECON1
EECON2

Reserved
Reserved

accesses

A0h - BFh

accesses

70h-7Fh

Bank 3

(1)

(1)

File

Address

(*)

180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h

1A0h

1BFh
1C0h

1EFh
1F0h

1FFh

Unimplemented data memory locations, read as '0'.

* Not a physical register.

Note 1: These registers are reserved; maintain these registers clear.

DS30221C-page 8 © 2006 Microchip Technology Inc.

PIC16F872

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.

The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

(2)

00h

01h TMR0 Timer0 Module Register xxxx xxxx 35, 93

02h

03h

04h

05h PORTA

06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31, 93

07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 33, 93

08h — Unimplemented — —

09h — Unimplemented — —

0Ah

0Bh

0Ch PIR1 (3) ADIF (3) (3) SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 16, 93

0Dh PIR2

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 40, 94

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 40, 94

10h T1CON

11h TMR2 Timer2 Module Register 0000 0000 43, 94

12h T2CON

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 55, 94

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 53, 94

15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx 45, 94

16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx 45, 94

17h CCP1CON

18h — Unimplemented — —

19h — Unimplemented — —

1Ah — Unimplemented — —

1Bh — Unimplemented — —

1Ch — Unimplemented — —

1Dh — Unimplemented — —

1Eh ADRESH A/D Result Register High Byte xxxx xxxx 84, 94

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are

INDF Addressing this location uses contents of FSR to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12, 93

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx 21, 93

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.

(not a physical register)

— — PORTA Data Latch when written: PORTA pins when read --0x 0000 29, 93

— (3) —EEIFBCLIF— — (3) -r-0 0--r 18, 93

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 39, 94

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 43, 94

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 45, 94

—ADON

DONE

Value on:

POR,

BOR

0000 0000 21, 93

0000 00-0 79, 94

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© 2006 Microchip Technology Inc. DS30221C-page 9

PIC16F872

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(2)

80h

81h OPTION_REG RBPU

82h

83h

84h

85h TRISA

86h TRISB PORTB Data Direction Register 1111 1111 31, 94

87h TRISC PORTC Data Direction Register 1111 1111 33, 94

88h — Unimplemented — —

89h — Unimplemented — —

8Ah

8Bh

8Ch PIE1 (3) ADIE (3) (3) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 15, 94

8Dh PIE2

8Eh PCON

8Fh — Unimplemented — —

90h — Unimplemented — —

91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 54, 94

92h PR2 Timer2 Period Register 1111 1111 43, 94

93h SSPADD Synchronous Serial Port (I

94h SSPSTAT SMP CKE D/A

95h — Unimplemented — —

96h — Unimplemented — —

97h — Unimplemented — —

95h — Unimplemented — —

95h — Unimplemented — —

9Ah — Unimplemented — —

9Bh — Unimplemented — —

9Ch — Unimplemented — —

9Dh — Unimplemented — —

9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 84, 94

9Fh ADCON1 ADFM

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are

INDF Addressing this location uses contents of FSR to address data memory

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12, 93

(2)

FSR Indirect data memory address pointer xxxx xxxx 21, 93

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93

Shaded locations are unimplemented, read as ‘0’.

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.

(not a physical register)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13, 94

— — PORTA Data Direction Register --11 1111 29, 94

— (3) —EEIEBCLIE— — (3) -r-0 0--r 17, 94

— — — — — —PORBOR ---- --qq 19, 94

2

C mode) Address Register 0000 0000 58, 94

PSR/WUA BF 0000 0000 52, 94

— — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 80, 94

Value on:

POR,

BOR

0000 0000 21, 93

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DS30221C-page 10 © 2006 Microchip Technology Inc.

PIC16F872

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

POR,

BOR

Bank 2

Value on:

(2)

100h

INDF Addressing this location uses contents of FSR to address data memory

0000 0000 21, 93

(not a physical register)

101h TMR0 Timer0 Module Register xxxx xxxx 35, 93

(2)

102h

103h

104h

PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12, 93

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx 21, 93

105h — Unimplemented — —

106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31, 93

107h — Unimplemented — —

108h — Unimplemented — —

109h — Unimplemented — —

(1,2)

10Ah

10Bh

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93

10Ch EEDATA EEPROM Data Register Low Byte xxxx xxxx 23, 94

10Dh EEADR EEPROM Address Register Low Byte xxxx xxxx 23, 94

10Eh EEDATH

10Fh EEADRH

— — EEPROM Data Register High Byte xxxx xxxx 23, 94

— — — EEPROM Address Register High Byte xxxx xxxx 23, 94

Bank 3

(2)

180h

INDF Addressing this location uses contents of FSR to address data memory

0000 0000 21, 93

(not a physical register)

181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13, 94

(2)

182h

183h

184h

PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12, 93

(2)

FSR Indirect Data Memory Address Pointer xxxx xxxx 21, 93

185h — Unimplemented — —

186h TRISB PORTB Data Direction Register 1111 1111 31, 94

187h — Unimplemented — —

188h — Unimplemented — —

189h — Unimplemented — —

(1,2)

18Ah

18Bh

18Ch EECON1 EEPGD

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93

— — — WRERR WREN WR RD x--- x000 24, 94

18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- 23, 94

18Eh — Reserved; maintain clear 0000 0000 —

18Fh — Reserved; maintain clear 0000 0000 —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.

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© 2006 Microchip Technology Inc. DS30221C-page 11

PIC16F872

2.2.2.1 STATUS Register

The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.

The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any status bits, see the
“Instruction Set Summary."

Note: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub­traction. See the SUBLW and SUBWF
instructions for examples.

REGISTER 2-1: STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)

bit 6:5 RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

(for borrow

1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow

the polarity is reversed)

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.

PD ZDCC

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS30221C-page 12 © 2006 Microchip Technology Inc.

PIC16F872

2.2.2.2 OPTION_REG Register

The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign­able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to
the Watchdog Timer.

REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU

bit 6 INTEDG: Interrupt Edge Select bit

bit 5 T0CS: TMR0 Clock Source Select bit

bit 4 T0SE: TMR0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS2:PS0: Prescaler Rate Select bits

: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

Bit Value TMR0 Rate WDT Rate

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3

in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper oper­ation of the device

© 2006 Microchip Technology Inc. DS30221C-page 13

PIC16F872

2.2.2.3 INTCON Register

The INTCON Register is a readable and writable regis­ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

REGISTER 2-3: INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIETMR0IEINTE RBIETMR0IFINTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set

the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).

0 = None of the RB7:RB4 pins have changed state

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS30221C-page 14 © 2006 Microchip Technology Inc.

PIC16F872

2.2.2.4 PIE1 Register

The PIE1 register contains the individual enable bits for
the peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

REGISTER 2-4: PIE1 REGISTER (ADDRESS: 8Ch)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

reserved ADIE reserved reserved SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 Reserved: Always maintain these bits clear

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt

bit 5-4 Reserved: Always maintain these bits clear

bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt
0 = Disables the SSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

© 2006 Microchip Technology Inc. DS30221C-page 15

PIC16F872

2.2.2.5 PIR1 Register

The PIR1 register contains the individual flag bits for
the peripheral interrupts.

REGISTER 2-5: PIR1 REGISTER (ADDRESS: 0Ch)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

reserved ADIF reserved reserved SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 Reserved: Always maintain these bits clear

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed
0 = The A/D conversion is not complete

bit 5-4 Reserved: Always maintain these bits clear

bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag

1 = The SSP interrupt condition has occurred, and must be cleared in software before returning

from the Interrupt Service Routine. The conditions that will set this bit are:

• SPI

- A transmission/reception has taken place

2

• I

C Slave

- A transmission/reception has taken place

2

•I

C Master

- A transmission/reception has taken place

- The initiated START condition was completed by the SSP module

- The initiated STOP condition was completed by the SSP module

- The initiated Restart condition was completed by the SSP module

- The initiated Acknowledge condition was completed by the SSP module

- A START condition occurred while the SSP module was idle (multi-master system)

- A STOP condition occurred while the SSP module was idle (multi-master system)

0 = No SSP interrupt condition has occurred

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode:

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

Unused in this mode

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt bits are clear prior to enabling an
interrupt.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS30221C-page 16 © 2006 Microchip Technology Inc.

2.2.2.6 PIE2 Register

The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, and the EEPROM write operation interrupt.

REGISTER 2-6: PIE2 REGISTER (ADDRESS: 8Dh)

U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0

— reserved — EEIE BCLIE — — reserved

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6 Reserved: Always maintain this bit clear

bit 5 Unimplemented: Read as '0'

bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit

1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt

bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enable bus collision interrupt
0 = Disable bus collision interrupt

bit 2-1 Unimplemented: Read as '0'

bit 0 Reserved: Always maintain this bit clear

PIC16F872

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

© 2006 Microchip Technology Inc. DS30221C-page 17

PIC16F872

2.2.2.7 PIR2 Register

The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.

.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

REGISTER 2-7: PIR2 REGISTER (ADDRESS: 0Dh)

U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0

— reserved — EEIF BCLIF — — reserved

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6 Reserved: Always maintain this bit clear

bit 5 Unimplemented: Read as '0'

bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred in the SSP, when configured for I
0 = No bus collision has occurred

bit 2-1 Unimplemented: Read as '0'

bit 0 Reserved: Always maintain this bit clear

2

C Master mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS30221C-page 18 © 2006 Microchip Technology Inc.

PIC16F872

2.2.2.8 PCON Register

The Power Control (PCON) Register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR

Reset.

Note: BOR is unknown on POR. It must be set by

the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurred. The BOR status
bit is a don’t care and is not predictable if
the brown-out circuit is disabled (by clear­ing the BODEN bit in the Configuration
Word).

REGISTER 2-8: PCON REGISTER (ADDRESS: 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1

— — — — — —PORBOR

bit 7 bit 0

bit 7-2 Unimplemented: Read as '0'

bit 1 POR

bit 0 BOR

: Power-on Reset Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

© 2006 Microchip Technology Inc. DS30221C-page 19

PIC16F872

2.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-3 shows the two situations
for the loading of the PC. The upper example in the fig­ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig­ure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PC

PCLATH<4:0>

5

PCLATH

PCH PCL

12 11 10 0

PC

2

87

PCLATH<4:3>

PCLATH

11

2.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
Application Note,
(AN556).

“Implementing a Table Read"

8

Instruction with
PCL as
Destination

ALU

GOTO,CALL

Opcode <10:0>

2.3.2 STACK

The PIC16FXXX family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an inter­rupt causes a branch. The stack is POPed in the event
of a RETURN, RETLW or a RETFIE instruction execu­tion. PCLATH is not affected by a PUSH or POP oper­ation.

The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an inter­rupt address.

2.4 Program Memory Paging

All PIC16FXXX devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. Since the PIC16F872 has only 2K
words of program memory or one page, additional code
is not required to ensure that the correct page is
selected before a CALL or GOTO instruction is exe­cuted. The PCLATH<4:3> bits should always be main­tained as zeros. If a return from a CALL instruction (or
interrupt) is executed, the entire 13-bit PC is popped off
the stack. Therefore, manipulation of the
PCLATH<4:3> bits are not required for the return
instructions (which POPs the address from the stack).

Note: The contents of the PCLATH register are

unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis­ter for any subsequent subroutine calls or
GOTO instructions.

DS30221C-page 20 © 2006 Microchip Technology Inc.

PIC16F872

2.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF reg­ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg­ister, FSR. Reading the INDF register itself indirectly
(FSR = '0'), will read 00h. Writing to the INDF register
indirectly results in a no operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-4.

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING

RP1:RP0 6

Bank Select Location Select

From Opcode

0

00 01 10 11

00h

80h

100h

A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

MOVLW 0x20 ;initialize pointer

NEXT CLRF INDF ;clear INDF register

CONTINUE

MOVWF FSR ;to RAM

INCF FSR,F ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next

: ;yes continue

Indirect AddressingDirect Addressing

IRP FSR Register

Bank Select

180h

7

0

Location Select

Data

(1)

Memory

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Note 1: For register file map detail, see Figure 2-2.

FFh

17Fh

1FFh

© 2006 Microchip Technology Inc. DS30221C-page 21

PIC16F872

NOTES:

DS30221C-page 22 © 2006 Microchip Technology Inc.

3.0 DATA EEPROM AND FLASH PROGRAM MEMORY

The Data EEPROM and FLASH Program Memory are
readable and writable during normal operation over the
entire V
gle byte for Data EEPROM memory and a single word
for Program memory. A write operation causes an
erase-then-write operation to take place on the speci­fied byte or word. A bulk erase operation may not be
issued from user code (which includes removing code
protection).

Access to program memory allows for checksum calcu­lation. The values written to Program memory do not
need to be valid instructions. Therefore, numbers of up
to 14 bits can be stored in memory for use as calibra­tion parameters, serial numbers, packed 7-bit ASCII,
etc. Executing a program memory location, containing
data that forms an invalid instruction, results in the exe­cution of a NOP instruction.

The EEPROM Data memory is rated for high erase/
write cycles (specification #D120). The FLASH Pro­gram memory is rated much lower (specification
#D130) because EEPROM Data memory can be used
to store frequently updated values. An on-chip timer
controls the write time and it will vary with voltage and
temperature, as well as from chip to chip. Please refer
to the specifications for exact limits (specifications
#D122 and #D133).

A byte or word write automatically erases the location
and writes the new value (erase before write). Writing
to EEPROM Data memory does not impact the opera­tion of the device. Writing to Program memory will
cease the execution of instructions until the write is
complete. The program memory cannot be accessed
during the write. During the write operation, the oscilla­tor continues to run, the peripherals continue to func­tion and interrupt events will be detected and
essentially “queued” until the write is complete. When
the write completes, the next instruction in the pipeline
is executed and the branch to the interrupt vector will
take place if the interrupt is enabled and occurred dur­ing the write.

Read a

DD range. These operations take place on a sin-

PIC16F872

© 2006 Microchip Technology Inc. DS30221C-page 23

PIC16F872

Write operations have two control bits, WR and WREN,
and two status bits, WRERR and EEIF. The WREN bit
is used to enable or disable the write operation. When
WREN is clear, the write operation will be disabled.
Therefore, the WREN bit must be set before executing
a write operation. The WR bit is used to initiate the write
operation. It also is automatically cleared at the end of
the write operation. The interrupt flag EEIF (located in
register PIR2) is used to determine when the memory
write completes. This flag must be cleared in software
before setting the WR bit. For EEPROM Data memory,
once the WREN bit and the WR bit have been set, the
desired memory address in EEADR will be erased fol­lowed by a write of the data in EEDATA. This operation
takes place in parallel with the microcontroller continu­ing to execute normally. When the write is complete,
the EEIF flag bit will be set. For program memory, once
the WREN bit and the WR bit have been set, the micro­controller will cease to execute instructions. The

desired memory location pointed to by
EEADRH:EEADR will be erased. Then the data value
in EEDATH:EEDATA will be programmed. When com­plete, the EEIF flag bit will be set and the microcontrol­ler will continue to execute code.

The WRERR bit is used to indicate when the device
has been RESET during a write operation. WRERR
should be cleared after Power-on Reset. Thereafter, it
should be checked on any other RESET. The WRERR
bit is set when a write operation is interrupted by a

Reset or a WDT Time-out Reset during normal

MCLR
operation. In these situations, following a RESET, the
user should check the WRERR bit and rewrite the
memory location if set. The contents of the data regis­ters, address registers and EEPGD bit are not affected
by either MCLR
normal operation.

Reset or WDT Time-out Reset during

REGISTER 3-1: EECON1 REGISTER (ADDRESS 18Ch)

R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD — — — WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Program/Data EEPROM Select bit

1 = Accesses Program memory
0 = Accesses data memory

(This bit cannot be changed while a read or write operation is in progress.)

bit 6-4 Unimplemented: Read as '0'

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated

(any MCLR

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles
0 = Inhibits write to the EEPROM

bit 1 WR: Write Control bit

1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not

cleared) in software.

0 = Does not initiate an EEPROM read

Legend:

S = Settable bit R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR

’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

Reset or any WDT Reset during normal operation)

DS30221C-page 24 © 2006 Microchip Technology Inc.

PIC16F872

3.2 Reading the EEPROM Data Memory

Reading EEPROM Data memory only requires that the
desired address to access be written to the EEADR
register and clear the EEPGD bit. After the RD bit is set,
data will be available in the EEDATA register on the
very next instruction cycle. EEDATA will hold this value
until another read operation is initiated or until it is writ­ten by firmware.

The steps to reading the EEPROM Data Memory are:

1. Write the address to EEDATA. Make sure that

the address is not larger than the memory size
of the device.

2. Clear the EEPGD bit to point to EEPROM Data

memory.

3. Set the RD bit to start the read operation.

4. Read the data from the EEDATA register.

EXAMPLE 3-1: EEPROM DATA READ

BSF STATUS, RP1 ;
BCF STATUS, RP0 ;Bank 2
MOVF ADDR, W ;Write address
MOVWF EEADR ;to read from
BSF STATUS, RP0 ;Bank 3
BCF EECON1, EEPGD ;Point to Data memory
BSF EECON1, RD ;Start read operation
BCF STATUS, RP0 ;Bank 2
MOVF EEDATA, W ;W = EEDATA

3.3 Writing to the EEPROM Data Memory

There are many steps in writing to the EEPROM Data
memory. Both address and data values must be written
to the SFRs. The EEPGD bit must be cleared and the
WREN bit must be set to enable writes. The WREN bit

should be kept clear at all times, except when writing to
the EEPROM Data. The WR bit can only be set if the
WREN bit was set in a previous operation, i.e., they
both cannot be set in the same operation. The WREN
bit should then be cleared by firmware after the write.
Clearing the WREN bit before the write actually com­pletes will not terminate the write in progress.

Writes to EEPROM Data memory must also be pref­aced with a special sequence of instructions that pre­vent inadvertent write operations. This is a sequence of
five instructions that must be executed without interrup­tion for each byte written.

The steps to write to program memory are:

1. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.

2. Write the 8-bit data value to be programmed in
the EEDATA registers.

3. Clear the EEPGD bit to point to EEPROM Data
memory.

4. Set the WREN bit to enable program operations.

5. Disable interrupts (if enabled).

6. Execute the special five instruction sequence:

• Write 55h to EECON2 in two steps (first to W,

then to EECON2)

• Write AAh to EECON2 in two steps (first to

W, then to EECON2)

• Set the WR bit

7. Enable interrupts (if using interrupts).

8. Clear the WREN bit to disable program operations.

9. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware). Firmware
may check for EEIF to be set or WR to clear to
indicate end of program cycle.

EXAMPLE 3-2: EEPROM DATA WRITE

BSF STATUS, RP1 ;
BCF STATUS, RP0 ;Bank 2
MOVF ADDR, W ;Address to
MOVWF EEADR ;write to
MOVF VALUE, W ;Data to
MOVWF EEDATA ;write
BSF STATUS, RP0 ;Bank 3
BCF EECON1, EEPGD ;Point to Data memory

;Only disable interrupts

;otherwise discard

;Only enable interrupts

;otherwise discard

© 2006 Microchip Technology Inc. DS30221C-page 25

BSF EECON1, WREN ;Enable writes

BCF INTCON, GIE ;if already enabled,

MOVLW 0x55 ;Write 55h to
MOVWF EECON2 ;EECON2
MOVLW 0xAA ;Write AAh to
MOVWF EECON2 ;EECON2

Required

Sequence

BSF EECON1, WR ;Start write operation

BSF INTCON, GIE ;if using interrupts,

BCF EECON1, WREN ;Disable writes

PIC16F872

3.4 Reading the FLASH Program Memory

Reading FLASH Program memory is much like that of
EEPROM Data memory, only two NOP instructions
must be inserted after the RD bit is set. These two
instruction cycles that the NOP instructions execute will
be used by the microcontroller to read the data out of
program memory and insert the value into the
EEDATH:EEDATA registers. Data will be available fol­lowing the second NOP instruction. EEDATH and
EEDATA will hold their value until another read opera­tion is initiated, or until they are written by firmware.

EXAMPLE 3-3: FLASH PROGRAM READ

BSF STATUS, RP1 ;

BCF STATUS, RP0 ;Bank 2

MOVF ADDRL, W ;Write the

MOVWF EEADR ;address bytes

MOVF ADDRH,W ;for the desired

MOVWF EEADRH ;address to read

BSF STATUS, RP0 ;Bank 3

BSF EECON1, EEPGD ;Point to Program memory

BSF EECON1, RD ;Start read operation

NOP ;Required two NOPs

NOP ;

Required

Sequence

BCF STATUS, RP0 ;Bank 2

MOVF EEDATA, W ;DATAL = EEDATA

MOVWF DATAL ;

MOVF EEDATH,W ;DATAH = EEDATH

MOVWF DATAH ;

The steps to reading the FLASH Program Memory are:

1. Write the address to EEADRH:EEADR. Make
sure that the address is not larger than the mem­ory size of the device.

2. Set the EEPGD bit to point to FLASH Program
memory.

3. Set the RD bit to start the read operation.

4. Execute two NOP instructions to allow the micro­controller to read out of program memory.

5. Read the data from the EEDATH:EEDATA
registers.

3.5 Writing to the FLASH Program Memory

Writing to FLASH Program memory is unique in that the
microcontroller does not execute instructions while pro­gramming is taking place. The oscillator continues to
run and all peripherals continue to operate and queue
interrupts, if enabled. Once the write operation com­pletes (specification #D133), the processor begins exe­cuting code from where it left off. The other important
difference when writing to FLASH Program memory is
that the WRT configuration bit, when clear, prevents
any writes to program memory (see Table 3-1).

Just like EEPROM Data memory, there are many steps
in writing to the FLASH Program memory. Both
address and data values must be written to the SFRs.
The EEPGD bit must be set and the WREN bit must be
set to enable writes. The WREN bit should be kept

clear at all times, except when writing to the FLASH
Program memory. The WR bit can only be set if the
WREN bit was set in a previous operation, i.e., they
both cannot be set in the same operation. The WREN
bit should then be cleared by firmware after the write.
Clearing the WREN bit before the write actually com­pletes will not terminate the write in progress.

Writes to program memory must also be prefaced with
a special sequence of instructions that prevent inad­vertent write operations. This is a sequence of five
instructions that must be executed without interruption
for each byte written. These instructions must then be
followed by two NOP instructions to allow the microcon­troller to setup for the write operation. Once the write is
complete, the execution of instructions starts with the
instruction after the second NOP.

DS30221C-page 26 © 2006 Microchip Technology Inc.

PIC16F872

The steps to write to program memory are:

1. Write the address to EEADRH:EEADR. Make
sure that the address is not larger than the mem­ory size of the device.

2. Write the 14-bit data value to be programmed in
the EEDATH:EEDATA registers.

3. Set the EEPGD bit to point to FLASH Program
memory.

4. Set the WREN bit to enable program operations.

5. Disable interrupts (if enabled).

6. Execute the special five instruction sequence:

• Write 55h to EECON2 in two steps (first to W,

then to EECON2)

• Write AAh to EECON2 in two steps (first to W,
then to EECON2)

• Set the WR bit

7. Execute two NOP instructions to allow the micro­controller to setup for write operation.

8. Enable interrupts (if using interrupts).

9. Clear the WREN bit to disable program
operations.

At the completion of the write cycle, the WR bit is
cleared and the EEIF interrupt flag bit is set. (EEIF
must be cleared by firmware). Since the microcontroller
does not execute instructions during the write cycle, the
firmware does not necessarily have to check either
EEIF or WR to determine if the write had finished.

EXAMPLE 3-4: FLASH PROGRAM WRITE

BSF STATUS, RP1 ;
BCF STATUS, RP0 ;Bank 2
MOVF ADDRL, W ;Write address
MOVWF EEADR ;of desired
MOVF ADDRH, W ;program memory
MOVWF EEADRH ;location
MOVF VALUEL, W ;Write value to
MOVWF EEDATA ;program at
MOVF VALUEH, W ;desired memory
MOVWF EEDATH ;location
BSF STATUS, RP0 ;Bank 3
BSF EECON1, EEPGD ;Point to Program memory
BSF EECON1, WREN ;Enable writes

;Only disable interrupts

;otherwise discard

;Only enable interrupts

;otherwise discard

BCF INTCON, GIE ;if already enabled,

MOVLW 0x55 ;Write 55h to
MOVWF EECON2 ;EECON2
MOVLW 0xAA ;Write AAh to
MOVWF EECON2 ;EECON2
BSF EECON1, WR ;Start write operation

Required

Sequence

NOP ;Two NOPs to allow micro
NOP ;to setup for write

BSF INTCON, GIE ;if using interrupts,

BCF EECON1, WREN ;Disable writes

3.6 Write Verify

The PIC16F87X devices do not automatically verify the
value written during a write operation. Depending on
the application, good programming practice may dic­tate that the value written to memory be verified against
the original value. This should be used in applications
where excessive writes can stress bits near the speci­fied endurance limits.

3.7 Protection Against Spurious Writes

There are conditions when the device may not want to
write to the EEPROM Data memory or FLASH program
memory. To protect against these spurious write condi­tions various mechanisms have been built into the
device. On power-up, the WREN bit is cleared and the
Power-up Timer (if enabled) prevents writes.

The write initiate sequence and the WREN bit together
help prevent any accidental writes during brown-out,
power glitches or firmware malfunction.

© 2006 Microchip Technology Inc. DS30221C-page 27

PIC16F872

3.8 Operation While Code Protected

ent effects on writing to program memory. Table 4-1
shows the effect of the code protect bits and the WRT

The PIC16F872 has two code protect mechanisms,
one bit for EEPROM Data memory and two bits for
FLASH Program memory. Data can be read and written
to the EEPROM Data memory regardless of the state
of the code protection bit, CPD. When code protection
is enabled, CPD cleared, external access via ICSP is
disabled regardless of the state of the program memory
code protect bits. This prevents the contents of
EEPROM Data memory from being read out of the
device.

The state of the program memory code protect bits,
CP0 and CP1, do not affect the execution of instruc­tions out of program memory. The PIC16F872 can
always read the values in program memory, regardless
of the state of the code protect bits. However, the state
of the code protect bits and the WRT bit will have differ-

bit on program memory.

Once code protection has been enabled for either
EEPROM Data memory or FLASH Program memory,
only a full erase of the entire device will disable code
protection.

3.9 FLASH Program Memory Write Protection

The configuration word contains a bit that write protects
the FLASH Program memory called WRT. This bit can
only be accessed when programming the device via
ICSP. Once write protection is enabled, only an erase
of the entire device will disable it. When enabled, write
protection prevents any writes to FLASH Program
memory. Write protection does not affect program
memory reads.

TABLE 3-1: READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY

Configuration Bits

Memory Location

CP1 CP0 WRT

000 All program memory Yes No No No

001 All program memory Yes Yes No No

110 All program memory Yes No Yes Yes

111 All program memory Yes Yes Yes Yes

Internal

Read

Internal

Write

ICSP Read ICSP Write

TABLE 3-2: REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh, 8Bh,
10Bh, 18Bh

10Dh EEADR EEPROM Address Register, Low Byte xxxx xxxx uuuu uuuu

10Fh EEADRH

10Ch EEDATA EEPROM Data Register, Low Byte xxxx xxxx uuuu uuuu

10Eh EEDATH

18Ch EECON1 EEPGD

18Dh EECON2 EEPROM Control Register2 (not a physical register) — —

8Dh PIE2

0Dh PIR2

Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'.

Note 1: These bits are reserved; always maintain these bits clear.

INTCON GIE PEIE

— — — EEPROM Address, High Byte xxxx xxxx uuuu uuuu

— — EEPROM Data Register, High Byte xxxx xxxx uuuu uuuu

— (1) —EEIEBCLIE — — (1) -r-0 0--r -r-0 0--r

— (1) —EEIFBCLIF — — (1) -r-0 0--r -r-0 0--r

Shaded cells are not used during FLASH/EEPROM access.

TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

— — — WRERR WREN WR RD x--- x000 x--- u000

Value on:

POR,

BOR

Value on
all other
RESETS

DS30221C-page 28 © 2006 Microchip Technology Inc.