MICROCHIP PIC16F84A Technical data

PIC16F84A

Data Sheet

18-pin Enhanced FLASH/EEPROM

8-bit Microcontroller

 2001 Microchip Technology Inc. DS35007B

Note the following details of the code protection feature on PICmicro® MCUs.

• The PICmicro family meets the specifications contained in the Microchip Data Sheet.

• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today , when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable”.

• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features o f our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks

The Microchip name and lo go, the Microc hip logo , PIC, PICmic ro, PICMASTER, PICSTART, PRO MATE, K

EELOQ, SEEVAL,

MPLAB and The Embedded Control Solutions Company are registered trademar ks of Micr ochip Technology Incorporated in t he U.S.A. and other countries.

Total Endurance, ICSP, In-Circuit Serial Programming, Filter-

Flex

ROM,

fuzzy

Lab, MXDEV, microID,

LAB, MPASM, MPLINK, MPLIB, PICC, PICDEM, PICDEM.net, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR, Select Mode and microPort are trademarks of Microchip Technology Incorporated in the U.S.A.

Serialized Quick T erm Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system certification for its worldwid e head qu art ers, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.

8-bit MCUs, KEELOQ

code hoppin g

DS35007B - page ii  2001 Microchip Technology Inc.

PIC16F84A

18-pin Enhanced FLASH/EEPROM 8-Bit Microcontroller

High Performance RISC CPU Features:

• Only 35 single word instructions to learn

• All instructions single-cycle except for program branches which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• 1024 words of program memory

• 68 bytes of Data RAM

• 64 bytes of Data EEPROM

• 14-bit wide instruction words

• 8-bit wide data bytes

• 15 Special Function Hardware registers

• Eight-level deep hardware stack

• Direct, indirect and relative addressing modes

• Four interrupt sources:

- External RB0/INT pin

- TMR0 timer overflow

- PORTB<7:4> interrupt-on-change

- Data EEPROM write complete

Peripheral Features:

• 13 I/O pins with individual direction control

• High current sink/source for direct LED drive

- 25 mA sink max. per pin

- 25 mA source max. per pin

• TMR0: 8-bit timer/counter with 8-bit programmable prescaler

Pin Diagrams

PDIP, SOIC

RA2 RA3

RA4/T0CKI

MCLR

VSS

RB0/INT

RB1 RB2 RB3

SSOP

RA2 RA3

RA4/T0CKI

MCLR

VSS VSS

RB0/INT

RB1 RB2 RB3

•

1 2 3 4 5 6 7 8 9

•

1 2 3 4 5 6 7 8 9 10

PIC16F84A

18 17 16 15 14 13 12 11 10

20 19 18 17 16 15 14 13 12 11

RA1 RA0 OSC1/CLKIN OSC2/CLKOUT V

RB7 RB6 RB5 RB4

RA1 RA0 OSC1/CLKIN OSC2/CLKOUT V

VDD RB7 RB6 RB5 RB4

Special Microcontroller Features:

• 10,000 erase/write cycles Program memory typical

• 10,000,000 typical erase/write cy cle s EEPROM Data memory typical

• EEPROM Data Retention > 40 years

• In-Circuit Serial Programming™ (ICSP™) - via two pins

• Power-on Reset (POR), Power-up T imer (PWRT), Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own On-Chip RC Oscillator for reliable operation

Enhanced

FLASH

CMOS Enhanced

FLASH/EEPROM

Technology:

• Low power, high speed technology

• Fully static design

• Wide operating voltage range:

- Commercial: 2.0V to 5.5V

- Industrial: 2.0V to 5.5V

• Low power consumption:

- < 2 mA typical @ 5V, 4 MHz

-15 µA typical @ 2V, 32 kHz

- < 0.5 µA typical standby curr ent @ 2V

• Code protection

• Power saving SLEEP mode

• Selectable oscillator options

 2001 Microchip Technology Inc. DS35007B-page 1

PIC16F84A

Table of Contents

1.0 Device Overview..........................................................................................................................................................................3

2.0 Memory Organization...................................................................................................................................................................5

3.0 Data EEPROM Memory.............................................. ............ ............. ............. ............ ..................... ............. ............ ............. ..13

4.0 I/O Ports.............................. ............. ............ ............. ............ ............. ............. ......... ............ ............ ............. ............ ............. .... 15

5.0 Timer0 Module ........................................................................................................................................................................... 19

6.0 Special Features of the CPU......................................................................................................................................................21

7.0 Instruction Set Summary............................................................................................................................................................35

8.0 Development Support.................................................................................................................................................................43

9.0 Electrical Characteristics............................................................................................................................................................49

10.0 DC/AC Characteristic Graphs ....................................................................................................................................................61

11.0 Packaging Information...................... ......................................................................................................... ............ ............. ........71

Appendix A: Revision History ..............................................................................................................................................................75

Appendix B: Conversion Considerations.............. .................................................................................................................... ............76

Appendix C: Migration from Baseline to Mid-Range Devices..............................................................................................................78

Index ....................................................................................................................................................................................................79

On-Line Support........................ ................................................................. ....................... ............. ......................................................83

Reader Response................................................................................................................................................................................84

PIC16F84A Product Identification System...........................................................................................................................................85

TO OUR VALUED CUSTOMERS

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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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ature number) you are using.

Customer Notification System

DS35007B-page 2  2001 Microchip Technology Inc.

PIC16F84A

1.0 DEVICE OVERVIEW

This document contains device specific information for the operation of the PIC16F84A device. Additional

information may be found in the PICmicro™ MidRange Reference Manual, (DS33023), which may be downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.

The PIC16F84A belo ngs to t he mid-range family o f th e PICmicro

the device is shown in Figure 1-1.

FIGURE 1-1: PIC16F84A BLOCK DIAGRAM

microcontroller devices. A block diagram of

Program Counter

FLASH

Program

Memory 1K x 14

Program

Bus

Instruction Register

8 Level Stack

(13-bit)

Data Bus

File Registers

68 x 8

Addr Mux

The program memory contains 1K words, which translates to 1024 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 68 bytes. Data EEPROM is 64 bytes.

There are also 13 I/O pins that are user-configured on a pin-to-pin basis . Some pins are m ultiplexed with other device functions. These functions include:

• External interrupt

• Change on PORTB interrupt

• Timer0 clock input Table 1-1 details the pinout of the device with descrip-

tions and details for each pin.

EEPROM Data Memory

RAM

EEDATA

RAM Addr

EEPROM

Data Memory

64 x 8

EEADR

Instruction

Decode &

Control

Timing

Generation

OSC2/CLKOUT

OSC1/CLKIN

Direct Addr

Power-up

Timer

Oscillator

Start-up Time r

Power-on

Reset

Watchdog

Timer

MCLR

VDD, VSS

FSR reg

STATUS reg

ALU

W reg

MUX

Indirect

Addr

TMR0

RA4/T0CKI

I/O Ports

RA3:RA0

RB7:RB1

RB0/INT

 2001 Microchip Technology Inc. DS35007B-page 3

PIC16F84A

TABLE 1-1: PIC16F84A PINOUT DESCRIPTION

Pin Name

OSC1/CLKIN 16 16 18 I ST/CMOS OSC2/CLKOUT 15 15 19 O — Oscillator crystal output. Connects to crystal or

MCLR

RA0 17 17 19 I/O TTL RA1 18 18 20 I/O TTL RA2 1 1 1 I/O TTL RA3 2 2 2 I/O TTL RA4/T0CKI 3 3 3 I/O ST Can also be selected to be the clo ck input to the

RB0/INT 6 6 7 I/O TTL/ST

RB1 7 7 8 I/O TTL RB2 8 8 9 I/O TTL RB3 9 9 10 I/O TTL RB4 10 10 11 I/O TTL Interrupt-on-change pin. RB5 11 11 12 I/O TTL Interrupt-on-change pin. RB6 12 12 13 I/O TTL/ST

RB7 13 13 14 I/O TTL/ST

SS 5 5 5,6 P — Ground reference for logic and I/O pins.

DD 14 14 15,16 P — Positive supply for logic and I/O pins.

V Legend: I= input O = Output I/O = Input/Output P = Power

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

PDIP

SOIC

No.

4 4 4 I/P ST Master Clear (Reset) input/programming voltage

— = Not used TTL = TTL input ST = Schmitt Trigger input

No.

SSOP

No.

I/O/P Type

Buffer

Type

Description

(3)

Oscillator crystal input /external clock source input.

resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.

input. This pin is an activ e low RESET to the de vice. PORTA is a bi-directional I/O port.

TMR0 timer/counter. Output is open drain type.

PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.

(1)

(2)

RB0/INT can also be selected as an external interrupt pin.

Interrupt-on-change pin. Serial programming clock.

Interrupt-on-change pin. Serial programming data.

DS35007B-page 4  2001 Microchip Technology Inc.

PIC16F84A

2.0 MEMORY ORGANIZATION

There are two memory blocks in the PIC16F84A. These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle.

The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that

control the “core” are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module.

The data memory area also contains the data EEPROM memory . This memory is no t directly mapped into the data m emory, but is indirectly m ap ped . T hat is , an indirect address p ointer s pecifies the ad dress of the data EEPROM memory to read/write. The 64 bytes of data EEPROM memory have the address range 0h-3Fh. More details on the EEPROM memory can be found in Section 3.0.

Additional informa tion on devi ce memory m ay be found in the PICmicro™ Mid-Range Reference Manual, (DS33023).

2.1 Program Memory Organization

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK - PIC16F84A

CALL, RETURN RETFIE, RETLW

Peripheral Interrupt Vector

Space

User Memory

PC<12:0>

Stack Level 1

Stack Level 8

RESET Vector

•

0000h

0004h

3FFh

The PIC16FXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16F84A, the first 1K x 14 (0000h-03FFh) are physically imple mented (Fi gure 2-1). Accessing a location above the physically implemented address will cause a wraparound. For example, for locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h, the instruction will be the same.

The RESET vector is at 0000h and the interrupt vector is at 0004h.

1FFFh

 2001 Microchip Technology Inc. DS35007B-page 5

PIC16F84A

2.2 Data Memory Organization

The data memory is par titione d into two areas. T he first is the Special Fu nction Regis ters (SFR) a rea, wh ile th e second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device.

Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are loc at ed i n th e STATU S R egi ste r. Figure 2-2 shows the data memory map organization.

Instructions MOVWF and MOVF can move values from

the W register to any location in the register file (“F”), and vice-versa.

The entire data memory can be accessed either directly using the absolute address o f ea ch regi ste r fil e or indirectly through the File Select Register (FSR) (Section 2.5). Indirect addressing uses the present value of the RP0 bit for acces s into the banked ar eas of data memory.

Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank

1. Each Bank extends up to 7Fh (128 bytes). The first twelve locations of each Bank are reserved for the Special Funct ion Registers. The remain der are General Purpose Registers, implemented as static RAM.

2.2.1 GENERAL PURPOSE REGISTER FILE

FIGURE 2-2: REGISTER FILE MAP -

PIC16F84A

File Address

00h 01h

02h 03h 04h 05h 06h

07h 08h

09h 0Ah 0Bh

0Ch

4Fh

50h

(1)

Indirect addr.

TMR0 OPTION_REG

PCL

STATUS

FSR PORTA PORTB

—

EEDATA

EEADR

PCLATH INTCON

General

Purpose

Registers

(SRAM)

Indirect addr.

STATUS

EECON1

EECON2

PCLATH

INTCON

Mapped

(accesses)

in Bank 0

PCL

FSR TRISA TRISB

—

File Address

(1)

80h 81h

82h 83h 84h 85h 86h

87h 88h 89h

8Ah 8Bh

8Ch

CFh D0h

Each General Purpose Register (GPR) is 8-bits wide and is accessed either dire ctl y o r indirectly through the FSR (Section 2.5).

The GPR addresses in Bank 1 are mapped to addresses in Bank 0. As an ex ample, addressing location 0Ch or 8Ch will access the same GPR.

DS35007B-page 6  2001 Microchip Technology Inc.

7Fh

Unimplemented data memory location, read as ’0’.

Note 1: Not a physical register.

Bank 0

Bank 1

FFh

PIC16F84A

2.3 Special Function Registers

The special function regi sters can be classified into tw o sets, core and peripheral. Those associated with the

The Special Function Registers (Figure 2-2 and Table 2-1) are used by the CPU and Peripheral functions to control the device operation. These

core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specific feature.

registers are static RAM.

TABLE 2-1: SPECIAL FUNCTION REGISTER FILE SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00h INDF Uses contents of FSR to address Data Memory (not a physical register) 01h TMR0 8-bit Real-Time Clock/Counter 02h PCL Low Order 8 bits of the Program Counter (PC) 03h

STATUS

04h FSR Indirect Data Memory Address Pointer 0 05h PORTA

06h PORTB 07h — Unimplemented location, read as '0' — — 08h EEDATA EEPROM Data Register 09h EEADR EEPROM Address Register 0Ah

PCLATH

0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF

Bank 1

80h INDF Uses Contents of FSR to address Data Memory (not a physical register) 81h

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

82h PCL Low order 8 bits of Program Counter (PC) 83h

STATUS

84h FSR Indirect data memory address pointer 0 85h TRISA 86h TRISB PORTB Data Direction Register 87h — Unimplemented location, read as '0' — — 88h EECON1 89h

EECON2 EEPROM Control Register 2 (not a physical register)

0Ah

PCLATH

0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF Legend: x = unknown, u = unchanged. - = unimplemented, read as '0', q = value depends on condition

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents

2: The TO 3: Other (non power-up) RESETS include: external RESET through MCLR 4: On any device RESET, these pins are configured as inputs. 5: This is the value that will be in the port output latch.

(2)

IRP RP1 RP0 TO PD ZDCC

(4)

— — — RA4/T0CKI RA3 RA2 RA1 RA0

(5)

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT

— — — Write Buffer for upper 5 bits of the PC

(2)

IRP RP1 RP0 TO PD ZDCC

— — — PORTA Data Direction Register

— — — EEIF WRERR WREN WR RD

— — — Write buffer for upper 5 bits of the PC

of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> are never transferred to PCLATH.

and PD status bits in the STATUS register are not affected by a MCLR Reset.

and the Watchdog Tim er Reset.

(1)

Value on

Power-on

RESET

---- ---xxxx xxxx 0000 0000

0001 1xxx xxxx xxxx

---x xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

---0 0000 0000 000x

---- ---1111 1111

0000 0000 0001 1xxx

xxxx xxxx

---1 1111 1111 1111

---0 x000

---- ----

---0 0000 0000 000x

Details

on page

11 20 11

16 18

13,14 13,14

11 10

11 16 18

13 14

11 10

 2001 Microchip Technology Inc. DS35007B-page 7

PIC16F84A

2.3.1 STATUS REGISTER

The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory.

As with any register, the STATUS register can be the destination for any instruction. If the STATUS regi ster is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits ar e s et o r c leared according t o d evi ce lo gic . Furthermore, the TO Therefore, the result of an instruction wi th t he STATUS register as destina tio n may be different than intended.

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 7-2), because these instructions do not affect any status bit.

and PD bits are not writable.

Note 1: The IRP and RP1 bits (STATUS<7:6>)

are not used by the PIC16F84A and should be progra mmed as c leared. U se of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products.

2: The C and DC bits operate as a borrow

and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructi ons for examples.

3: When the STATUS register is the

destinati on for an instruct ion that affects the Z, DC or C bits, then the writ e to these three bits is disabled. The specified bit(s) will be updated according to device logic

REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

bit 7-6 Unimplemented: Maintain as ‘0’

bit 5 RP0: Register Bank Select bits (used for direct addressing)

01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF , ADDLW,SUBLW,SUBWF inst ructio ns) (for borr ow, th e pol arity

is reversed)

1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is

reversed)

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

Note: A subtraction is executed by adding the two’s complement of the second operand.

For rotate (RRF, RLF) instructions, this bi t is loaded with eithe r th e h igh or low order bit of the source register.

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS35007B-page 8  2001 Microchip Technology Inc.

PIC16F84A

2.3.2 OPTION REGISTER

The OPTION register is a readable and writable register which con tain s v arious c ontrol bit s to conf igure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB.

Note: When the prescaler is assigned to

the WDT (PSA = ’1’), TMR0 has a 1:1 prescaler assignment.

REGISTER 2-2: OPTION REGISTER (ADDRESS 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RB

bit 6 INTEDG: Interrupt Edge Select bit

bit 5 T0CS: TMR0 Clock Source Select bit

bit 4 T0SE: TMR0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS2:PS0: Prescaler Rate Select bits

PU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

Bit Value TMR0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2001 Microchip Technology Inc. DS35007B-page 9

PIC16F84A

2.3.3 INTCON REGISTER

The INTCON register is a readable and writable register that contains the various enable bits for all interrupt sources.

Note: Interrupt flag bits are se t whe n an in terru pt

condition occurs, regar dless of the sta te of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE EEIE T0IE INTE RBIE T0IF INTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE Write Complete interrupts 0 = Disables the EE Write Complete interrupt

bit 5 T0IE: TMR0 Overflow Interr upt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS35007B-page 10  2001 Microchip Technology Inc.

PIC16F84A

2.4 PCL and PCLATH

The program counter (PC ) sp eci fie s th e a ddre ss of th e instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. If the program counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. All updates to t he PCH reg- ister go through the PCLATH register.

2.4.1 STACK

The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution .

Mid-range devices have an 8 level deep x 13-bit wide hardware s tack. The stack space is not par t of either program or data space and the stack pointer is not readable or writabl e. The PC i s PUSHed onto th e stac k when a CALL instruction is executed or an interrupt causes a branch. The st ac k is POPed in the event of a RETURN, RETLW or a RETFIE instruction ex ecution. PCLATH is not modified wh en th e s tac k i s PU SH ed or POPed.

After the stack has bee n PUSHed eight time s, the ninth push overwrites th e value tha t was stored fro m the firs t push. The tenth pus h ov erwr i tes the se co nd push (and so on).

2.5 Indirect Addressing; INDF and FSR Registers

The INDF register is no t a physical reg ister . Addr essing INDF actually addresse s the regi st er whose ad dress i s contained in the FSR reg ister (FSR is a indirect addressing.

EXAMPLE 2-1: INDIRECT ADDRESSING

• Register file 05 contains the value 10h

• Register file 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF regi ste r w ill ret urn t he v al ue of 10h

• Increment the value of the FSR register by one (FSR = 06)

• A read of the INDF register now will return the value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR ;inc pointer btfss FSR,4 ;all done?

goto NEXT ;NO, clear next CONTINUE : ;YES, continue

pointer

). This is

An effective 9-b it addre ss is obt ained b y con catena ting the 8-bit FSR register and the IRP bit (STATUS<7>), a s shown in Figure 2-3. However, IRP is not used in the PIC16F84A.

 2001 Microchip Technology Inc. DS35007B-page 11

PIC16F84A

FIGURE 2-3: DIRECT/INDIRECT ADDRESSING

Direct Addressing

RP1 RP0 6

(2) (2)

Bank Select Location Select

Note 1: For memory map detail, see Figure 2-2.

2: Maintain as clear for upward compatibility with future products. 3: Not implemented.

From Opcode

Data

(1)

Memory

0IRP7

00 01

00h

0Bh 0Ch

80h

Addresses map back to Bank 0

4Fh 50h

7Fh

(3)

Bank 0 Bank 1

(3)

FFh

Bank Select

Indirect Addressing

(FSR)

Location Select

DS35007B-page 12  2001 Microchip Technology Inc.

PIC16F84A

3.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable during normal operation (full V is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory. These registers are:

• EECON1

• EECON2 (not a physically implemented register)

• EEDA TA

• EEADR EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEPROM location being accessed. PIC16F84A devices have 64 bytes of data EEPROM with an address range from 0h to 3Fh.

DD range). This memory

The EEPROM data memory allows b yte read and write. A byte write automatically erases the location and writes the new data (erase be fore write). The EEPROM data memory is rated fo r high eras e/write c ycles. The write time is controlled by an on-chip timer. The writetime will vary with voltage and temperature as well as from chip to c hip. Pl ease refe r to A C s peci ficat io ns fo r exact limits.

When the device is code protected, the CPU may continue to read and write th e data EEPROM memory. The device programmer can no longer access this memory.

Additional information on the Data EEPROM is available in the PICmicro™ Mid-Range Reference Manual (DS33023).

REGISTER 3-1: EECON1 REGISTER (ADDRESS 88h)

U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

— — — EEIF WRERR WREN WR RD

bit 7 bit 0

bit 7-5 Unimplemented: Read as '0' bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely termina ted

(any MCLR

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles 0 = Inhibits write to the EEPROM

bit 1 WR: Write Control bit

1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not

cleared) in software.

0 = Does not initiate an EEPROM read

Reset or any WDT Reset during normal operation)

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2001 Microchip Technology Inc. DS35007B-page 13

PIC16F84A

3.1 Reading the EEPROM Data Memory

T o read a d ata memory lo cation, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>). The data is available, in the very next cycle, in the EEDATA register; th erefore, it can be read in the next instru ction. EEDATA will hold this valu e until another read or until it is written to by the user (during a write operation).

EXAMPLE 3-1: DATA EEPROM READ

BCF STATUS, RP0 ; Bank 0 MOVLW CONFIG_ADDR ; MOVWF EEADR ; Address to read BSF STATUS, RP0 ; Bank 1 BSF EECON1, RD ; EE Read BCF STATUS, RP0 ; Bank 0 MOVF EEDATA, W ; W = EEDATA

3.2 Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specific sequence to initiate the write for each byte.

Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accident al writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, clearing the WREN bit will not affec t this writ e cycle. The WR bit will be inhibited from being s et unless the WREN bit is set.

At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.

3.3 Write Verify

Depending on the application, good programming practice may dictate that the value written to the Data EEPROM should be verified (Example 3-3) to the desired value to be written. This should be used in applications where an EEPROM bit will be stressed near the specification limit.

Generally , th e EEPROM write failure wil l be a bit whic h was written as a ’0’, but reads back as a ’1’ (due to leakage off the bit).

EXAMPLE 3-2: DATA EEPROM WRITE

BSF STATUS, RP0 ; Bank 1 BCF INTCON, GIE ; Disable INTs. BSF EECON1, WREN ; Enable Write MOVLW 55h ;

MOVWF EECON2 ; Write 55h MOVLW AAh ; MOVWF EECON2 ; Write AAh BSF EECON1,WR ; Set WR bit ; begin write

Required

Sequence

BSF INTCON, GIE ; Enable INTs.

The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment.

EXAMPLE 3-3: WRITE VERIFY

BCF STATUS,RP0 ; Bank 0 : ; Any code : ; can go here MOVF EEDATA,W ; Must be in Bank 0 BSF STATUS,RP0 ; Bank 1

READ

BSF EECON1, RD ; YES, Read the

; value written

BCF STATUS, RP0 ; Bank 0

; ; Is the value written ; (in W reg) and ; read (in EEDATA) ; the same?

; SUBWF EEDATA, W ; BTFSS STATUS, Z ; Is difference 0? GOTO WRITE_ERR ; NO, Write error

TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

08h EEDATA EE PROM Data Register 09h EEADR EEPROM Address Register xxxx xxxx uuuu uuuu 88h EECON1

89h EECON2 EEPROM Control Register 2 ---- ---- ---- ---Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition.

Shaded cells are not used by data EEPROM.

— — — EEIF WRERR WREN WR RD ---0 x000 ---0 q000

Value on

Power-on

Reset

xxxx xxxx uuuu uuuu

Value on

all other

RESETS

DS35007B-page 14  2001 Microchip Technology Inc.

PIC16F84A

4.0 I/O PORTS

Some pins for thes e I/O ports are mul tiplexed wit h an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

Additional inform atio n o n I/O ports ma y b e found in the

PICmicro™ Mid-Range Refer ence M anual (DS33 023).

4.1 PORTA and TRISA Registers

PORTA is a 5-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will m ake the corres ponding POR T A pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the correspondin g PORTA pin an output (i.e., put the contents of the output latch on the selected pin).

Note: On a Power-on Reset, these pins are con-

figured as inputs and read as '0'.

Reading the PORTA register reads the status of the pins, whereas writing to i t will wri te to th e po rt latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read. This value is m odifie d and then written to the port data latch.

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trig ger input and an open drai n output. All other RA port pins have TTL input levels and full CMOS output drivers.

EXAMPLE 4-1: INITIALIZING PORTA

BCF STATUS, RP0 ; CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0x0F ; Value used to

; initialize data

; direction MOVWF TRISA ; Set RA<3:0> as inputs

; RA4 as output

; TRISA<7:5> are always

; read as ’0’.

FIGURE 4-1: BLOCK DIAGRAM OF

PINS RA3:RA0

Data Bus

WR Port

WR TRIS

RD Port

Note: I/O pins have protection diodes to VDD and V SS.

Data Latch

TRIS Latch

RD TRIS

VDD

TTL Input Buffer

I/O pin

FIGURE 4-2: BLOCK DIAGRAM OF PIN

RA4

Data Bus

WR Port

WR TRIS

Data Latch

TRIS Latch

RD TRIS

Schmitt Trigger Input Buffer

RA4 pin

RD Port

TMR0 Clock Input

Note: I/O pins have protection diodes to VDD and VSS.

 2001 Microchip Technology Inc. DS35007B-page 15

PIC16F84A

TABLE 4-1: PORTA FUNCTIONS

Name Bit0 Buffer Type Function

RA0 bit0 TTL Input/output RA1 bit1 TTL Input/output RA2 bit2 TTL Input/output RA3 bit3 TTL Input/output RA4/T0CKI bit4 ST Input/output or external clock input for TMR0.

Output is open drain type.

Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05h PORT A

85h TRISA Legend:x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are unimplemented, read as '0'.

— — — R A4/T0CKI RA3 RA2 RA1 RA0 — — — TRISA4 TRISA3 TRISA2 T RIS A1 TRISA0

Value on

Power-on

Reset

---x xxxx ---u uuuu

---1 1111 ---1 1111

Value on all

other

RESETS

DS35007B-page 16  2001 Microchip Technology Inc.

PIC16F84A

4.2 PORTB and TRISB Registers

PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the c orresponding POR TB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the correspo nding POR TB pin an output ( i.e., p ut the contents of the output latch on the selected pin).

EXAMPLE 4-2: INITIALIZING PORTB

BCF STATUS, RP0 ; CLRF PORTB ; Initialize PORTB by

; clearing output

BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to

MOVWF TRISB ; Set RB<3:0> as inputs

Each of the PORTB pins has a we ak inte rnal pul l-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU pull-up is automatically turned off when the port pin is configured as an outpu t. The pull-ups are disable d on a Power-on Reset.

Four of PORTB’s pi ns, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only us ed f or the int errup t-on -ch ang e feature. Polling of PORTB is not recommended while using the interrupt-on-change feature.

; data latches

; initialize data

; direction

; RB<5:4> as outputs

; RB<7:6> as inputs

(OPTION<7>). The weak

FIGURE 4-3: BLOCK DIAGRAM OF

PINS RB7:RB4

RD Port

DD and VSS.

Weak Pull-up

I/O pin

TTL Input Buffer

(1)

RBPU

Data Bus

WR Port

WR TRIS

Set RBIF

From other RB7:RB4 pins

Note 1: TRISB = ’1’ enables weak pull-up

2: I/O pins have diode protection to V

Data Latch

TRIS Latch

RD TRIS

RD Port

= ’0’ in the OPTION_REG register).

(if RBPU

Latch

FIGURE 4-4: BLOCK DIAGRAM OF

PINS RB3:RB0

TTL Input Buffer

DD and VSS.

Weak

Pull-up

I/O pin

RD Port

(1)

RBPU

Data Bus

WR Port

WR TRIS

RB0/INT

Note 1: TRISB = ’1’ enables weak pull-up

2: I/O pins have diode protection to V

Data Latch

TRIS Latch

RD TRIS

RD Port

Schmitt Trigger Buffer

= ’0’ in the OPTION_REG register).

(if RBPU

(2)

 2001 Microchip Technology Inc. DS35007B-page 17

PIC16F84A

TABLE 4-3: PORTB FUNCTIONS

Name Bit Buffer Type I/O Consistency Function

RB0/INT bit0 TTL/ST

RB1 bit1 TTL Input/out put pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/out put pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/out put pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/out put pin (wit h interrupt-on-change).

RB5 bit5 TTL Input/out put pin (wit h interrupt-on-change).

RB6 bit6 TTL/ST

RB7 bit7 TTL/ST

Legend: TTL = TTL input, ST = Schmitt Trigger.

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

(1)

Input/output pin or external interrupt input. Internal software programmable weak pull-up.

Internal software programmable weak pull-up.

(2)

Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up. Serial programming clock.

(2)

Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up. Serial programming data.

TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 81h OPTION_REG RBPU 0Bh,8Bh INTCON GIE Legend:x = unknown, u = unchanged. Shaded cells are not used by PORTB.

INTEDG T0CS T0SE PSA PS2 PS1 PS0

EEIE T0IE INTE RBIE T0IF INTF RBIF

Value on

Power-on

Reset

xxxx xxxx uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111 0000 000x 0000 000u

Value on all other RESETS

DS35007B-page 18  2001 Microchip Technology Inc.

PIC16F84A

5.0 TIMER0 MODULE

The Timer0 module timer/counter has the following features:

• 8-bit timer/counter

• Readable and writable

• Internal or external clock select

• Edge select for external clock

• 8-bit software programmable prescaler

• Interrupt-on-overflow from FFh to 00h Figure 5-1 is a simplified block diagram of the Timer0

module. Additional information on timer modules is available in

the PICmicro™ Mid-Range Reference Manual (DS33023).

5.1 Timer0 Operation

Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In Timer mode, the Timer0 module will increment ev ery ins tru cti on c y cle (with ou t prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed be low.

When an external clock inpu t is used for T i mer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized w ith the internal phase clock (T

OSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization. Additional information on external clock requirements

is available in the PICmicro™ Mid-Range Reference Manual, (DS33023).

5.2 Prescaler

An 8-bit count er is availa ble as a prescale r for the T imer 0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 5-2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutual ly exclu sively shar ed between the T imer0 module and the Watchdog Timer. Thus, a prescaler assignment for t he Tim er0 module me ans that th ere is no prescaler for the Watchdog Timer, and vice-versa.

The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>)

determine the prescaler assignment and pre scale ratio. Clearing bit PSA will assign the p rescaler to the T ime r0

module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable.

Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT , prescale values of 1:1, 1:2, ..., 1:128 are selectable.

When assigned to the Timer0 module, all instructions writing to the TMR0 regi ster (e.g., CLRF 1, MOVWF 1, BSF 1,etc.) will clear the presca ler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.

FIGURE 5-1: TIMER0 BLOCK DIAGRAM

Data Bus

FOSC/4

RA4/T0CKI pin

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).

 2001 Microchip Technology Inc. DS35007B-page 19

T0SE

2: The prescaler is shared with Watchdog Timer (refer to Figure5-2 for detailed block diagram).

T0CS

Programmable

Prescaler

PS2, PS1, PS0

PSA

OUT

Sync with

Internal

Clocks

(2 Cycle Delay)

TMR0

PSOUT

Set Interrupt

Flag bit T0IF

on Overflow

PIC16F84A

5.2.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software con-

trol (i.e., it can be changed “on the fly” during program execution).

Note: To avoid an unintended device RESET, a

specific instructio n sequence (shown in the PICmicro™ Mid-Range Reference Manual, DS33023) must be executed when

5.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON <2>). The interrup t can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by th e Ti mer0 module Interru pt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut-off during SLEEP.

changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

FIGURE 5-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT (= F

RA4/T0CKI

OSC/4)

T0SE

T0CS

M U

PSA

SYNC

Cycles

Data Bus

TMR0 reg

Set Flag bit T0IF

on Overflow

M U

Watchdog

Timer

WDT Enable bit

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

8-bit Prescaler

8 - to - 1 MUX

Time-out

M U X

WDT

PS2:PS0

PSA

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 0Bh,8Bh INTCON GIE 81h OPTION_REG 85h TRISA

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— — — PORTA Data Direction Register ---1 1111 ---1 1111

Value on

POR,

BOR

Value on all

other

RESETS

DS35007B-page 20  2001 Microchip Technology Inc.

PIC16F84A

6.0 SPECIAL FEATURES OF THE CPU

What sets a microcontroller apart from other processors are sp ecial circu its to deal with the needs of real time applications. The PIC16F84A has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are:

• OSC Selection

• RESET

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code Protection

• ID Locations

• In-Circuit Serial Programming™ (ICSP™)

The PIC16F84A has a Watchdog Timer which can be shut-off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer nec essar y delays on power-u p. One i s the Oscillator Start-up Timer (OST), intended to keep

the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. This design keeps the device in RESET while the power supply st abili zes. W ith the se tw o time rs on-c hip, most applications need no external RESET circuitry.

SLEEP mode offers a very low current power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Time-out or through an interrupt. Several oscillator options are provided to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select the various options.

Additional information on special features is available in the PICmicro™ Mid-Range Reference Manual (DS33023).

6.1 Configuration Bits

The configuration bit s can be programme d (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped in program memory location 2007h.

Address 2007h is beyond the user program memory space and it belongs to the special test/configuration memory space (2000h - 3FFFh). This space can only be accessed during programming.

REGISTER 6-1: PIC16F84A CONFIGURATION WORD

R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u

CP CP CP CP CP CP CP CP CP CP PWRTE

bit13 bit0

bit 13-4 CP: Code Protection bit

1 = Code protection disabled 0 = All program memory is code protected

bit 3 PWRTE

1 = Power-up Timer is disabled 0 = Power-up Timer is enabled

bit 2 WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0 FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

: Power-up Timer Enable bit

WDTE F0SC1 F0SC0

 2001 Microchip Technology Inc. DS35007B-page 21

PIC16F84A

6.2 Oscillator Configurations

6.2.1 OSCILLATOR TYPES

The PIC16F84A can be operated in four different oscillator modes. The user can program two configuration bit s (FOSC1 a nd FOSC0) to sele ct one of these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

6.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In XT, LP, or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure6-1).

FIGURE 6-1: CRY STAL/CERAMIC

RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)

(1)

Note 1: See T able 6-1 for recommended values

2: A series resistor (R

The PIC16F84A oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP, or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 6-2).

OSC1

XTAL

OSC2

(2)

of C1 and C2.

for AT strip cut crystals.

(3)

S) may be required

Internal Logic

SLEEP

PIC16FXX

FIGURE 6-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

Clock from Ext. System

Open

OSC1

PIC16FXX

OSC2

TABLE 6-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Ranges Tested:

Mode Freq OSC1/C1 OSC2/C2

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

10.0 MHz

Note: Recommended values of C1 and C2 are

identical to the ranges tested in this table. Higher capacitance increases the stability of the oscillator, but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for the appropriate values of external components.

Note: When using resonators with frequencies

above 3.5 MHz, the use of H S mode rath er than XT mode, is re commended. HS mod e may be used at any V controller is rated.

47 - 100 pF

15 - 33 pF 15 - 33 pF

DD for which the

47 - 100 pF

15 - 33 pF 15 - 33 pF

DS35007B-page 22  2001 Microchip Technology Inc.

PIC16F84A

TABLE 6-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

Mode Freq OSC1/C1 OSC2/C2

LP 32 kHz

200 kHz

XT 100 kHz

2 MHz 4 MHz

HS 4 MHz

20 MHz

Note: Higher capacitance increases the stability

of the oscillator, but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode, as well as XT mode , to av oid ove rdriving crystals with low drive level specification. Since each crystal has its own characteristics , the user should c onsult the crystal manufacturer for appropriate values of external components.

DD > 4.5V, C1 = C2 ≈ 30 pF is recom-

For V mended.

68 - 100 pF

15 - 33 pF

100 - 150 pF

15 - 33 pF 15 - 33 pF

68 - 100 pF

15 - 33 pF

100 - 150 pF

15 - 33 pF 15 - 33 pF

6.2.3 RC OSCILLATOR

For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R

EXT) values, capacitor (CEXT) values, and

the operating temperature. In ad dition to this, the os cillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in le ad fram e c apacitance between package types also affects the oscillation frequency, especially for low C

EXT values. The user needs to take into

account variation, due to tolerance of the external R and C components. Figure 6-3 shows how an R/C combination is connected to the PIC16F84A.

FIGURE 6-3: RC OSCILLATOR MODE

VDD

REXT

OSC1

CEXT

VSS

Recommended values: 5 kΩ ≤ REXT ≤ 100 k

OSC/4

OSC2/CLKOUT

EXT > 20pF

Internal

Clock

PIC16FXX

Ω

 2001 Microchip Technology Inc. DS35007B-page 23

PIC16F84A

6.3 RESET

Some registers a re not affe cted in any RE SET cond ition; their statu s is unkn own on a POR an d un ch ange d in a ny

The PIC16F84A differentiates between various kinds of RESET:

• Power-on Reset (POR)

•MCLR

during normal operation

•MCLR during SLEEP

• WDT Reset (during normal operation)

• WDT Wake-up (during SLEEP)

Figure 6-4 shows a simplified block diagram of the On-Chip RESET Circuit. The MCLR

Reset path has a noise filter to ignore small pulses. The electrical specifications state the pulse width requirements for the

pin.

MCLR

other RESET. Most other reg isters are reset to a “RESET state” on POR, MCLR ation and on M CLR

or WDT Reset during norm al oper-

during SLEEP. They are not a ffec ted by a WDT Reset during SLEEP, since this RESET is viewed as the resumption of normal operation.

Table 6-3 gives a description of RESET conditions for the program counter (PC) and the STATUS register. T able 6-4 gives a full description of RESET s tates for all registers.

The TO

and PD bits are set or cleared differently in different RESET situations (Section 6.7). These bits are used in software to de termine the nature of th e RESET.

FIGURE 6-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

VDD

OSC1/ CLKIN

WDT

Module

DD Rise

Detect

OST/PWRT

On-Chip

(1)

RC Osc

SLEEP

WDT

Time-out

Reset

Power-on Reset

OST

10-bit Ripple Counter

PWRT

10-bit Ripple Counter

Chip_Reset

See Table 6-5

Enable PWRT

Enable OST

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

2: See Table 6-5.

TABLE 6-3: RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER

Condition Program Counter STATUS Register

Power-on Reset 000h MCLR during normal operat ion 000h MCLR during SLEEP 000h WDT Reset (during normal operation) 000h WDT Wake-up PC + 1 Interrupt wake-up from SLEEP PC + 1

(1)

Legend: u = unchanged, x = unknown Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

DS35007B-page 24  2001 Microchip Technology Inc.

0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu uuu1 0uuu

PIC16F84A

TABLE 6-4: RESET CONDITIONS FOR ALL REGISTERS

during:

MCLR

– normal operation

– SLEEP WDT Reset during normal operation

W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h ---- ---- ---- ---- ---- ---TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h 0000 0000 0000 0000 PC + 1 STATUS 03h 0001 1xxx 000q quuu

(3)

FSR 0 4h xxxx xxxx uuuu uuuu uuuu uuuu

(4)

PORTA PORTB

(5)

05h ---x xxxx ---u uuuu ---u uuuu

06h xxxx xxxx uuuu uuuu uuuu uuuu EEDATA 08h xxxx xxxx uuuu uuuu uuuu uuuu EEADR 09h xxxx xxxx uuuu uuuu uuuu uuuu PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh 0000 000x 0000 000u uuuu uuuu INDF 80h ---- ---- ---- ---- ---- ---OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu PCL 82h 0000 0000 0000 0000 PC + 1 STATUS 83h 0001 1xxx 000q quuu

(3)

FSR 8 4h xxxx xxxx uuuu uuuu uuuu uuuu TRISA 85h ---1 1111 ---1 1111 ---u uuuu TRISB 86h 1111 1111 1111 1111 uuuu uuuu EECON1 88h ---0 x000 ---0 q000 ---0 uuuu EECON2 89h ---- ---- ---- ---- ---- ---PCLATH 8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 8Bh 0000 000x 0000 000u uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition

Note 1: One or more bits in INTCON will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: Table 6-3 lists the RESET value for each specific condition. 4: On any device RESET, these pins are configured as inputs. 5: This is the value that will be in the port output latch.

Wake-up from SLEEP: – through interrupt – through WDT Time-out

uuuq quuu

(2)

(3)

(1)

(2)

(3)

(1)

 2001 Microchip Technology Inc. DS35007B-page 25

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