Microchip PIC16F818, PIC16F819 Schematics
PIC16F818/819
Data Sheet
18/20-Pin
Enhanced Flash Microcontrollers
with nanoWatt Technology
2004 Microchip Technology Inc. DS39598E
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intended manner and under normal conditions.
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knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Sm art Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS39598E-page ii 2004 Microchip Technology Inc.
PIC16F818/819
18/20-Pin Enhanced Flash Microcontr ollers
with nanoWatt Technology
Low-Power Features:
• Power-Managed modes:
- Primary Run: XT, RC oscillator,
87 µA, 1 MHz, 2V
-INTRC: 7µA, 31.25 kHz, 2V
- Sleep: 0.2 µA, 2V
• Timer1 oscillator: 1.8 µA, 32 kHz, 2V
• Watchdog Timer: 0.7 µA, 2V
• Wide operating voltage range:
- Industrial: 2.0V to 5.5V
Oscillators:
• Three Crystal modes:
- LP, XT, HS: up to 20 MHz
• Two External RC modes
• One External Clock mode:
- ECIO: up to 20 MHz
• Internal oscillator block:
- 8 user selectabl e fre que nc i es : 3 1kHz, 125 kHz,
250kHz, 500kHz, 1MHz, 2 MHz, 4 MHz, 8 MHz
Peripheral Features:
• 16 I/O pins with individual direction control
• High sink/source current: 25 mA
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-b it ti m er/ co un ter with prescaler , c a n b e
incremented during Sleep via external crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM (CCP) module:
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 10-bit, 5-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with
SPI™ (Master/Slave) and I2C™ (Slave)
Pin Diagram
18-Pin PDIP, SOIC
RA2/AN2/ VREF-
RA3/AN3/V
RA4/AN4/T0CKI
RA5/MCLR
RB2/SDO/CCP1
RB3/CCP1/PGM
REF+
/VPP
VSS
RB0/INT
RB1/SDI/SDA
•1
2
3
4
5
6
7
PIC16F818/819
8
9
RA1/AN1
18
RA0/AN0
17
RA7/OSC1/CLKI
16
RA6/OSC2/C LK O
15
14
13
12
11
10
DD
V
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5/SS
RB4/SCK/SCL
Special Microcontroller Features:
• 100,000 erase/write cycles Enhanced Flash
program memory typical
• 1,000,000 typical erase/write cycles EEPROM
data memory typical
• EEPROM Data Retention: > 40 years
TM
• In-Circuit Serial Programming
• Processor read/write access to program memory
• Low-Voltage Progr amming
• In-Circuit Debugging via two pins
(ICSPTM) via two pins
Program Memory Data Memory
Device
PIC16F818 1792 1024 128 128 16 5 1 Y Y 2/1
PIC16F819 3584 2048 256 256 16 5 1 Y Y 2/1
2004 Microchip Technology Inc. DS39598E-page 1
Flash
(Bytes)
# Single-Word
Instructions
SRAM
(Bytes)
EEPROM
(Bytes)
I/O Pins
10-bit
A/D (ch)
CCP
(PWM)
SPI™
SSP
Slave
2
C™
I
Timers
8/16-bit
PIC16F818/819
Pin Diagrams
18-Pin PDIP, SOIC
RA2/AN2/VREF-
RA3/AN3/V
RA4/AN4/T0CKI
RA5/MCLR
RB2/SDO/CCP1
RB3/CCP1/PGM
REF+
/VPP
VSS
RB0/INT
RB1/SDI/SDA
•1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
PIC16F818/819
10
28-Pin QFN
RA5/MCLR/VPP
NC
VSS
NC
V
NC
RB0/INT
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
V
DD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5/SS
RB4/SCK/SCL
REF+
RA3/AN3/V
RA4/AN4/T0CKI
282627
1
2
3
4
PIC16F818/819
SS
5
6
7
8109
NC
RA2/AN2/VREF-
25
11
20-Pin SSOP
RA2/AN2/ VREF-
RA3/AN3/V
RA4/AN4/T0CKI
RA5/MCLR
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
RA1/AN1
NC
RA0/AN0
22
23
24
21
20
19
18
17
16
15
14
13
12
•1
REF+
/VPP
VSS
VSS
2
3
4
5
6
7
8
9
10
RA7/OSC1/CLKI
RA6/OSC2/CLKO
DD
V
NC
V
DD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
20
19
18
17
16
15
14
13
PIC16F818/819
12
11
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
V
DD
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5/SS
RB4/SCK/SCL
RB1/SDI/SDA
RB2/SDO/CCP1
NC
RB3/CCP1/PGM
NC
RB5/SS
RB4/SCK/SCL
DS39598E-page 2 2004 Microchip Technology Inc.
PIC16F818/819
Table of Contents
1.0 Device Overview..........................................................................................................................................................................5
2.0 Memory Organization................................................................................................................................................................... 9
3.0 Data EEPROM and Flash Program Memory.............................................................................................................................. 25
4.0 Oscillator Configurations............................................................................................................................................................ 33
5.0 I/O Ports............................................................................... ..................... .................................................................................39
6.0 Timer0 Module ........................................................................................................................................................................... 53
7.0 Timer1 Module ........................................................................................................................................................................... 57
8.0 Timer2 Module ........................................................................................................................................................................... 63
9.0 Capture/Compare/PWM (CCP) Module..................................................................................................................................... 65
10.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 71
11.0 Analog-to-Digital Converter (A/D) Module..................................................................................................................................81
12.0 Special Features of the CPU.................................................... ..................... ............................................................................. 89
13.0 Instruction Set Summary.......................................................................................................................................................... 103
14.0 Development Support............................................................................................................................................................... 111
15.0 Electrical Characteristics.......................................................................................................................................................... 117
16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 143
17.0 Packaging Information. ..................... ..................... ..................... ..................... ......................................................................... 157
Appendix A: Revision History.............................................................................................................................................................163
Appendix B: Device Differences ........................................................................................................................................................ 163
Index .................................................................................................................................................................................................. 165
On-Line Support................................................................................................................................................................................. 171
Systems Information and Upgrade Hot Line...................................................................................................................................... 171
Reader Response..............................................................................................................................................................................172
PIC16F818/819 Product Identification System ..................................................................................................................................173
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2004 Microchip Technology Inc. DS39598E-page 3
PIC16F818/819
NOTES:
DS39598E-page 4 2004 Microchip Technology Inc.
PIC16F818/819
1.0 DEVICE OVERVIEW
This document contains device specific information for
the operation of the PIC16F818/819 devices. Additional
information may be found in the “PICmicro® Mid-Range
MCU Family Reference Manual” (DS33023) which may
be downloaded from the Microchip web site. The
Reference Manual should be considered a comp lementary document to this data sheet and is highly
recommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
The PIC16F818/819 belongs to the Mid-Range family
of the PICmicro
other in the amount of Flash program memory, data
memory and data EEPROM (see Table 1-1). A block
diagram of the devices is shown in Figure 1-1. These
devices contain features that are new to the PIC16
product line:
• Internal RC oscillator with eight selectable
frequencies, including 31.25 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz and
8 MHz. The INTRC can be configured as the
system clock via the configuration bits. Refer to
Section 4.5 “Internal Oscillator Block” and
Section 12.1 “Configuration Bits” for further
details.
• The Timer1 module current consumption has
been greatly reduced from 20 µA (previous PIC16
devices) to 1.8µA typical (32 kHz at 2V), which is
ideal for real-time clock applications. Refer to
Section 6 .0 “Timer0 Module” for further details.
• The amount of oscill ator selections ha s increased.
The RC and INTRC modes can be selected with
an I/O pin configured as an I/O or a clock output
OSC/4). An external clock can be configured
(F
with an I/O pin. Refer to Section 4.0 “Oscillator
Configurations” for further details.
®
devices. The device s differ from each
TABLE 1-1: AVAILABLE MEMORY IN
PIC16F818/819 DEVICES
Device
PIC16F818 1K x 14 128 x 8 128 x 8
PIC16F819 2K x14 256 x 8 256 x 8
There are 16 I/O pins that are user configurable on a
pin-to-pin basis. Some pins are multiplexed with other
device functions. These functions include:
• External Interrupt
• Change on PORTB Interrupt
• Timer0 Clock Input
• Low-Power Timer1 Clock/Oscillator
• Capture/Compare/PWM
• 10-bit, 5-channel Analog-to-Digital C onverter
2
• SPI/I
•MCLR (RA5) can be configured as an Input
Table 1-2 details the pinout of the devices with
descriptions and details for each pin.
Program
Flash
C
Data
Memory
Data
EEPROM
2004 Microchip Technology Inc. DS39598E-page 5
PIC16F818/819
FIGURE 1-1: PIC16F818/819 BLOCK DIAGRAM
Program
Bus
RA7/OSC1/CLKI
RA6/OSC2/CLKO
Flash
Program
Memory
1K/2K x 14
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8-Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
(13-bit)
Timer
Reset
Timer
Reset
RAM Addr
7
3
8
Data Bus
RAM
File
Registers
128/256 x 8
(1)
9
Addr MUX
8
FSR reg
Status reg
MUX
ALU
W reg
8
Indirect
Addr
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR/VPP
RA6/OSC2/CLKO
RA7/OSC1/CLKI
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
RB4/SCK/SCL
RB5/SS
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
MCLR
VDD, VSS
Timer0
10-bit, 5-channel
A/D
Note 1: Higher or der bits are from the Status register.
Timer1 Timer2
Synchronous
Serial Port
Data EE
128/256 Bytes
CCP1
DS39598E-page 6 2004 Microchip Technology Inc.
PIC16F818/819
TABLE 1-2: PIC16F818/819 PINOUT DESCRIPTIONS
PDIP/
Pin Name
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/V
RA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR
RA6/OSC2/CLKO
RA7/OSC1/CLKI
Legend: I = Input O = Output I/O = Input/Output P = Power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
REF-
RA2
AN2
REF-
V
RA3
AN3
REF+
V
RA4
AN4
T0CKI
/VPP
RA5
MCLR
VPP
RA6
OSC2
CLKO
RA7
OSC1
CLKI
– = Not used TTL = TTL Input ST = Schmitt Trigger Input
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
SSOP
SOIC
Pin#
17 19 23
18 20 24
1126
2227
3328
441
15 17 20
16 18 21
Pin#
QFN
Pin#
I/O/P
Type
I/O
I
I/O
I
I/O
I
I
I/O
I
I
I/O
I
I
I
I
P
I/O
O
O
I/O
I
I
Buffer
Type
TTL
Analog
TTL
Analog
TTL
Analog
Analog
TTL
Analog
Analog
ST
Analog
ST
ST
ST
–
ST
–
–
ST
ST/CMOS
–
Description
PORTA is a bidirectional I/O port.
Bidirectional I/O pin.
Analog input channel 0.
Bidirectional I/O pin.
Analog input channel 1.
Bidirectional I/O pin.
Analog input channel 2.
A/D reference voltage (low) input.
Bidirectional I/O pin.
Analog input channel 3.
A/D reference voltage (high) input.
Bidirectional I/O pin.
Analog input channel 4.
Clock input to the TMR0 timer/counter.
Input pin.
Master Clear (Reset). Input/programming
voltage input. This pin is an active-low Reset
to the device.
Programming threshold voltage.
Bidirectional I/O pin.
Oscillator cryst al outpu t. Connect s to crys tal or
resonator i n Crystal Oscill ator mode.
In RC mode, this pin outputs CLKO signal
which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
Bidirectional I/O pin.
(3)
Oscillator crystal input.
External clock source input.
2004 Microchip Technology Inc. DS39598E-page 7
PIC16F818/819
TABLE 1-2: PIC16F818/819 PINOUT DESCRIPTIONS (CONTINUED)
PDIP/
Pin Name
RB0/INT
RB0
INT
RB1/SDI/SDA
RB1
SDI
SDA
RB2/SDO/CCP1
RB2
SDO
CCP1
RB3/CCP1/PGM
RB3
CCP1
PGM
RB4/SCK/SCL
RB4
SCK
SCL
RB5/SS
RB5
SS
RB6/T1OSO/T1CKI/PGC
RB6
T1OSO
T1CKI
PGC
RB7/T1OSI/PGD
RB7
T1OSI
PGD
SS 5 5, 6 3, 5 P – Ground reference for logic and I/O pins.
V
VDD 14 15, 16 17, 19 P – Positive supply for logic and I/O pins.
Legend: I = Input O = Output I/O = Input/Output P = Power
– = Not used TTL = TTL Input ST = Schmitt Trigger Input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
SSOP
SOIC
Pin#
677
788
899
91010
10 11 12
11 12 13
12 13 15
13 14 16
Pin#
QFN
Pin#
I/O/P
Type
I/O
I
I/O
I
I/O
I/O
O
I/O
I/O
I/O
I
I/O
I/O
I
I/O
I
I/O
O
I
I
I/O
I
I
Buffer
Type
TTL
(1)
ST
TTL
ST
ST
TTL
ST
ST
TTL
ST
ST
TTL
ST
ST
TTL
TTL
TTL
ST
ST
(2)
ST
TTL
ST
(2)
ST
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed fo r in tern al weak pull-up on
all inputs.
Bidirectional I/O pin.
External interrupt pin.
Bidirectional I/O pin.
SPI™ data in.
2
C™ data.
I
Bidirectional I/O pin.
SPI data out.
Capture input, Compare output, PWM output.
Bidirectional I/O pin.
Capture input, Compare output, PWM output.
Low-Voltage ICSP™ Programming enable pin.
Bidirectional I/O pin. Interrupt-on-change pin.
Synchronous serial clock input/output for SPI.
Synchronous serial clock input for I
Bidirectional I/O pin. Interrupt-on-change pin.
Slave select for SPI in Slave mode.
Interrupt-on-change pin.
Timer1 Oscillator output.
Timer1 clock input.
In-circuit debugger and ICSP program m ing
clock pin.
Interrupt-on-change pin.
Timer1 oscillator input.
In-circuit debugger and ICSP program m ing
data pin.
2
C.
DS39598E-page 8 2004 Microchip Technology Inc.
PIC16F818/819
2.0 MEMORY ORGANIZATION
There are two memory blocks in the PIC16F818/819.
These are the program memory and the data memory.
Each block has its own bus, so access to each block
can occur during the same oscillator cycle.
The data memory can be further broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory . This memory is no t directly mapped
into the data memory but is indirectly mapped. That is,
an indirect addres s poin ter speci fies th e addre ss of th e
data EEPROM memory to read/write. The PIC16F818
device’s 128 bytes of dat a EEPROM memory h ave th e
address range of 00 h-7Fh and the PIC16 F819 devic e’s
256 bytes of data EEPROM memo ry hav e the add res s
range of 00h-FFh. More details on the EEPROM
memory can be found in Section 3.0 “Data EEPROM
and Flash Program Memory”.
Additional informa tion on devi ce memory may be found
in the “PICmicro
(DS33023).
®
Mid-Range Reference Manual”
2.1 Program Memory Organization
The PIC16F818/819 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. For the PIC16F818, the first 1K x 14
(0000h-03FFh) is physically implemented (see
Figure 2-1). For the PIC16F819, the first 2K x 14 is
located at 0000h-07FFh (see Figure 2-2). Accessing a
location above the ph ysicall y implem ented addres s will
cause a wraparound. For example, the same instruction will be accessed at locations 020h, 420h, 820h,
C20h, 1020h, 1420h, 1820h and 1C20h.
The Reset vector is a t 0000h and t he in terrupt vecto r i s
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC16F818
PC<12:0>
CALL, RETURN
RETFIE, RETLW
On-Chip
Program
Memory
Stac k Lev el 1
Stac k Lev el 2
Stack Level 8
Reset Vector
Interru pt Vector
Page 0
Wraps to
0000h-03FFh
13
0000h
0004h
0005h
03FFh
0400h
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR
PIC16F819
PC<12:0>
CALL, RETURN
RETFIE, RETLW
On-Chip
Program
Memory
Stac k Lev el 1
Stac k Lev el 2
Stack Level 8
Reset Vector
Interrupt Vector
Page 0
Wraps to
0000h-07FFh
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
2004 Microchip Technology Inc. DS39598E-page 9
1FFFh
PIC16F818/819
2.2 Data Memory Organization
The data memory is p arti tioned into m ultip le ban ks th at
contain the Ge neral Purpose Reg isters and the Spe cial
Function Registers. Bits RP1 (Status<6>) and RP0
(Status<5>) are the bank select bits.
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Ab ove the Speci al Function Registers are th e Genera l Purpos e Regist ers, im plement ed
as static RAM. All implemented bank s contain SFRs.
Some “high use” SFRs from one bank may be mirrored
in another bank for code reduction and quicker access
(e.g., the Status register is in Banks 0-3).
Note: EEPROM dat a memory description can be
found in Section 3.0 “Data EEPROM and
Flash Program Memory” of this data
sheet.
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or
indirectly through the File Select Register, FSR.
DS39598E-page 10 2004 Microchip Technology Inc.
FIGURE 2-3: PIC16F818 REGISTER FILE MAP
PIC16F818/819
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0 ADCON1
General
Purpose
Register
96 Bytes
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*)
OPTION_REG
STATUS
PCLATH
INTCON
OSCCON
OSCTUNE
SSPADD
SSPSTAT
ADRESL
General
Purpose
Register
32 Bytes
Accesses
40h-7Fh
PCL
FSR
TRISA
TRISB
PIE1
PIE2
PCON
PR2
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
Accesses
20h-7Fh
File
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
11Fh
120h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved
Reserved
Accesses
20h-7Fh
(1)
(1)
File
Address
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
19Fh
1A0h
Bank 0
7Fh
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
2004 Microchip Technology Inc. DS39598E-page 11
Bank 1
FFh
Bank 2
17Fh
Bank 3
1FFh
PIC16F818/819
FIGURE 2-4: PIC16F819 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0 ADCON1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*)
OPTION_REG
STATUS
PCLATH
INTCON
OSCCON
OSCTUNE
SSPADD
SSPSTAT
ADRESL
PCL
FSR
TRISA
TRISB
PIE1
PIE2
PCON
PR2
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
File
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
11Fh
120h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved
Reserved
(1)
(1)
File
Address
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
19Fh
1A0h
General
Purpose
Register
96 Bytes
7Fh
Bank 0
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
DS39598E-page 12 2004 Microchip Technology Inc.
General
Purpose
Register
80 Bytes
Accesses
70h-7Fh
Bank 1
EFh
F0h
FFh
General
Purpose
Register
80 Bytes
Accesses
70h-7Fh
Bank 2
16Fh
170h
17Fh
Accesses
20h-7Fh
1FFh
Bank 3
PIC16F818/819
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
(1)
00h
01h TMR0 Timer0 Module Register xxxx xxxx 53, 17
02h
03h
04h
05h PORTA PORTA Data Latch when written; PORTA pins when read xxx0 0000 39
06h PORTB PORTB Data Latch when written; PORTB pins when read xxxx xxxx 43
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah
0Bh
0Ch PIR1
0Dh PIR2
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57
10h T1CON
11h TMR2 Timer2 Module Register 0000 0000 63
12h T2CON
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 71, 76
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 73
15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 66, 67, 68
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 66, 67, 68
17h CCP1CON
18h — Unimplemented — —
19h — Unimplemented — —
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRESH A/D Result Register High Byte xxxx xxxx 81
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: These registers can be addressed from any bank.
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
(1)
PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23
(1)
STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 16
(1)
FSR Indirect Data Memory Address Pointer xxxx xxxx 23
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23
(1)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 18
—ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 20
— — — EEIF — — — — ---0 ---- 21
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 57
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 64
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 65
—ADON0000 00-0 81
Shaded locations are unimplemented, read as ‘0’.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
3: Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
Value on
POR, BOR
Details on
page:
2004 Microchip Technology Inc. DS39598E-page 13
PIC16F818/819
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
(1)
80h
81h OPTION_REG RBPU
82h
83h
84h
85h TRISA TRISA7 TRISA6 TRISA5
86h TRISB PORTB Data Direction Register 1111 1111 43
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah
8Bh
8Ch PIE1
8Dh PIE2
8Eh PCON
8Fh OSCCON
90h
91h — Unimplemented — —
92h PR2 Timer2 Period Registe r 1111 1111 68
93h SSPADD Synchronous Serial Port (I
94h SSPSTAT SMP CKE D/A
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 81
9Fh ADCON1 ADFM ADCS2
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: These registers can be addressed from any bank.
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
(1)
PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23
(1)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 16
(1)
FSR Indirect Data Memory Address Pointer xxxx xxxx 23
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 23
(1)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 18
(1)
OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 36
Shaded locations are unimplemented, read as ‘0’.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
3: Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17, 54
(3)
PORTA Data Direction Register (TRISA<4:0> 1111 1111 39
—ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 19
— — — EEIE — — — — ---0 ---- 21
— — — — — —PORBOR ---- --qq 22
— IRCF2 IRCF1 IRCF0 — IOFS — — -000 -0-- 38
2
C™ mode) Address Register 0000 0000 71, 76
PSR/WUA BF 0000 0000 72
— — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 82
Value on
POR, BOR
Details on
page:
DS39598E-page 14 2004 Microchip Technology Inc.
PIC16F818/819
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 2
(1)
100h
101h TMR0 Timer0 Module Register xxxx xxxx 53
102h
103h
104h
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written; PORTB pins when read xxxx xxxx 43
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah
10Bh
10Ch EEDATA EEPROM/Flash Data Register Low Byte xxxx xxxx 25
10Dh EEADR EEPROM/Flash Address Register Low Byte xxxx xxxx 25
10Eh EEDATH
10Fh EEADRH
Bank 3
180h
181h OPTION _REG RBPU
182h
183h
184h
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 43
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah
18Bh
18Ch EECON1 EEPGD
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 25
18Eh — Reserved; maintain clear 0000 0000 —
18Fh — Reserved; maintain clear 0000 0000 —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: These registers can be addressed from any bank.
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
(1
PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23
(1)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 16
(1)
FSR Indirect Data Memory Address Pointer xxxx xxxx 23
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23
(1)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 18
— — EEPROM/Flash Data Register High Byte --xx xxxx 25
— — — — — E EPROM /F lash A ddr ess Regi st er
(1)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
(1)
PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23
(1)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 16
(1)
FSR Indirect Data Memory Address Pointer xxxx xxxx 23
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23
(1)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 18
Shaded locations are unimplemented, read as ‘0’.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
3: Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17, 54
— — FREE WRERR WREN WR RD x--x x000 26
High Byte
Value on
POR, BOR
---- -xxx 25
Details on
page:
2004 Microchip Technology Inc. DS39598E-page 15
PIC16F818/819
2.2.2.1 Status Register
The St atus register , s hown in Register2-1, contains the
arithmeti c statu s of th e ALU, the Re set sta tus an d the
bank select bits for data memory.
The Status register can be the destination for any
instruction, as with any other register. If the Status
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
and PD bits are not
For example, CLRF STATUS, w ill c lear the upper three
bits and set the Z bit. Thi s leaves the Status register as
‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Stat us regist er because the se inst ructions do not af fect
the Z, C or DC bits from the Status register. For other
instructions not affecting any status bits, see
Section 13.0 “Instruction Set Summary”.
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 bytes.
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow
bit 0 C: Carry/borrow
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW, SUBLW and SUBWF ins tru cti ons )
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
PD ZDCC
(1)
(1,2)
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand.
2: For rotate (RRF, RLF) instructions, this bi t is loa ded with e ither the high or l ow-order
bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39598E-page 16 2004 Microchip Technology Inc.
PIC16F818/819
2.2.2.2 OPTION_RE G Regist er
The OPTION_REG register is a readable and writable
register that contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external
INT interrupt, TMR0 and the weak pull-u ps o n POR TB.
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
REGISTER 2-2: OPTION_REG: OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU
bit 7 bit 0
bit 7 RBPU
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low trans ition on T0CKI pin
0 = Increment on low-to-high trans ition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bit s
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
INTEDG T0CS T0SE PSA PS2 PS1 PS0
: PORTB Pull-up Enable bit
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. DS39598E-page 17
PIC16F818/819
2.2.2.3 INTCON Register
The INTCON register is a readable and writable register that contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.
Note: Interrupt flag bits get set when an interrupt
condition occurs regardle ss of the sta te of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software shoul d ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
A mismatch condi tio n wil l c on tin ue to set flag bit RBIF. Reading PORTB will end the mis mat ch
condition and allow flag bit RBI F to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39598E-page 18 2004 Microchip Technology Inc.
PIC16F818/819
2.2.2.4 PIE1 Regi st er
This register contains the individual enable bits for the
peripheral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE— — SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4 Unimplemented: Read as ‘0’
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. DS39598E-page 19
PIC16F818/819
2.2.2.5 PIR1 Register
This register contains the individual flag bits for the
peripheral interrupts.
Note: Interrupt flag bits are set when an in terrupt
condition occurs regardle ss of the sta te of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software shoul d ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIF— — SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ‘0’
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software befo re returning
from the I n t err upt S erv ic e Ro ut i ne . T h e co ndi ti o ns t hat wil l s et t hi s b i t a re a t ran sm is si on /
reception has taken place.
0 = No SSP interrupt condition has occurred
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overfl owed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39598E-page 20 2004 Microchip Technology Inc.
PIC16F818/819
2.2.2.6 PIE2 Regi st er
The PIE2 register contains the individual enable bit for
the EEPROM write operation interrupt.
REGISTER 2-6: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0
— — — EEIE — — — —
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE write interrupt
0 = Disable EE w rite interrupt
bit 3-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2.2.2.7 PIR2 Register
The PIR2 register contains the fla g bit for the EEPROM
write operation interrupt.
.
Note: Interrupt flag bits are set when an in terrupt
condition occurs regardles s of the sta te of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software shoul d ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST ( FLAG) REGIST ER 2 (ADDRESS 0Dh)
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0
— — — EEIF — — — —
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4 EEIF: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE write interrupt
0 = Disable EE w rite interrupt
bit 3-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. DS39598E-page 21
PIC16F818/819
2.2.2.8 PCON Regist er
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should en sure the ap propriate interrupt flag bits are clear prior to
enabling an interrupt.
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset, an external MCLR Reset
and WDT Reset.
Note: BOR is unknown on Power-on Reset. It
must then be set by the us er an d c hec ke d
on subsequent Resets to see if BOR is
clear , indicating a brown-out has occurred.
The BOR status bit is a ‘don’t care’ and is
not necessarily predictable if the brownout circuit is disabled (by clearing the
BOREN bit in the Configuration word).
REGISTER 2-8: PCON: POWER CONTROL REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x
— — — — — —PORBOR
bit 7 bit 0
bit 7-2 Unimplemented: R e ad as ‘0’
bit 1 POR
bit 0 BOR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39598E-page 22 2004 Microchip Technology Inc.
PIC16F818/819
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The upper bits (PC<12:8>) are
not readable but are indirectly writable through the
PCLATH register. On any Reset, the upper bits of the
PC will be cleared. Fig ure2-5 shows the two situations
for the loading of the PC. The upper example in the
figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the
figure shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
87
PCLATH<4:3>
PCLATH
11
8
Instruction with
PCL as
Destination
ALU
GOTO,CALL
Opcode <10:0>
The stack operat es as a circular buf fer . This means th at
after the stack has been PUSHed eight times, the ninth
push overwrites th e valu e that was s tored fro m the firs t
push. The tenth pus h ov erwr i tes the se co nd push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
2.4 Indirect Addressing: INDF and FSR Registers
The INDF register is not a physica l register . Addr essing
INDF actually addresse s the regi st er whose ad dress i s
contained in the FSR reg ister (FSR is a pointer). This is
indirect addressing.
EXAMPLE 2-1: INDIR ECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF regi ste r will ret urn the value
of 10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah
2.3.1 COMPUTED GOTO
A computed GOTO is accomplish ed by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercise d i f the t able loca tio n cros ses a PCL
memory boundary (each 256-byte block). Refer to the
application note AN556, “Implementing a Table Read”
(DS00556).
2.3.2 STACK
The PIC16F818/819 family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the Stack Pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an
interrupt causes a branch. The stack is POPed in the
event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although status bits may be affected).
A simple program to clear RAM locations, 20h-2Fh,
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR, 4 ;all done?
GOTO NEXT ;NO, clear next
CONTINUE
: ;YES, continue
An effective 9-b it addre ss is obtained by concatenating
the 8-bit FSR register and the IRP bit (Status<7>) as
shown in Figure 2-6.
2004 Microchip Technology Inc. DS39598E-page 23
PIC16F818/819
FIGURE 2-6: DIRE CT/INDI RECT ADDRESSING
RP1:RP 0 6
From Opcode
0
Indirect AddressingDirect Addressing
IRP FSR Register
7
0
Bank Select Location Select
00 01 10 11
00h
Data
(1)
Memory
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: For register file map detail, see Figure 2-3 or Figure 2-4.
80h
FFh
100h
17Fh
180h
1FFh
Bank Select
Location Select
DS39598E-page 24 2004 Microchip Technology Inc.
PIC16F818/819
3.0 DATA EEPROM AND FLASH PROGRAM MEMORY
The data EEPROM and Flash program memory are
readable and writable during normal operation (over
the full V
in the register file space. Instead, it is indirectly
addressed through the Special Function Registers.
There are six SFRs used to read and write this
memory:
• EECON1
• EECON2
• EEDATA
• EEDATH
• EEADR
• EEADRH
This section focuses on reading and writing data
EEPROM and Flash program memory during normal
operation. Refer to the appropriate device programming specification document for serial programming
information.
When interfacing the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 128 or 256 bytes of data
EEPROM, with an address range from 00h to 0FFh.
Addresses from 80h to FFh are unimplemented on the
PIC16F818 device and will read 00h. When writing to
unimplemented locations, the charge pump will be
turned off.
When interfacing the program memory block, the
EEDATA and EEDATH registers form a two-byte word
that holds the 14-bit data fo r read/write and the EEADR
and EEADRH registers f orm a two-byte wor d that holds
the 13-bit address of the EEPROM location being
accessed. These devices have 1K or 2K words of
program Flash, with an address range from 0000h to
03FFh for the PIC16F818 and 0000h to 07FFh for the
PIC16F819. Addresse s abov e the range of the respe ctive device will wra paround to t he beginning o f program
memory.
The EEPROM data memory allows single byte read
and write. The Flash program memory allows singleword reads and four-word block writes. Program
memory writes must first start with a 32-word block
erase, then write in 4-word blocks. A byte write in data
EEPROM memory automatically erases the location
and writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
DD range). This memory is not directl y mapped
When the device is code-protected, the CPU may
continue to read and write th e data EEPROM memory.
Depending on the settings of the write-protect bits, the
device may or may not be able to write certain blocks
of the program memory; ho wever , reads of the program
memory are allowed. When co de-prote cted, the devic e
programmer can no longer access data or program
memory; this does NOT inh ib it in tern al re ad s or w ri tes .
3.1 EEADR and EEADRH
The EEADRH:EEADR register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 8K words of program EEPROM. When
selecting a data address value, only the LSB of the
address is written to the EEADR regist er. When selecting a program address value, the MSB of the address
is written to the EEADRH register and the LSB is
written to the EEADR register.
If the device cont ains less me mory than the fu ll address
reach of the address register pair, the Most Significant
bits of the regist ers are not im plem ented. F or exam ple,
if the device has 128 b yte s o f da t a EEPROM , th e Mos t
Significant bit of EEADR i s not im plement ed o n acces s
to data EEPROM.
3.2 EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
Control bit, EEPGD, determines if the access will be a
program or data memory access. When clear, as it is
when Reset, any subsequent operations will operate
on the data memory. When set, any subsequent
operations will operate on the program memory.
Control bits, RD and WR, initiate read and write,
respectiv ely. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bi t, when set, wil l allow a write or erase
operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write (or erase) operation is
interrupted by a MCLR
during normal operation. In these situations, following
Reset, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged
in the EEDATA and EEADRregisters.
Interrupt flag bit, EEIF in the PIR2 register, is set when
the write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
or a WDT Time-out Reset
2004 Microchip Technology Inc. DS39598E-page 25
PIC16F818/819
REGISTER 3-1: EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch)
R/W-x U-0 U-0 R/W-x R/W-x R/W-0 R/S-0 R/S-0
EEPGD — — FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-5 Unimplemented: Read as ‘0’
bit 4 FREE: EEPROM Forced Row Erase bit
1 = Erase the program memory row a ddressed by EEADRH:EEADR on th e next WR command
0 = Perform write-only
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR
operation)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1 WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read, RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0 = Does not initiate an EEPROM read
or any WDT Reset during normal
Legend:
R = Readable bit W = Writable bit S = Set only U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39598E-page 26 2004 Microchip Technology Inc.
PIC16F818/819
3.3 Reading Data EEPROM Memory
T o read a d ata memory loca tion, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available in the very next
cycle in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read or until it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1. Write the address to EEADR. Make su re that the
address is not larger than the memory size of
the device.
2. Clear the EEPGD bit to point to EEPROM data
memory.
3. Set the RD bit to start the read operation.
4. Read the data from the EEDATA regi ster.
EXAMPLE 3-1: DATA EEPROM READ
BANKSEL EEADR ; Select Bank of EEADR
MOVF ADDR, W ;
MOVWF EEADR ; Data Memory Address
; to read
BANKSEL EECON1 ; Select Bank of EECON1
BCF EECON1, EEPGD ; Point to Data memory
BSF EECON1, RD ; EE Read
BANKSEL EEDATA ; Select Bank of EEDATA
MOVF EEDATA, W ; W = EEDATA
The steps to write to EEPROM data memory are:
1. If step 10 is not implemented, check the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make su re that the
address is not larger than the memory size of
the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to enable program ope rations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
• Write AAh to EECON2 in two steps (first to W,
then to EECON2)
• Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set
(EEIF must be cleared by firmware). If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to b e cle ar, to indicate
the end of the program cycle.
3.4 Writing to Data EEPROM Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then, the user must follow a
specific write sequence to initiate the write for each
byte.
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not af fect this wri te cycle. The W R bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
EXAMPLE 3-2: DATA EEPROM WRITE
BANKSEL EECON1 ; Select Bank of
BTFSC EECON1, WR ; Wait for write
GOTO $-1 ; to complete
BANKSEL EEADR ; Select Bank of
MOVF ADDR, W ;
MOVWF EEADR ; Data Memory
MOVF VALUE, W ;
MOVWF EEDATA ; Data Memory Value
BANKSEL EECON1 ; Select Bank of
BCF EECON1, EEPGD ; Point to DATA
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable INTs.
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW AAh ;
MOVWF EECON2 ; Write AAh
Required
Sequence
BSF EECON1, WR ; Set WR bit to
BSF INTCON, GIE ; Enable INTs.
BCF EECON1, WREN ; Disable writes
; EECON1
; EEADR
; Address to write
; to write
; EECON1
; memory
; begin write
2004 Microchip Technology Inc. DS39598E-page 27
PIC16F818/819
3.5 Reading Flash Program Memory
To read a program memory location, the user must
write two bytes of the address to the EEADR and
EEADRH registers, set the EEPGD control bit
(EECON1<7>) and then set control bit, RD
(EECON1<0>). Once the read control bit is set, the
program memo ry Flash con troller wil l use the sec ond
instruction cycle to read the data. This causes the
second instruction immediately following the
“BSF EECON1, RD” instruction to be ignore d. The da ta
is availabl e in the very next cycle in the EEDATA and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions. EEDATA and
EEDA TH registe rs will h old this valu e until ano ther read
or until it is written to by the user (during a write
operation).
EXAMPLE 3-3: FLASH PROGRAM READ
BANKSEL EEADRH ; Select Bank of EEADRH
MOVF ADDRH, W ;
MOVWF EEADRH ; MS Byte of Program
; Address to read
MOVF ADDRL, W ;
MOVWF EEADR ; LS Byte of Program
; Address to read
BANKSEL EECON1 ; Select Bank of EECON1
BSF EECON1, EEPGD ; Point to PROGRAM
; memory
BSF EECON1, RD ; EE Read
;
NOP ; Any instructions
; here are ignored as
NOP ; program memory is
; read in second cycle
; after BSF EECON1,RD
BANKSEL EEDATA ; Select Bank of EEDATA
MOVF EEDATA, W ; DATAL = EEDATA
MOVWF DATAL ;
MOVF EEDATH, W ; DATAH = EEDATH
MOVWF DATAH ;
3.6 Erasing Flash Program Memory
The minimum erase block is 32 words. Only through
the use of an external programmer, or through ICSP
control, can larger blocks of program memory be bulk
erased. Word erase in the Flash array is not supp orted.
When initiating an erase sequence from the microcontroller itse lf, a block of 32 words of program memor y
is erased. The Most Significant 11 bits of the
EEADRH:EEADR point to the block being erased.
EEADR< 4:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enabl e
write operations. The FR EE bit is set to select an eras e
operation.
For protection, the wri te i nit iat e s equ enc e f or EEC ON 2
must be used.
After the “BSF EECON1, WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP ins tructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the erase
takes place. This is not Sleep mode, as the clocks and
peripherals will continue to run. After the erase cycle,
the processor will resume operation with the third
instruction after the EECON1 write instruction.
3.6.1 FLASH PROGRAM MEMORY ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1. Load EEADRH:EEADR with address of row
being erased.
2. Set EEPGD bit to point to program memory; set
WREN bit to enable writes and set FREE bit to
enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase.
DS39598E-page 28 2004 Microchip Technology Inc.
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