MICROCHIP PIC16F7X7 Technical data

PIC16F7X7

Data Sheet

28/40/44-Pin, 8-Bit CMOS Flash

Microcontrollers with 10-Bit A/D

and nanoWatt Technology

 2004 Microchip Technology Inc. DS30498C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR­RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
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implicitly or otherwise, under any Microchip intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Sm art Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

DS30498C-page ii  2004 Microchip Technology Inc.

PIC16F7X7

Pin Diagrams

PDIP, SOIC, SSOP (28-pin)

MCLR/VPP/RE3

RA2/AN2/V

RA5/AN4/LVDIN/SS

REF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RA0/AN0
RA1/AN1

/C2OUT

V

1
2
3
4
5
6
7

SS

(1)

8
9

10
11

12
13
14

28
27
26
25
24
23
22
21
20
19
18

PIC16F737/767

17
16
15

RB7/PGD
RB6/PGC
RB5/AN13/CCP3
RB4/AN11
RB3/CCP2
RB2/AN8
RB1/AN10
RB0/INT/AN12
V
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

(1)

/AN9

DD

QFN (28-pin)

MCLR/VPP/RE3

RB7/PGD

RB6/PGC

RB5/AN13/CCP3

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/LVDIN/SS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

/C2OUT

VSS

RA0/AN0

RA1/AN1

2627

28

1
2
3

PIC16F737

4

PIC16F767

5
6
7

10

912

8

25

11

24

23

13 14

RB4/AN11

22

21
20
19
18
17
16
15

RB3/CCP2
RB2/AN8
RB1/AN10
RB0/INT/AN12
V
VSS
RC7/RX/DT

DD

(1)

/AN9

QFN (44-pin)

RC7/RX/DT

RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

VSS

VDD

RB0/INT/AN12

VDD

RB1/AN10

RB2/AN8

RC6/TX/CK

4443424140

1
2
3
4
5
6
7
8
9
10
11

131415

12

NC

/AN9

(1)

RB3/CCP2

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

39

38

PIC16F747
PIC16F777

16

17

18

/VPP/RE3

RB7/PGD

RB6/PGC

RB4/AN11

MCLR

RB5/AN13/CCP3

(1)

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

363435

37

202122

19

RA1/AN1

RA0/AN0

REF-/CVREF

RA2/AN2/V

(1)

RC5/SDO

RC2/CCP1

RC0/T1OSO/T1CKI

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

33
32
31
30
29
28
27
26
25
24

23

REF+

RA3/AN3/V

OSC2/CLKO/RA6
OSC1/CLKI/RA7

SS

V
VSS
NC
VDD
RE2/CS/AN7

/AN6

RE1/WR
RE0/RD

/AN5
RA5/AN4/LVDIN/SS
RA4/T0CKI/C1OUT

/C2OUT

RC4/SDI/SDA

RC3/SCK/SCL

RC6/TX/CK

Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

DS30498C-page 2  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

PIC16F7X7

RC7/RX/DT

RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

RB0/INT/AN12

RB1/AN10

RB2/AN8

RB3/CCP2

(1)

V

VDD

/AN9

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2(1)

NC

4443424140

1
2
3
4

PIC16F747

SS

5
6
7
8
9
10
11

121314

NC

NC

RB4/AN11

16

15

RB6/PGC

RB5/AN13/CCP3

39

37

38

17

1819202122

RA0/AN0

/VPP/RE3

RB7/PGD

MCLR

363435

RA1/AN1

33
32
31
30
29
28
27
26
25
24
23

REF-/CVREF

RA3/AN3/VREF+

RA2/AN2/V

NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

SS

VDD
RE2/CS/AN7

/AN6

RE1/WR

/AN5

RE0/RD
RA5/AN4/LVDIN/SS
RA4/T0CKI/C1OUT

/C2OUT

 2004 Microchip Technology Inc. DS30498C-page 3

PIC16F7X7

Table of Contents

1.0 Device Overview..........................................................................................................................................................................5

2.0 Memory Organization.................................................................................................................................................................15

3.0 Reading Program Memory .......................................................................................... ...... ......................................................... 31

4.0 Oscillator Configurations............................................................................................................................................................ 33

5.0 I/O Ports............................ ..................... ..................... ..................... .......................................................................................... 49

6.0 Timer0 Module ........................................................................................................................................................................... 73

7.0 Timer1 Module ........................................................................................................................................................................... 77

8.0 Timer2 Module ........................................................................................................................................................................... 85

9.0 Capture/Compare/PWM Modules ................................................................................................ .............................................. 87

10.0 Master Synchronous Serial Port (MSSP) Module ...................................................................................................................... 93

11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) ........................................................... 133

12.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................151

13.0 Comparator Module............................................................. .... ......... .. .... .. .... ......... .. .... .... .........................................................161

14.0 Comparator Voltage Reference Module...................................................................................................................................167

15.0 Special Features of the CPU............................................................ ..................... ................................................................... 169

16.0 Instruction Set Summary.......................................................................................................................................................... 193

17.0 Development Support...............................................................................................................................................................201

18.0 Electrical Characteristics.......................................................................................................................................................... 207

19.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................237

20.0 Packaging Information...................... ..................... ..................... ..................... ......................................................................... 251

Appendix A: Revision History.............................................................................................................................................................261

Appendix B: Device Differences.........................................................................................................................................................261

Appendix C: Conversion Considerations .................................................................... .... .. .... .. .... ....................................................... 262

Index .................................................................................................................................................................................................. 263

On-Line Support........................................................................ .. .... .. ......... .... .. .... ......... .. ................................................................... 271

Systems Information and Upgrade Hot Line...................................................................................................................................... 271

Reader Response.............................................................................................................................................................................. 272

PIC16F7X7 Product Identification System.........................................................................................................................................273

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DS30498C-page 4  2004 Microchip Technology Inc.

PIC16F7X7

1.0 DEVICE OVERVIEW

This document contains device specific information
about the following devices:

• PIC16F737 • PIC16F767

• PIC16F747 • PIC16F777

PIC16F737/767 devices are available only in 28-pin
packages, while PIC16F747/777 devices are available
in 40-pin and 44-pin packages. All devices in the
PIC16F7X7 family sha re com mon archi tecture with the
following differences:

• The PIC16F737 and PIC1 6F7 67 ha ve on e-h alf of
the total on-chip memory of the PIC16F747 and
PIC16F777.

• The 28-pin devices have 3 I/O ports, while the
40/44-pin devices have 5.

• The 28-pin devices have 16 interrupts, while the
40/44-pin devices have 17.

• The 28-pin devices have 11 A/D input channels,
while the 40/44-pin devices have 14.

• The Parallel Slave Port is implemented only on
the 40/44-pin devices.

• Low-Power m od es: RC_RUN allows the core and
peripherals to be clocked from the INTRC, while
SEC_RUN allows the core and peripherals to be
clocked from the low-power Timer1. Refer to
Section 4.7 “Power-Managed Modes” for
further details.

• Internal R C o scil la t o r w i th ei gh t s e le ctable
frequencies , i nc lu di ng 3 1.2 5kHz, 125 kHz,
250kHz, 500kHz, 1MHz, 2 MHz, 4 MHz and
8 MHz. The INTRC can be configured as a primary
or secondary clock source. Refer to Section 4.5
“Internal Oscilla tor Bloc k” f or fur the r d etails.

• The Timer1 module current consumption has
been greatly reduced from 20µA (previous PIC16
devices) to 1.8 µA typical (32 kHz at 2V), which is
ideal for real-time clock applications. Refer to
Section 7.0 “Timer1 Module” for further details.

• Extended Watchdog Ti me r (W D T) tha t can have a
programmable period from 1 ms to 268s. The WDT
has its own 16-bit pre scaler . Refer to Section 15.17
“Watch dog Timer (WDT)” for further details.

• Two-Speed Start-up: When the oscillator is
configured for LP, XT or HS, this feature will clock
the device from the INTRC while the oscillator is
warming up. This, in turn, will enable almost
immediate code execution. Refer to

Section 15.17.3 “Two-Speed Clock Start-up
Mode” for further details.

• Fail-Safe Clo ck Monitor: This feat ure will allow the
device to continue operation if the primary or
secondary clock source fails by switching over to
the INTRC.

The available features are summarized in Table 1-1.
Block diagrams of the PIC16F737/767 and
PIC16F747/777 devic es are provided i n Figure 1-1 and
Figure 1-2, respectively. The pinouts for these device
families are listed in Table 1-2 and Table 1-3.

Additional information may be found in the “PICmicro

Mid-Range MCU Family Reference Manual”

(DS33023) which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be considered a complementary document to this data
sheet and is highly recommended reading for a better
understanding o f the d ev ic e arc hi tec ture a nd operation
of the peripheral modules.

®

TABLE 1-1: PIC16F7X7 DEVICE FEATURES

Key Features PIC16F737 PIC16F747 PIC16F767 PIC16F777

Operating Frequency DC – 20 MHz DC – 20 MHz DC – 20 MHz DC – 20 MHz
Resets (and Delays) POR, BOR

(PWRT, OST)
Flash Program Memory (14-bit words) 4K 4K 8K 8K
Data Memory (bytes) 368 368 368 368
Interrupts 16 17 16 17
I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E
Timers 3333
Capture/Compare/PWM Modules 3 3 3 3
Master Serial Communications MSSP, AUSART MSSP, AUSART MSSP , AUSART MSSP, AUSART
Parallel Communications — PSP — PSP
10-bit Analog-to-Digital Module 11 Input Channels 14 Input Channels 11 Input Channels 14 Input Channels
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Packaging 28-pin PDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

 2004 Microchip Technology Inc. DS30498C-page 5

POR, BOR

(PWRT, OST)

40-pin PDIP

44-pin QFN

44-pin TQFP

POR, BOR

(PWRT, OST)

28-pin PDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

POR, BOR

(PWRT, OST)

40-pin PDIP

44-pin QFN

44-pin TQFP

PIC16F7X7

FIGURE 1-1: PIC16F 73 7 AND PIC16F767 BLOCK DIAGRAM

Program

Bus

OSC1/CLKI

OSC2/CLKO

Standard

Flash

Program

Memory

4K/8K x 14

14

Instruction Register

Instruction
Decode &

Control

Timing

Generation

13

Program Counter

8-Level Stack

Direct Addr

8

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

Brown-out

(13-bit)

Timer

Reset

Timer

Reset

RAM Addr

7

3

8

Data Bus

RAM

File

Registers

368 x 8

(1)

Addr MUX

ALU

WREG

9

Indirect

8

FSR reg

Status reg

MUX

8

Addr

PORTA

PORTB

PORTC

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/
SS/C2OUT

OSC2/CLKO/RA6
OSC1/CLKI/RA7

RB0/INT/AN12
RB1/AN10
RB2/AN8
RB3/CCP2
RB4/AN11
RB5/AN13/CCP3
RB7/PGD:RB6/PGC

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1

RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

(1)

/AN9

(1)

V

DD, VSS

10-bit A/DTimer0 Timer1 Timer2

Comparators

Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

CCP1, 2, 3

MSSP

Addressable

USART

PORTE

BOR/LVD

MCLR

/VPP/RE3

DS30498C-page 6  2004 Microchip Technology Inc.

FIGURE 1-2: PIC16F 74 7 AND PIC16F777 BLOCK DIAGRAM

Program

Bus

OSC1/CLKI
OSC2/CLKO

Standard

Flash

Program
Memory

4K/8K x 14

14

Instruction Register

Instruction

Decode &

Control

Timing

Generation

13

Program Counter

8-Level Stack

Direct Addr

8

Start-up Timer

Watchdog
Brown-out

(13-bit)

Power-up

Timer

Oscillator

Power-on

Reset

Timer

Reset

RAM Addr

7

3

8

Data Bus

RAM

File

Registers

368 x 8

(1)

Addr MUX

ALU

WREG

9

Indirect

8

FSR reg

Status reg

MUX

8

Addr

PIC16F7X7

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/

/C2OUT

SS
OSC2/CLKO/RA6

OSC1/CLKI/RA7

PORTB

PORTC

PORTD

RB0/INT/AN12
RB1/AN10
RB2/AN8
RB3/CCP2
RB4/AN11
RB5/AN13/CCP3
RB7/PGD:RB6/PGC

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

RD7/PSP7:RD0/PSP0

(1)

/AN9

(1)

Parallel Slave Port

V

DD, VSS

10-bit A/DTimer0 Timer1 Timer2

Comparators BOR/LVD

Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

CCP1, 2, 3

MSSP

Addressable

USART

PORTE

RE0/RD

/AN5

/AN6

RE1/WR
RE2/CS

/AN7

MCLR/VPP/RE3

 2004 Microchip Technology Inc. DS30498C-page 7

PIC16F7X7

TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION

PDIP

Pin Name

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

/VPP/RE3

MCLR

MCLR

VPP
RE3

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI/C1OUT

RA5/AN4/LVDIN/SS

Legend: I = input O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

REF-/CVREF

RA2
AN2
V

REF-

REF

CV

REF+

RA3
AN3

REF+

V

RA4
T0CKI
C1OUT

RA5
AN4
LVDIN
SS
C2OUT

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
4: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

/C2OUT

— = Not used TTL = TTL input ST = Schmitt Trigger input

SOIC

SSOP

Pin #

10 7

QFN

Pin #

96

126

227

328

41

52

63

74

I/O/P
Type

I

I

I/O

O

O

I/O

I

P

I

I/O

I

I/O

I

I/O

I
I

0

I/O

I
I

I/O

I

O

I/O

I

I/O

I

O

Buffer

Type

ST/CMOS

ST

—

ST
ST

ST

TTL

TTL

TTL

TTL

ST

TTL

Description

(3)

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST

buffer when configured in RC mode; otherwise CMOS.

External clock source input. Always associated with pin

function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).

Digital I/O.

Oscillator crystal or clock output.

Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs CLKO whic h has 1/4 t he
frequency of OSC1 and denotes the in str uctio n cycle rat e.
Digital I/O.

Master Clear (input) or programming voltage (output).

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input only pin.

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage input (low).
Comparator voltage reference output.

Digital I/O.
Analog input 3.
A/D reference voltage input (high).

Digital I/O – Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output bit.

Digital I/O.
Analog input 4.
Low-Voltage Detect input.
SPI™ slave select input.
Comparator 2 output bit.

DS30498C-page 8  2004 Microchip Technology Inc.

PIC16F7X7

T ABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION (CONTINUED)

PDIP

Pin Name

RB0/INT/AN12

RB0
INT
AN12

RB1/AN10

RB1
AN10

RB2/AN8

RB2
AN8

RB3/CCP2/AN9

RB3

(4)

CCP2
AN9

RB4/AN11

RB4
AN11

RB5/AN13/CCP3

RB5
AN13
CCP3

RB6/PGC

RB6
PGC

RB7/PGD

RB7
PGD

Legend: I = input O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

— = Not used TTL = TTL input ST = Schmitt Trigger input

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
4: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

SOIC

SSOP

Pin #

21 18

22 19

23 20

24 21

25 22

26 23

27 24

28 25

QFN

Pin #

I/O/P
Type

I/O

I
I

I/O

I

I/O

I

I/O
I/O

I

I/O

I

I/O

I

I/O

I/O
I/O

I/O
I/O

Buffer

Type

TTL/ST

TTL

TTL

TTL

TTL

TTL

TTL/ST

TTL/ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.

(1)

Digital I/O.
External interrupt.
Analog input channel 12.

Digital I/O.
Analog input channel 10.

Digital I/O.
Analog input channel 8.

Digital I/O.
CCP2 capture input, compare output, PWM output.
Analog input channel 9.

Digital I/O.
Analog input channel 11.

Digital I/O.
Analog input channel 13.
CCP3 capture input, compare output, PWM output.

(2)

Digital I/O.
In-Circuit Debugger and ICSP™ programming clock.

(2)

Digital I/O.
In-Circuit Debugger and ICSP programming data.

 2004 Microchip Technology Inc. DS30498C-page 9

PIC16F7X7

TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION (CONTINUED)

PDIP

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(4)

CCP2

RC2/CCP1

RC2
CCP1

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

SS 8, 19 5, 16 P — Ground reference for logic and I/O pins.

V
V

DD 20 17 P — Positive supply for logic and I/O pins.

Legend: I = input O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

— = Not used TTL = TTL input ST = Schmitt Trigger input

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
4: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

SOIC

SSOP

Pin #

11 8

12 9

13 10

14 11

15 12

16 13

17 14

18 15

QFN

Pin #

I/O/P
Type

I/O

O

I

I/O

I

I/O

I/O
I/O

I/O
I/O
I/O

I/O

I

I/O

I/O

O

I/O

O

I/O

I/O

I

I/O

Buffer

Type

ST

ST

ST

ST

ST

ST

ST

ST

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.

Digital I/O.
Capture1 input, Compare1 output, PWM1 output.

Digital I/O.
Synchronous serial clock input/output for SPI™ mode.
Synchronous serial clock input/output for I

Digital I/O.
SPI data in.

2

C data I/O.

I

Digital I/O.
SPI data out.

Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock.

Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data.

2

C™ mode.

DS30498C-page 10  2004 Microchip Technology Inc.

PIC16F7X7

TABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION

Pin Name

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

/VPP/RE3

MCLR

MCLR

VPP
RE3

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI/C1OUT

RA5/AN4/LVDIN/SS

Legend: I = input O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.

REF-/CVREF

RA2
AN2

REF-

V
CV

REF

REF+

RA3
AN3

REF+

V

RA4
T0CKI
C1OUT

RA5
AN4
LVDIN
SS
C2OUT

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel

4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

/C2OUT

— = Not used TTL = TTL input ST = Schmitt Trigger input

Slave Port mode (for interfacing to a microprocessor bus).

PDIP
Pin #

QFN

Pin #

13 32 30

14 33 31

11818

21919

32020

42121

52222

62323

72424

TQFP

Pin #

I/O/P
Type

I

I

I/O

O

O

I/O

I

P

I

I/O

I

I/O

I

I/O

I
I
I

I/O

I
I

I/O

I

O

I/O

I
I
I
I

Buffer

Type

ST/CMOS

ST

—

ST
ST

ST

TTL

TTL

TTL

TTL

ST

TTL

Description

(4)

Oscillator crystal or external clock input.

Oscillator cry stal in put or extern al clock sour ce input.
ST buffer when configured in RC mode; otherwise
CMOS.

External clock source input. Always associated with
pin function OSC1 (see OSC1/CLKI, OSC2/CLKO
pins).

Bidirectional I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.

Bidirectional I/O pin.

Master Clear (input) or programming voltage (output).

Master Clear (Reset) input. This pin is an
active-low Reset to the device.

Programming voltage input.

Digital input only pin.

PORTA is a bidirectional I/O port.

Digital I/O.

Analog input 0.

Digital I/O.

Analog input 1.

Digital I/O.

Analog input 2.

A/D reference voltage input (low).

Comparator voltage reference output.

Digital I/O.

Analog input 3.

A/D reference voltage input (high).

Digital I/O – Open-drain when configured as output.

Timer0 external clock input.

Comparator 1 output.

Digital I/O.

Analog input 4.

Low-Voltage Detect input.

SPI™ slave select input.

Comparator 2 output.

 2004 Microchip Technology Inc. DS30498C-page 11

PIC16F7X7

TABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED)

Pin Name

RB0/INT/AN12

RB0
INT
AN12

RB1/AN10

RB1
AN10

RB2/AN8

RB2
AN8

RB3/CCP2/AN9

RB3

(5)

CCP2
AN9

RB4/AN11

RB4
AN11

RB5/AN13/CCP3

RB5
AN13
CCP3

RB6/PGC

RB6
PGC

RB7/PGD

RB7
PGD

Legend: I = input O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.

— = Not used TTL = TTL input ST = Schmitt Trigger input

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

PDIP
Pin #

QFN

TQFP

Pin #

33 9 8

34 10 9

35 11 10

36 12 11

37 14 14

38 15 15

39 16 16

40 17 17

Pin #

I/O/P
Type

I/O

I
I

I/O

I

I/O

I

I/O
I/O

I

I/O

I

I/O

I
I

I/O
I/O

I/O
I/O

Buffer

Type

TTL/ST

TTL

TTL

TTL

TTL

TTL

TTL/ST

TTL/ST

Description

PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.

(1)

Digital I/O.
External interrupt.
Analog input channel 12.

Digital I/O.
Analog input channel 10.

Digital I/O.
Analog input channel 8.

Digital I/O.
CCP2 capture input, compare output, PWM output.
Analog input channel 9.

Digital I/O.
Analog input channel 11

Digital I/O.
Analog input channel 13.
CCP3 capture input, compare output, PWM output.

(2)

Digital I/O.
In-Circuit Debugger and ICSP™ programming
clock.

(2)

Digital I/O.
In-Circuit Debugger and ICSP programming
data.

DS30498C-page 12  2004 Microchip Technology Inc.

PIC16F7X7

T ABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED)

Pin Name

RC0/T1OSO/T1CKI

RC0
T1OSO
T1CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(5)

CCP2

RC2/CCP1

RC2
CCP1

RC3/SCK/SCL

RC3
SCK

SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

PDIP
Pin #

QFN

Pin #

15 34 32

16 35 35

17 36 36

18 37 37

23 42 42

24 43 43

25 44 44

26 1 1

TQFP

Pin #

I/O/P
Type

I/O

O

I

I/O

I

I/O

I/O
I/O

I/O
I/O

I/O

I/O

I

I/O

I/O

O

I/O

O

I/O

I/O

I

I/O

Buffer

Type

ST

ST

ST

ST

ST

ST

ST

ST

Description

PORTC is a bidirectional I/O port.

Digital I/O.

Timer1 oscillator output.

Timer1 external clock input.

Digital I/O.

Timer1 oscillator input.

Capture 2 input, Compare 2 output, PWM 2 output.

Digital I/O.

Capture 1 input, Compare 1 output, PWM 1 output.

Digital I/O.

Synchronous serial clock input/output

for SPI™ mode.

Synchronous serial clock input/output

2

C™ mode.

for I

Digital I/O.

SPI data in.

2

C data I/O.

I

Digital I/O.

SPI data out.

Digital I/O.

AUSART asynchronous transmit.

AUSART synchronous clock.

Digital I/O.

AUSART asynchronous receive.

AUSART synchronous data.

 2004 Microchip Technology Inc. DS30498C-page 13

PIC16F7X7

TABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED)

Pin Name

PDIP
Pin #

RD0/PSP0

RD0
PSP0

RD1/PSP1

RD1
PSP1

RD2/PSP2

RD2
PSP2

RD3/PSP3

RD3
PSP3

RD4/PSP4

RD4
PSP4

RD5/PSP5

RD5
PSP5

RD6/PSP6

RD6
PSP6

RD7/PSP7

RD7
PSP7

/AN5

RE0/RD

RE0
RD
AN5

RE1/WR

/AN6
RE1
WR
AN6

/AN7

RE2/CS

RE2
CS
AN7

SS — 31 — P — Analog ground reference.

V
V

SS 12, 31 6, 30 6, 29 P — Ground reference for logic and I/O pins.
DD — 8 — P — Analog positive supply.

V

DD 11, 32 7, 28 7, 28 P — Positive supply for logic and I/O pins.

V
NC — 13, 29 12, 13,

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.

QFN

TQFP

Pin #

Pin #

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

82525

92626

10 27 27

33, 34

I/O/P
Type

Buffer

Type

Description

PORTD is a bidirectional I/O port or Parallel Slave Port
when interfacing to a microprocessor bus.

(3)

I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O

ST/TTL

ST/TTL

ST/TTL

ST/TTL

ST/TTL

ST/TTL

ST/TTL

ST/TTL

(3)

(3)

(3)

(3)

(3)

(3)

(3)

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

Digital I/O.
Parallel Slave Port data.

PORTE is a bidirectional I/O port.

(3)

ST/TTL

I/O

I/O

I/O

I
I

(3)

ST/TTL

I
I

(3)

ST/TTL

I
I

Digital I/O.
Read control for Parallel Slave Port.
Analog input 5.

Digital I/O.
Write control for Parallel Slave Port.
Analog input 6.

Digital I/O.
Chip select control for Parallel Slave Port.
Analog input 7.

— — These pins are not internally connected. These pins

should be left unconnected.

DS30498C-page 14  2004 Microchip Technology Inc.

PIC16F7X7

2.0 MEMORY ORGANIZATION

There are two memory blocks in each of these
PICmicro
memory have separate buses so that concurrent
access can oc cur and is detailed in this section. The
program memo ry can be read inte rnally b y user co de
(see Section 3.0 “Reading Program Memory”).

Additional informa tion on devi ce memory may be found
in the “PICmicro
Manual” (DS33023).

2.1 Program Memory Organization

The PIC16F7X7 dev ices have a 13-b it program coun ter
capable of addressing an 8K word x 14-bit program
memory space. The PIC16F767/777 devices have
8K words of Flash program memory and the
PIC16F737/747 devices have 4K words. The program
memory maps for PIC16F7X7 devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.

The Reset vector is at 0000h an d the interrupt ve ctor is
at 0004h.

®

MCUs. The program memory and data

®

Mid-Range MCU Family Reference

2.2 Data Memor y Organization

The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (Status<6>) and
RP0 (Status<5>) are the bank select bits:

RP1:RP0 Bank

00 0
01 1
10 2
11 3

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Abo ve the Speci al Function Re gis­ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.

2.2.1 GENERAL PURPOSE REGISTER FILE

The register file (shown in Figure 2-2 and Figure 2-3)
can be accessed either directly, or indirectly, through
the File Select Register (FSR).

FIGURE 2-1: PROGRAM MEMORY MAPS AND STACKS FOR PIC16F7X7 DEVICES

PC<12:0>

CALL, RETURN
RETFIE, RETLW

On-Chip
Program

Memory

Stack Level 1
Stack Level 2

Stack Level 8

Reset Vector

Interrupt Vector

Page 0

Page 1

Page2

Page 3

13

0000h

0004h
0005h

07FFh
0800h

0FFFh
1000h

17FFh
1800h

1FFFh

Memory available on all
PIC16F7X7.

Memory available on PIC16F767
and PIC16F777. The memory
wraps to 000h through 0FFFh on
the PIC16F737 and PIC16F747.

 2004 Microchip Technology Inc. DS30498C-page 15

PIC16F7X7

FIGURE 2-2: DATA MEMORY MAP FOR PIC16F737 AND THE PIC16F767

Indirect addr.

TMR0

PCL

STATUS

FSR

PORTA
PORTB

PORTC

PORTE
PCLATH
INTCON

PIR1

PIR2
TMR1L
TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA
TXREG

RCREG
CCPR2L
CCPR2H

CCP2CON

ADRESH

ADCON0

General
Purpose
Register

96 Bytes

Bank 0

File

Address

(*)

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h

7Fh

Indirect addr.

OPTION_REG

PCL

STATUS

FSR
TRISA
TRISB
TRISC

TRISE

PCLATH
INTCON

PIE1

PIE2

PCON

OSCCON
OSCTUNE
SSPCON2

PR2

SSPADD

SSPSTAT

CCPR3L

CCPR3H

CCP3CON

TXSTA

SPBRG

ADCON2

CMCON

CVRCON

ADRESL

ADCON1

General
Purpose
Register
80 Bytes

Accesses

70h-7Fh

Bank 1

File

Address

(*)

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

EFh
F0h

FFh

Indirect addr.

TMR0

PCL

STATUS

FSR

WDTCON

PORTB

LVDCON
PCLATH
INTCON

PMDATA

PMADR
PMDATH

PMADRH

General
Purpose
Register
16 Bytes

General
Purpose
Register
80 Bytes

Accesses

70h-7Fh

Bank 2

File

Address

(*)

100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h

11Fh
120h

16Fh
170h

17Fh 1FFh

Indirect addr.

OPTION_REG

PCL

STATUS

FSR

TRISB

PCLATH
INTCON

PMCON1

General
Purpose
Register
16 Bytes

General
Purpose
Register
80 Bytes

Accesses

70h-7Fh

Bank 3

File

Address

(*)

180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h

19Fh
1A0h

1EFh
1F0h

Unimplemented data memory locations read as ‘0’.

* Not a phys ic al regis ter.

DS30498C-page 16  2004 Microchip Technology Inc.

PIC16F7X7

FIGURE 2-3: DATA MEMORY MAP FOR PIC16F747 AND THE PIC16F777

Indirect addr.

TMR0

PCL

STATUS

FSR
PORTA
PORTB

PORTC
PORTD

PORTE
PCLATH
INTCON

PIR1

PIR2
TMR1L
TMR1H
T1CON

TMR2

T2CON

SSPBUF
SSPCON
CCPR1L
CCPR1H

CCP1CON

RCSTA
TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRESH
ADCON0

General
Purpose
Register

96 Bytes

Bank 0

File

Address

(*)

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h

7Fh

Indirect addr.

OPTION_REG

PCL

STATUS

FSR

TRISA

TRISB
TRISC
TRISD
TRISE

PCLATH
INTCON

PIE1

PIE2

PCON

OSCCON

OSCTUNE

SSPCON2

PR2

SSPADD

SSPSTAT

CCPR3L

CCPR3H

CCP3CON

TXSTA

SPBRG

ADCON2

CMCON

CVRCON

ADRESL

ADCON1

General
Purpose
Register
80 Bytes

Accesses

70h-7Fh

Bank 1

File

Address

(*)

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

EFh
F0h

FFh

Indirect addr.

TMR0

PCL

STATUS

FSR

WDTCON

PORTB

LVDCON

PCLATH
INTCON

PMDATA

PMADR

PMDATH
PMADRH

General
Purpose
Register
16 Bytes

General
Purpose
Register
80 Bytes

Accesses

70h-7Fh

Bank 2

File

Address

(*)

100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h

11Fh
120h

16Fh
170h

17Fh 1FFh

Indirect addr.

OPTION_REG

PCL

STATUS

FSR

TRISB

PCLATH
INTCON

PMCON1

General
Purpose
Register
16 Bytes

General
Purpose
Register
80 Bytes

Accesses

70h-7Fh

Bank 3

File

Address

(*)

180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h

19Fh
1A0h

1EFh
1F0h

Unimplemented data memory locations read as ‘0’.

* Not a phys ic al regis ter.

 2004 Microchip Technology Inc. DS30498C-page 17

PIC16F7X7

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.

The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY

Address

Bank 0

(4)

00h
01h TMR0 Timer0 Module Register xxxx xxxx 76, 180

(4)

02h

(4)

03h

(4)

04h
05h PORTA PORTA Data Latch when written: PORTA pins when read xx0x 0000 55, 180
06h PORTB PORTB Data Latch when written: PORTB pins when read xx00 0000 64, 180
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 66, 180

(5)

08h

(5)

09h

(1,4)

0Ah

(4)

0Bh
0Ch PIR1 PSPIF
0Dh PIR2 OSFIF CMIF LVDIF
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 83, 180
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 83, 180
10h T1CON
11h TMR2 Timer2 Module Register 0000 0000 86, 180
12h T2CON
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 101, 180
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 101, 180
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 90, 180
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 90, 180
17h CCP1CON
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 134, 180
19h TXREG AUSART Transmit Data Register 0000 0000 139, 180
1Ah RCREG AUSART Receive Data Register 0000 0000 141, 180
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 92, 180
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx 92, 180
1Dh CCP2CON
1Eh ADRESH A/D Result Register High Byte xxxx xxxx 160, 180
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.

Note 1: The upper byte of the progra m c oun ter is n ot dire ctly a ccessi bl e. PCLATH is a holding regis ter f or the P C<1 2:8 > bits, whose contents

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180

PCL Program Counter (PC) Least Significant Byte 0000 0000 29, 180
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180
FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180

PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 67, 180
PORTE — — — — RE3 RE2 RE1 RE0 ---- x000 68, 180
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 29, 180
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 23, 180

Shaded locations are unimplemented, read as ‘0’.

are transferred to the upper byte of the program counter during branches (CALL or GOTO).

2: Other (non Powe r-up) Resets include external Reset through MCLR
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; alway s maintain these bits clear .
4: These regist ers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implement ed on the 28-pin devices (except for RE3), read as ‘ 0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.

(3)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 25, 180

—BCLIF— CCP3IF CCP2IF 000- 0-00 27, 180

— T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 83, 180

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 86, 180

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 88, 180

— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 88, 180

CHS3 ADON 0000 0000 152, 180

and Watchdog Timer Reset.

Value on:

POR, BOR

Details

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DS30498C-page 18  2004 Microchip Technology Inc.

PIC16F7X7

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Bank 1

(4)

80h
81h
82h
83h
84h

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
OPTION_REG

(4)

PCL Program Counter’s (PC) Least Significant Byte 0000 0000 29, 180

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180

(4)

FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 22, 180

85h TRISA PORTA Data Direction Register 1111 1111 55, 181
86h TRISB PORTB Data Direction Register 1111 1111 64, 181
87h TRISC PORTC Data Direction Register 1111 1111 66, 181

(5)

88h
89h
8Ah
8Bh
8Ch PIE1 PSPIE
8Dh PIE2 OSFIE CMIE LVDIE
8Eh PCON
8Fh OSCCON
90h OSCTUNE

TRISD PORTD Data Direction Register 1111 1111 67, 181

(5)

TRISE IBF

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23, 180

(4)

INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 25, 180

(5)

(3)

OBF

(5)

IBOV

(5)

PSPMODE

(5)

(8)

—

PORTE Data Direction bits 0000 1111 69, 181

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 24, 181

—BCLIE— CCP3IE CCP2IE 000- 0-00 26, 181
— — — — — SBOREN POR BOR ---- -1qq 28, 181
— IRCF2 IRCF1 IRCF0 OSTS

(7)

IOFS SCS1 SCS0 -000 1000 38, 181

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 36, 181

91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 105
92h PR2 Timer2 Period Register 1111 1111 86, 181

2

93h SSPADD Synchronous Serial Port (I
94h SSPSTAT SMP CKE D/A

C™ mode) Address Register 0000 0000 101, 181

PSR/WUA BF 0000 0000 101, 181
95h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx 92
96h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx 92
97h CCP3CON
98h TXSTA CSRC TX9 TXEN SYNC

— — CCP3X CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 92

—BRGHTRMTTX9D0000 -010 145, 181
99h SPBRG Baud Rate Generator Register 0000 0000 145, 181
9Ah — Unimplemented — —
9Bh ADCON2

— — ACQT2 ACQT1 ACQT0 — — — --00 0--- 154
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 55, 161
9Dh CVRCON CVREN CVROE CVRR

— CVR3 CVR2 CVR1 CVR0 000- 0000 55, 167
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 180
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 153, 181
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, r ead as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the pr ogra m coun ter is not dire ctly a cces sibl e. PCLATH is a holding regis ter f or the P C<1 2:8 > bit s, whos e con tents

are transferred to the upper byte of the program counter during branches (CALL or GOTO).

2: Other (non Powe r-up) Resets include external Reset through MCLR

and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; alway s maintain these bits clear .
4: These regist ers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implement ed on the 28-pin devices (except for RE3), read as ‘ 0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.

Details

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 2004 Microchip Technology Inc. DS30498C-page 19

PIC16F7X7

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Bank 2

(4)

100h

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180

101h TMR0 Timer0 Module Register xxxx xxxx 76, 180

(4)

102h
103h
104h
105h WDTCON

PCL Program Counter (PC) Least Significant Byte 0000 0000 29, 180

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180

(4)

FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 187
106h POR TB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 64, 180
107h — Unimplemented — —
108h — Unimplemented — —
109h LVDCON

(1,4)

10Ah
10Bh

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23, 180

(4)

INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 25, 180

— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 176

10Ch PMDATA EEPROM Data Register Low Byte xxxx xxxx 32, 181
10Dh PMADR EEPROM Address Register Low Byte xxxx xxxx 32, 181
10Eh PMDATH
10Fh PMADRH

— — EEPROM Data Register High Byte --xx xxxx 32, 181

— — — — EEPROM Address Register High Byte ---- xxxx 32, 181
Bank 3

(4)

180h
181h
182h
183h
184h

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
OPTION_REG

(4)

PCL Program Counter (PC) Least Significant Byte 0000 0000 29, 180

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180

(4)

FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 22, 180

185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 64, 181
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —

(1,4)

18Ah
18Bh
18Ch PMCON1

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23, 180

(4)

INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 25, 180

(6)

r

— — — — — —RD1--- ---0 32, 181
18Dh — Reserved, maintain clear — —
18Eh — Reserved, maintain clear — —
18Fh — Reserved, maintain clear — —
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the progra m c oun ter is n ot dire ctly a ccessi bl e. PCLATH is a holding regis ter f or the P C<1 2:8 > bits, whose contents

are transferred to the upper byte of the program counter during branches (CALL or GOTO).

2: Other (non Powe r-up) Resets include external Reset through MCLR

and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; alway s maintain these bits clear .
4: These regist ers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implement ed on the 28-pin devices (except for RE3), read as ‘ 0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.

Details

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DS30498C-page 20  2004 Microchip Technology Inc.

PIC16F7X7

2.2.2.1 Status Register

The St atus reg ister co ntai ns the ar ithmetic st atu s of the
ALU, the Reset status and the bank select bits for data
memory.

The Status register can be the destination for any
instruction, as with any other register. If the Status
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable, therefore, the result of an instruction with the
Status register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS, w ill c lear the upper three
bits and set the Z bit. Thi s leav es the Status register as
000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Stat us regist er because the se inst ructions do not af fect
the Z, C or DC bits from the Status register. For other
instructions not affecting any Status bits, see

Section 16.0 “Instruction Set Summary”.

Note 1: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.

REGISTER 2-1: STATUS: ARITHMETIC STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (use d for indirect addressi ng)

1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)

Each bank is 128 bytes.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-Down bit

1 = After power-up or b y the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow

two’s complement of the second operand. For rotate (RRF, RLF) instructions, this
bit is loaded with either the high or low-order bit of the source register.

, the polarity is reversed. A subtraction is executed by adding the

PD ZDCC

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. DS30498C-page 21

PIC16F7X7

2.2.2.2 OPTION_REG Register

The OPTION_REG register is a readable and writable
register which c ont ains vario us cont rol bi t s to c onfigu re
the TMR0 prescaler/WDT postscaler (single assign­able register also known as the prescaler), the external
INT interrupt, TMR0 and the weak pull-u ps o n POR TB.

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to
the Watchdog Timer.

REGISTER 2-2: OPTION_REG: OPTION CONTROL REGISTER (ADDRESS 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU

bit 7 bit 0

bit 7 RBPU

1 = PORTB pull-u ps are disabled
0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKO)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

INTEDG T0CS T0SE PSA PS2 PS1 PS0

: PORTB Pull-up Enable bit

Bit Value TMR0 Rate WDT Rate

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS30498C-page 22  2004 Microchip Technology Inc.

PIC16F7X7

2.2.2.3 INTCON Register

The INTCON register is a readable and writable regis­ter which contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.

Note: Interrupt flag bits are set when an in terrupt

condition occurs regardles s of the sta te of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software shoul d ensure the appropri­ate interrupt flag bits are clear prior to
enabling an interrupt.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt

bit 4 INT0IE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 regis ter has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1 INT0IF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. DS30498C-page 23

PIC16F7X7

2.2.2.4 PIE1 Register

The PIE1 register cont ains the ind ividual enab le bits for
the periph eral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

PSPIE

bit 7 bit 0

bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt

Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt

bit 5 RCIE: AUSART Receive Interrupt Enab le bit

1 = Enables the AUSART receive interrupt
0 = Disables the AUSART receive interru pt

bit 4 TXIE: AUSART Transmit Interrupt Enable bit

1 = Enables the AUSART transmit interrupt
0 = Disables the AUSART transmit interrupt

bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt
0 = Disables the SSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS30498C-page 24  2004 Microchip Technology Inc.

PIC16F7X7

2.2.2.5 PIR1 Register

The PIR1 register contains the individual flag bits for
the periph eral interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of its
corresponding enable bit or the Global Inter­rupt Enable bit, GIE (INTCON<7>). User
software should ensure the appropriate inter­rupt bits are clear prior to enabling an interrupt.

REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

PSPIF

bit 7 bit 0

bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred

Note: PSPIF is reserved on 28-pin devices; always maintain this bit clear.

bit 6 ADIF

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

(1)

 2004 Microchip Technology Inc. DS30498C-page 25

PIC16F7X7

2.2.2.6 PIE2 Register

The PIE2 register cont ains the ind ividual enab le bits for
the CCP2 and CCP3 peripheral interrupts.

REGISTER 2-6: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)

R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
OSFIE CMIE LVDIE

bit 7 bit 0

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled
0 = Disabled

bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enabled
0 = Disabled

bit 5 LVDIE: Low-Voltage Detect Interrupt Enable bit

1 = LVD interrupt is enabled
0 = LVD interrupt is disabled

bit 4 Unimplemented: Read as ‘0’
bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enable bus collision interrupt in the SSP when configured for I
0 = Disable bus collision interrupt in the SSP when configured for I

bit 2 Unimplemented: Read as ‘0’
bit 1 CCP3IE: CCP3 Interrupt Enable bit

1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

—BCLIE— CCP3IE CCP2IE

2

C Master mode

2

C Master mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS30498C-page 26  2004 Microchip Technology Inc.

PIC16F7X7

2.2.2.7 PIR2 Register

The PIR2 register contains the flag bits for the CCP2
interrupt.

REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)

R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0

OSFIF CMIF LVDIF —BCLIF— CCP3IF CCP2IF

bit 7 bit 0

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software)
0 = System clock operating

bit 6 CMIF: Comparator Interrupt Fl ag bit

1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed

bit 5 LVDIF: Low-Voltage Detect Interrupt Flag bit

1 = The supply vol tage h as falle n below the spec ified LVD voltage ( must be c leared in softwar e)
0 = The supply voltage is greater then the specified LVD voltage

bit 4 Unimplemented: Read as ‘0’
bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred in the SSP when configured for I
0 = No bus collision has occurred

bit 2 Unimplemented: Read as ‘0’
bit 1 CCP3IF: CCP3 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode:
Unused in this mode.

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode:
Unused.

Note: Interrupt flag bits are set when an in terrupt

condition occurs regardles s of the sta te of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software shoul d ensure the appropri­ate interrupt flag bits are clear prior to
enabling an interrupt.

2

C Master mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. DS30498C-page 27

PIC16F7X7

2.2.2.8 PCON Register

The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR

Reset.

Note: BOR is unknown on POR. It must be set

by the user and checked on subsequent
Resets to see if BOR is clear, indicating a
brown-out has occurred. The BOR status
bit is not predictab le if the brown-ou t circuit
is disabled (by clearing the BOREN bit in
the Configuration Word register).

REGISTER 2-8: PCON: POWER CONTROL/STATUS REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-1

— — — — — SBOREN POR BOR

bit 7 bit 0

bit 7-3 Unimplemented: Read as ‘0’
bit 2 SBOREN: Software Brown-out Reset Enable bit

If BORSEN in Configuration Word 2 is a ‘

1 = BOR enabled
0 = BOR disabled

bit 1 POR

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

: Power-on Reset Status bit

: Brown-out Reset Status bit

1’ and BOREN in Configuration Word 1 is ‘0’:

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS30498C-page 28  2004 Microchip Technology Inc.