MICROCHIP PIC16F7X Technical data
M
PIC16F7X
Data Sheet
28/40-pin, 8-bit CMOS FLASH
Microcontrollers
2002 Microchip Technology Inc. DS30325B
Note the following details of the code protection feature on PICmicro® MCUs.
• The PICmicro family meets the specifications contained in the Microchip Data Sheet.
• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
K
EELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,
PRO MATE, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microID,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, MXDEV , PIC C, PICDEM, PICDEM.ne t, rfPIC, Sel ect
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick T erm Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hoppin g
DS30325B - page ii 2002 Microchip Technology Inc.
M
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
PIC16F7X
Devices Included in this Data Sheet:
• PIC16F73
• PIC16F74
• PIC16F76
• PIC16F77
High Performance RISC CPU:
• High performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 8K x 14 words of FLASH Program M em ory,
Up to 368 x 8 bytes of Data Memory (RAM)
• Pinout compatible to the PIC16C73B/74B/76/77
• Pinout compatible to the PIC16F873/874/876/877
• Interrupt capability (up to 12 sources)
• Eight level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• Processor read access to program memory
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• In-Circuit Serial Programming (ICSP) via two
pins
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit, up to 8-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) wit h SPI (Master
mode) and I
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP), 8-bits wide with
external RD
• Brown-out detection circuitry for
Brown-out Reset (BOR)
2
C (Slave)
, WR and CS controls (40/44-pin only)
CMOS Technology:
• Low power, high speed CMOS FLASH tech nol og y
• Fully static design
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/S ource Current: 25 mA
• Industrial temperature range
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
-20 µA typical @ 3V, 32 kHz
-< 1 µA typical standby current
SPI
(Master)
SSP
2
C
I
(Slave)
USART
Timers
8/16-bit
Device
PIC16F73 4096 192 22 11 5 2 Yes Yes Yes 2 / 1
PIC16F74 4096 192 33 12 8 2 Yes Yes Yes 2 / 1
PIC16F76 8192 368 22 11 5 2 Yes Yes Yes 2 / 1
PIC16F77 8192 368 33 12 8 2 Yes Yes Yes 2 / 1
2002 Microchip Technology Inc. DS30325B-page 1
Program Memory
(# Single Wor d
Instructions)
Data
SRAM
(Bytes)
I/O Interrupts
8-bit
A/D (ch)
CCP
(PWM)
PIC16F7X
Pin Diagrams
DIP, SOIC, SS OP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC3/SCK/SCL
REF
RA4/T0CKI
RA5/AN4/SS
VSS
RC2/CCP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
PIC16F76/73
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
V
DD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
MLF
MCLR/VPP
RA0/AN0
RA1/AN1
RB7/PGD
RB6/PGC
RB5
RB4
24
23
26
RA2/AN2
RA3/AN3/V
RA4/T0CKI
RA5/AN4/SS
OSC1/CLKI
OSC2/CLKO
REF
VSS
27
28
1
2
3
PIC16F73
4
PIC16F76
5
6
7
10
912
8
22
25
11
13 14
21
20
19
18
17
16
15
RB3/PGM
RB2
RB1
RB0/INT
DD
V
VSS
RC7/RX/DT
RC5/SDO
PDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
RE1/WR
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC3/SCK/SCL
REF
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
/AN6
RE2/CS
/AN7
DD
V
VSS
OSC1/CLKIN
RC2/CCP1
RD0/PSP0
RD1/PSP1
RC2/CCP1
RC1/T1OSI/CCP2
RC0/T1OSO/T1CKI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
PIC16F77/74
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
DD
V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RC4/SDI/SDA
RC3/SCK/SCL
RC6/TX/CK
DS30325B-page 2 2002 Microchip Technology Inc.
Pin Diagrams (Continued)
PLCC
PIC16F7X
/VPP
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC
QFP
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR
/AN6
RE2/CS
/AN7
V
DD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
65432
7
8
9
10
11
12
13
14
15
16
17
181920212223242526
RC1/T1OSI/CCP2
RC6/TX/CK
RC5/SDO
1
PIC16F77
PIC16F74
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
44
RD3/PSP3
RD1/PSP1
RD0/PSP0
41
42
43
27
RC5/SDO
RC6/TX/CK
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
NC
RB3/PGM
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
V
VDD
RB0/INT
RB1
RB2
RB3/PGM
4443424140
1
2
3
4
SS
5
6
7
8
9
10
11
121314
NC
NC
39
PIC16F77
PIC16F74
16
17
15
RB5
RB4
RB7/PGD
RB6/PGC
363435
37
38
1819202122
/VPP
RA2/AN2
RA1/AN1
RA0/AN0
MCLR
33
32
31
30
29
28
27
26
25
24
23
RA3/AN3/VREF
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
SS
V
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
2002 Microchip Technology Inc. DS30325B-page 3
PIC16F7X
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................ 13
3.0 Reading Program Memory........................................................................................................................................................ 29
4.0 I/O Ports.................................................................................................................................................................................... 31
5.0 Timer0 Module................................................................................. .. .... .. .. .. ....... .. .. .... .. ............................................................ 43
6.0 Timer1 Module................................................................................. .. .... .. .. .. ....... .. .. .... .. ............................................................ 47
7.0 Timer2 Module................................................................................. .. .... .. .. .. ....... .. .. .... .. ............................................................ 51
8.0 Capture/Compare/PWM Modules............................................................................................................................................. 53
9.0 Synchronous Serial Port (SSP) Module.................................................................................................................................... 59
10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................................................... 69
11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 83
12.0 Special Features of the CPU .................................................................................................................................................... 89
13.0 Instruction Set Summary......................................................................................................................................................... 105
14.0 Development Support........................................ ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ...................................................... 113
15.0 Electrical Characteristics.................................... ............................................. ........................................................................ 119
16.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 141
17.0 Packaging Information............................................................................................................................................................ 151
Appendix A: Revision History ........................................................................................................................................................ 161
Appendix B: Device Differences .................................................................................................................................................... 161
Appendix C: Conversion Considerations ........................................................ .. .. ....... .. .... .. .. .... ..... .... ............................................. 162
Index ................................................................................................................................................................................................. 163
On-Line Support...................................................................... .. .... .... ....... .... .... .. .... ....... .... ................................................................ 169
Reader Response............................................................................................................................................................................. 170
PIC16F7X Product Identification System.. ........................................................................................................................................ 171
TO OUR VALUED CUSTOMERS
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS30325B-page 4 2002 Microchip Technology Inc.
PIC16F7X
1.0 DEVICE OVERVIEW
This document contains device specific information
about the following devices:
• PIC16F73
• PIC16F74
• PIC16F76
• PIC16F77
PIC16F73/76 devic es are ava ilable only in 28-pin packages, while PIC16F74/77 devices are available in
40-pin and 44-pin packages. All devices in the
PIC16F7X fam ily sh are co mmon archi tec tur e, wi th the
following differences:
• The PIC16F73 and PIC16F76 have one-half of
the total on-chip memory of the PIC16F74 and
PIC16F77
• The 28-pin devices have 3 I/O ports, while the
40/44-pin devices have 5
• The 28-pin devices have 11 interrupts, while the
40/44-pin devices have 12
• The 28-pin devices have 5 A/D input channels,
while the 40/44-pin devices have 8
• The Parallel Slave Port is implemented only on
the 40/44-pin devices
The available features are summarized in Table 1-1.
Block diagrams of the PIC16F73/76 and PIC16F74/77
devices are provided in Figure 1-1 and Figure1-2,
respectively. The pinouts for these device families are
listed in Table 1-2 and Table 1-3.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The
Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device
architecture and operation of the peripheral modules.
TABLE 1-1: PIC16F7X DEVICE FEATURES
Key Features PIC16F73 PIC16F74 PIC16F76 PIC16F77
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz
RESETS (and Delays) POR, BOR
(PWRT, OST)
FLASH Program Memory
(14-bit words)
Data Memory (bytes) 192 192 368 368
Interrupts 11 12 11 12
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Timers 3333
Capture/Compare/PWM Modules 2 2 2 2
Serial Communications SSP, USART SSP, USART SSP, USART SSP, USART
Parallel Communications — PSP — PSP
8-bit Analog-to-Digital Module 5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Packaging 28-pin DIP
4K 4K 8K 8K
28-pin SOIC
28-pin SSOP
28-pin MLF
POR, BOR
(PWRT, OST)
40-pin PDIP
44-pin PLCC
44-pin TQFP
POR, BOR
(PWRT, OST)
28-pin DIP
28-pin SOIC
28-pin SSOP
28-pin MLF
POR, BOR
(PWRT, OST)
40-pin PDIP
44-pin PLCC
44-pin TQFP
2002 Microchip Technology Inc. DS30325B-page 5
PIC16F7X
FIGURE 1-1: PIC16F73 AND PIC16F76 BLOCK DIAGRAM
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
FLASH
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
8
Power-up
Start-up Timer
Power-on
Watchdog
Brown-out
(13-bit)
Timer
Oscillator
Reset
Timer
Reset
RAM Addr
7
3
8
Data Bus
RAM
File
Registers
(1)
Addr MUX
FSR reg
STATUS reg
ALU
W reg
9
8
MUX
8
Indirect
Addr
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2/
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MCLR
CCP1
Device Program FLASH Data Memory
PIC16F73 4K 192 Bytes
PIC16F76 8K 368 Bytes
Note 1: Higher order bits are from the STATUS register.
CCP2
VDD, VSS
Synchronous
Serial Port
8-bit A/DTimer0 Timer1 Timer2
USART
DS30325B-page 6 2002 Microchip Technology Inc.
FIGURE 1-2: PIC16F74 AND PIC16F77 BLOCK DIAGRAM
PIC16F7X
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
FLASH
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
MCLR
(13-bit)
Timer
Reset
Timer
Reset
VDD, VSS
RAM Addr
7
3
8
Data Bus
RAM
File
Registers
(1)
Addr MUX
FSR reg
STATUS reg
ALU
W reg
9
8
MUX
8
Indirect
Addr
PORTA
PORTB
PORTC
PORTD
PORTE
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
CCP1
PIC16F74 4K 192 Bytes
PIC16F77 8K 368 Bytes
Note 1: Higher order bits are from the STATUS register.
CCP2
Device Program FLAS H Data Memory
Synchronous
Serial Port
8-bit A/DTimer0 Timer1 Timer2
USART
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
Parallel Slave Port
2002 Microchip Technology Inc. DS30325B-page 7
PIC16F7X
TABLE 1-2: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION
DIP
Pin Name
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO
OSC2
CLKO
/VPP
MCLR
MCLR
VPP
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2
RA2
AN2
RA3/AN3/V
RA4/T0CKI
RA5/SS/
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
REF
RA3
AN3
REF
V
RA4
T0CKI
AN4
RA5
SS
AN4
— = Not used TTL = TTL input ST = Schmitt Trigger input
2: Th is buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: Th is buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
SSOP
SOIC
Pin#
96
10 7
126
227
328
41
52
64
75
MLF
Pin#
I/O/P
Type
I
I
O
O
I
P
I/O
I
I/O
I
I/O
I
I/O
I
I
I/O
I
I/O
I
I
Buffer
Type
(3)
ST/CMOS
— Oscillator crystal or clock output.
ST Master Clear (input) or programming voltage (output).
TTL
TTL
TTL
TTL
ST
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input. ST
buffer when configured in RC mode. Otherwise CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
Master Clear (Reset) input. This pin is an active low
RESET to the device.
Programming voltage input.
PORTA is a bi-directional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
Digital I/O.
Analog input 3.
A/D reference voltage input.
Digital I/O – Open drain when configured as output.
Timer0 external clock input.
Digital I/O.
SPI slave select input.
Analog input 4.
Description
DS30325B-page 8 2002 Microchip Technology Inc.
TABLE 1-2: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin Name
RB0/INT
RB0
INT
RB1 22 19
RB2 23 20
RB3/PGM
RB3
PGM
RB4 25 22
RB5 26 23
RB6/PGC
RB6
PGC
RB7/PGD
RB7
PGD
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
SS 8, 19 5, 16 P — Ground reference for logic and I/O pins.
V
DD 20 17 P — Positive supply for logic and I/O pins.
V
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
— = Not used TTL = TTL input ST = Schmitt Trigger input
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
SSOP
SOIC
Pin#
21 18
24 21
27 24
28 25
11 8
12 9
13 10
14 11
15 12
16 13
17 14
18 15
MLF
Pin#
I/O/P
Type
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
O
I/O
I/O
I
I/O
Buffer
Type
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
TTL/ST
TTL Digital I/O.
TTL Digital I/O.
TTL
TTL Digital I/O.
TTL Digital I/O.
(2)
TTL/ST
(2)
TTL/ST
ST
ST
ST
ST
ST
ST
ST
ST
Digital I/O.
External interrupt.
Digital I/O.
Low voltage ICSP programming enable pin.
Digital I/O.
In-Circuit Debugger and ICSP programming clock.
Digital I/O.
In-Circuit Debugger and ICSP programming data.
PORTC is a bi-directional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
Digital I/O.
SPI data in.
2
I
C data I/O.
Digital I/O.
SPI data out.
Digital I/O.
USART asynchronous transmit.
USART 1 synchronous clock.
Digital I/O.
USART asynchronous receive.
USART synchronous data.
Description
PIC16F7X
2
C mode.
2002 Microchip Technology Inc. DS30325B-page 9
PIC16F7X
TABLE 1-3: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION
DIP
Pin Name
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO
OSC2
CLKO
/VPP
MCLR
MCLR
VPP
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2
RA2
AN2
RA3/AN3/V
RA4/T0CKI
RA5/SS/
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
REF
RA3
AN3
REF
V
RA4
T0CKI
AN4
RA5
SS
AN4
— = Not used TTL = TTL input ST = Schmitt Trigger input
2: Th is buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: Th is buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: Th is buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PLCC
Pin#
Pin#
13 14 30
14 15 31
1218
2319
3420
4521
5622
6723
7824
QFP
Pin#
I/O/P
Type
I
I
O
O
I
P
I/O
I
I/O
I
I/O
I
I/O
I
I
I/O
I
I/O
I
I
Buffer
Type
ST/CMOS
(4)
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. Otherwise
CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
— Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
ST Master Clear (input) or programming voltage (output).
TTL
TTL
TTL
TTL
ST
TTL
Master Clear (Reset) input. This pin is an active low
RESET to the device.
Programming voltage input.
PORTA is a bi-directional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
Digital I/O.
Analog input 3.
A/D reference voltage input.
Digital I/O – Open drain when configured as output.
Timer0 external clock input.
Digital I/O.
SPI slave select input.
Analog input 4.
Description
DS30325B-page 10 2002 Microchip Technology Inc.
PIC16F7X
TABLE 1-3: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin Name
RB0/INT
RB0
INT
RB1 34 37 9
RB2 353810
RB3/PGM
RB3
PGM
RB4 374114
RB5 384215
RB6/PGC
RB6
PGC
RB7/PGD
RB7
PGD
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PLCC
Pin#
Pin#
33 36 8
36 39 11
39 43 16
40 44 17
15 16 32
16 18 35
17 19 36
18 20 37
23 25 42
24 26 43
25 27 44
26 29 1
QFP
Pin#
I/O/P
Type
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
O
I/O
I/O
I
I/O
Buffer
Type
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
TTL/ST
Digital I/O.
External interrupt.
TTL Digital I/O.
TTL Digital I/O.
TTL
TTL Digital I/O.
TTL Digital I/O.
(2)
TTL/ST
(2)
TTL/ST
ST
ST
ST
ST
ST
ST
ST
ST
Digital I/O.
Low voltage ICSP programming enable pin.
Digital I/O.
In-Circuit Debugger and ICSP programming clock.
Digital I/O.
In-Circuit Debugger and ICSP programming data.
PORTC is a bi-directional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
Digital I/O.
Capture1 input/Compare1 output/PWM1 output
Digital I/O
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
Digital I/O.
SPI data in.
2
C data I/O.
I
Digital I/O.
SPI data out.
Digital I/O.
USART asynchronous transmit.
USART 1 synchronous clock.
Digital I/O.
USART asynchronous receive.
USART synchronous data.
Description
2
C mode.
2002 Microchip Technology Inc. DS30325B-page 11
PIC16F7X
TABLE 1-3: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin Name
RD0/PSP0
PLCC
Pin#
Pin#
19 21 38
RD0
PSP0
RD1/PSP1
20 22 39 I
RD1
PSP1
RD2/PSP2
21 23 40 I
RD2
PSP2
RD3/PSP3
22 24 41
RD3
PSP3
RD4/PSP4
27 30 2
RD4
PSP4
RD5/PSP5
28 31 3
RD5
PSP5
RD6/PSP6
29 32 4
RD6
PSP6
RD7/PSP7
30 33 5
RD7
PSP7
RE0/RD
/AN5
8925
RE0
RD
AN5
RE1/WR
/AN6
91026
RE1
WR
AN6
RE2/CS
/AN7
10 11 27
RE2
CS
AN7
SS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
V
DD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
V
NC — 1,17,2
8, 40
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: Th is buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: Th is buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: Th is buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
QFP
Pin#
12,13,
33, 34
I/O/P
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I
I
I/O
I
I
Buffer
Type
Description
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
(3)
ST/TTL
Digital I/O.
Parallel Slave Port data.
(3)
ST/TTL
Digital I/O.
Parallel Slave Port data.
(3)
ST/TTL
Digital I/O.
Parallel Slave Port data.
(3)
ST/TTL
Digital I/O.
Parallel Slave Port data.
(3)
ST/TTL
Digital I/O.
Parallel Slave Port data.
(3)
ST/TTL
Digital I/O.
Parallel Slave Port data.
(3)
ST/TTL
Digital I/O.
Parallel Slave Port data.
(3)
ST/TTL
Digital I/O.
Parallel Slave Port data.
PORTE is a bi-directional I/O port.
(3)
ST/TTL
Digital I/O.
Read control for parallel slave port .
Analog input 5.
(3)
ST/TTL
Digital I/O.
Write control for parallel slave port .
Analog input 6.
(3)
ST/TTL
Digital I/O.
Chip select control for parallel slave port .
Analog input 7.
— These pins are not internally connected. These pins should
be left unconnected.
DS30325B-page 12 2002 Microchip Technology Inc.
PIC16F7X
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro
Memory have separate buses so that concurrent
access can oc cur and is detailed in this section. The
Program Mem ory can be read i ntern ally by user co de
(see Section 3.0).
Additional informa tion on devi ce memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
2.1 Program Memory Organization
The PIC16F7X devices have a 13-bit program counter
capable of addressing an 8K word x 14-bit program
memory space. The PIC16F77/76 devices have
8K words of FLASH program memory and the
PIC16F73/74 devices have 4K words. The program
memory maps for PIC16F7X devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
The RESET Ve ctor is at 0000h an d the Interrup t V ector
is at 0004h.
®
MCUs. The Program Memory and Data
2.2 Data Memory Organization
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits:
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Abo ve the Speci al Function Re gisters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file (shown in Figure 2-2 and Figure 2-3)
can be accessed either directly, or indirectly, through
the File Select Register FSR.
FIGURE 2-1: PROGRAM MEMORY MAPS AND STACKS FOR PIC16F7X DEVICES
CALL, RETURN
RETFIE, RETLW
On-Chip
Program
Memory
PIC16F76/77
PC<12:0>
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
CALL, RETURN
RETFIE, RETLW
On-Chip
Program
Memory
PIC16F73/74
PC<12:0>
13
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
Interrupt Vector
Page 0
Page 1
Unimplemented
Read as ‘0’
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
2002 Microchip Technology Inc. DS30325B-page 13
PIC16F7X
FIGURE 2-2: PIC16F77/76 REGIST ER FIL E MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
CCP2CON
ADCON0
(1)
(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
ADRES
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
(1)
TRISD
(1)
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
PMDATA
PMADR
PMDATH
PMADRH
General
Purpose
Register
16 Bytes
File
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Indirect addr .(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
PMCON1
General
Purpose
Register
16 Bytes
File
Address
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
96 Bytes
7Fh
Bank 0
U nimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devi ce s.
DS30325B-page 14 2002 Microchip Technology Inc.
General
Purpose
Register
80 Bytes 80 Bytes 80 Bytes
accesses
70h-7Fh
Bank 1
EFh
F0h
FFh
General
Purpose
Register
accesses
70h-7Fh
Bank 2
16Fh
170h
17Fh
General
Purpose
Register
accesses
70h - 7Fh
Bank 3
1EFh
1F0h
1FFh
FIGURE 2-3: PIC16F74/73 REGIST ER FIL E MAP
PIC16F7X
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
SSPCON
CCP1CON
CCP2CON
(1)
(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
CCPR1L
CCPR1H
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
ADRES
ADCON0
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
(1)
TRISD
(1)
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
PMDATA
PMADR
PMDATH
PMADRH
File
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
120h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
PMCON1
File
Address
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
1A0h
General
Purpose
Register
96 Bytes
7Fh
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register .
Note 1: These registers are not implemented on 28-pin devices.
2002 Microchip Technology Inc. DS30325B-page 15
General
Purpose
Register
96 Bytes
Bank 1
FFh
accesses
20h-7Fh
Bank 2
16Fh
170h
17Fh
accesses
A0h - FFh
1EFh
1F0h
1FFh
Bank 3
PIC16F7X
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Bank 0
(4)
00h
01h TMR0 Timer0 Module Register
02h
03h
04h
05h PORTA — — PORT A Data Latch when written: PORTA pins when read --0x 0000 32, 96
06h PORTB PORTB Data Latch when written: PORTB pins when read
07h PORTC PORTC Data Latch when written: PORTC pins when read
08h
09h
0Ah
0Bh
0Ch PIR1
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 24, 96
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
11h TMR2 Timer2 Module Register
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 6 4, 68, 96
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
15h CCPR1L Capture/Compare/PWM Register1 (LSB)
16h CCPR1H Capture/Compare/PWM Register1 (MSB)
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D
19h TXREG USART Transmit Data Register 0000 0000 74, 96
1Ah RCREG USART Receiv e Dat a Reg i ste r 0000 0000 76, 96
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB)
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB)
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0
1Eh ADRES A/D Result Registe r Byt e
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Note 1: The upper byte of the program counter is not directly ac cessible. PCLATH is a holding register for the PC<12:8>, whose
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
(4)
PCL Program Counter (PC) Least Significant Byte
(4)
STATUS IRP RP1 RP0 TO PD ZDCC
(4)
FSR Indirect Data Memory Address Pointer
(5)
PORTD PORTD Data Latch when written: PORTD pins when read
(5)
PORTE — — — — — RE2 RE1 RE0
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter
(4)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
(3)
PSPIF
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter du ring branches (
2: Other (non power-up) RESETS include external RESET through MCLR
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clea r.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
GO/
DONE
and Watchdog Timer Reset.
— ADON
CALL or GOTO).
0000 0000 27, 96
xxxx xxxx 45, 96
0000 0000 26, 96
0001 1xxx 19, 96
xxxx xxxx 27, 96
xxxx xxxx 34, 96
xxxx xxxx 35, 96
xxxx xxxx 36, 96
---- -xxx 39, 96
---0 0000 26, 96
0000 000x 21, 96
0000 0000 23, 96
xxxx xxxx 50, 96
xxxx xxxx 50, 96
--00 0000 47, 96
0000 0000 52, 96
-000 0000 52, 96
0000 0000 61, 96
xxxx xxxx 56, 96
xxxx xxxx 56, 96
--00 0000 54, 96
0000 -00x 70, 96
xxxx xxxx 58, 96
xxxx xxxx 58, 96
--00 0000 54, 96
xxxx xxxx 88, 96
0000 00-0 83, 96
Details
on page
DS30325B-page 16 2002 Microchip Technology Inc.
PIC16F7X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
Value on:
Bank 1
(4)
80h
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
(4)
82h
83h
84h
PCL Program Counter’s (PC) Least Significant Byte
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 19, 96
(4)
FSR Indirect data memory address pointer
85h TRISA — — PORTA Data Direction Register
86h TRISB PORTB Data Direction Register
87h TRISC PORTC Data Direction Register
(5)
88h
89h
8Ah
8Bh
8Ch PIE1
TRISD PORTD Data Direction Register
(5)
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 38, 96
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter
(4)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 23, 96
(3)
PSPIE
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
8Dh PIE2 — — — — — — — CCP2IE
8Eh PCON — — — — — — POR BOR
8Fh — Unimplemented
90h — Unimplemented
0000 0000 27, 96
1111 1111 2 0, 44, 96
0000 0000 26, 96
xxxx xxxx 27, 96
--11 1111 32, 96
1111 1111 34, 96
1111 1111 35, 96
1111 1111 36, 96
---0 0000 21, 96
0000 0000 22, 96
---- ---0 24, 97
---- --qq 25, 97
— —
— —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 52, 97
93h SSPADD
Synchronous Serial Port (I
94h SSPSTAT SMP CKE D/A PSR/WUA BF
2
C mode) Address Register
0000 0000 68, 97
0000 0000 60, 97
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
99h SPBRG Baud Rate Generator Register
9Ah — Unimplemented
9Bh — Unimplemented
— —
0000 -010 69, 97
0000 0000 71, 97
—
—
9Ch — Unimplemented —
9Dh — Unimplemented
9Eh — Unimplemented
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0' , r = reserved.
—
—
---- -000 84, 97
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly ac cessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (
2: Other (non power-up) RESETS include external RESET through MCLR
and Watchdog Timer Reset.
CALL or GOTO).
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clea r.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
Details
on page
2002 Microchip Technology Inc. DS30325B-page 17
PIC16F7X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
Value on:
Bank 2
(4)
100h
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
101h TMR0 Timer0 Module Register
(4)
102h
103h
104h
PCL Program Counter (PC) Least Significant Byte
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 19, 96
(4)
FSR Indirect Data Memory Address Pointer
105h — Unimplemented
106h PORTB PORTB Data Latch when written: PORTB pins when read
107h — Unimplemented
108h — Unimplemented
0000 0000 27, 96
xxxx xxxx 45, 96
0000 0000 26, 96
xxxx xxxx 27, 96
— —
xxxx xxxx 34, 96
— —
— —
109h — Unimplemented — —
10Ah
10Bh
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter
(4)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
---0 0000 21, 96
0000 000x 23, 96
10Ch PMDATA Data Register Low Byte xxxx xxxx 29, 97
10Dh PMADR Address Register Low Byte
10Eh PMDA TH — — Data Register High Byte
10Fh PMADRH — — — Address Register High Byte
xxxx xxxx 29, 97
xxxx xxxx 29, 97
xxxx xxxx
Bank 3
(4)
180h
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
(4)
182h
183h
184h
PCL Program Counter (PC) Least Significant Byte 0000 0000 26, 96
(4)
STATUS IRP RP1 RP0 TO PD ZDCC
(4)
FSR Indirect Data Memory Address Pointer xxxx xxxx 27, 96
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 34, 96
187h — Unimplemented
188h — Unimplemented
189h — Unimplemented
(1,4)
18Ah
18Bh
PCLATH — — —
(4)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
18Ch PMCON1
—
(6)
— — — — — — RD
Write Buffer for the upper 5 bits of the Program Counter
18Dh — Unimplemented
18Eh — Reserved maintain clear
18Fh — Reserved maintain clear
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly ac cessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter du ring branches (
2: Other (non power-up) RESETS include external RESET through MCLR
and Watchdog Timer Reset.
CALL or GOTO).
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clea r.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
0000 0000 27, 96
1111 1111 2 0, 44, 96
0001 1xxx 19, 96
— —
— —
— —
---0 0000 21, 96
0000 000x 23, 96
1--- ---0 29, 97
—
0000 0000
0000 0000
Details
on page
29, 97
DS30325B-page 18 2002 Microchip Technology Inc.
PIC16F7X
2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the RESET statu s and the ba nk sele ct bit s for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC, or C bits, then the wri te to thes e three bi ts is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable, therefore, the result of an instruction with the
STATUS regist er as destinat ion may be differen t than
intended.
and PD bits are not
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C, or DC bits from the STATUS register.
For other in s tru ct i o ns no t aff ec t in g an y s tat us b its, s ee
the "Instruction Set Summary."
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO
bit 7 bit 0
bit 7 IRP: Register Bank Select bi t (used for indirect addr essing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO
bit 3 PD
bit 2
bit 1 DC: Digit carry/borrow
bit 0 C: Carry/borrow
: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
PD ZDCC
Note: For borrow
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. DS30325B-page 19
, the polarity is reversed. A subtraction is executed by adding the two’s
PIC16F7X
2.2.2.2 OPTION_REG Register
The OPTION_REG register is a readable and writable
register , which cont ains various contr ol bits to conf igure
the TMR0 prescaler/WDT postscaler (single assignable register k nown als o as th e presca ler), t he Externa l
INT Interrupt, TMR0 and the w eak pull-up s on POR TB.
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU
bit 7 bit 0
bit 7 RBPU
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
INTEDG T0CS T0SE PSA PS2 PS1 PS0
: PORTB Pull-up Enable bit
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30325B-page 20 2002 Microchip Technology Inc.
PIC16F7X
2.2.2.3 INTCON Register
The INTCON register is a readable and writable register, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
Note: Interrupt flag bits are set when an interru pt
condition occurs, re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Glob al Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
A mismatch condition wi ll cont inu e to set flag b it RBIF. Reading PORTB will end the mis match
condition and allow flag bit RBIF to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit i s set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. DS30325B-page 21
PIC16F7X
2.2.2.4 PIE1 Register
The PIE1 register cont ains the ind ividual enab le bits for
the periph eral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIE
bit 7 bit 0
bit 7 PSPIE
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
(1)
: Parallel Slave Port Read/Wri te Interru pt Enab le bit
enable any peripheral interrupt.
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30325B-page 22 2002 Microchip Technology Inc.
PIC16F7X
2.2.2.5 PIR1 Register
Note: Interrupt flag bits are set when an interrupt
The PIR1 register contains the individual flag bits for
the periph eral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIF
bit 7 bit 0
bit 7 PSPIF
bit 6 ADIF: A/D Converter Interrupt Flag bit
bit 5 RCIF: USART Receive Interrupt Flag bit
bit 4 TXIF: USA RT Tra n smit Inte rrupt Flag b it
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
bit 2 CCP1IF: CCP1 Interr u pt Flag bi t
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
(1)
1 = A read or a write operation has tak en pl ace (must be cleared in softw a re)
0 = No read or write has occurred
1 = An A/D conversion is com pl et ed (must be cleared in software)
0 = The A/D conversion is not complete
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
1 = The SSP interrupt condition has o ccurred, and must be cleared in sof tw ar e bef or e
returning from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
2
C Slave
I
A transmission/reception has taken place.
2
I
C Master
A transmission/reception has taken place.
The initiated START condition was completed by the SSP modu le.
The initiated STOP condition w as co m pl et ed by t he SSP module.
The initiated Restart cond iti on was completed by the SSP mo dule.
The initiated Acknowledge condition was com p leted by the SSP module.
A START condition occurred while the SSP module was IDLE (m ult i -master system).
A STOP condition occurred w hile the SSP module was IDLE (mul t i-m aster system).
0 = No SSP inter rupt condition has occurred
Capture mod e:
1 = A TMR1 register capture o ccurred (must be cleared in sof tw ar e)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compar e m at ch occurred
PWM mode:
Unused in this mode
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PSPIF is r ese rv ed o n 28- pin d evice s; always maintain this bit clear.
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
: Parallel Slave Port Read/Writ e In terrupt Flag bit
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should en sure the approp riate interrup t
bits are cle ar pri or to en ab li ng an i nte rru pt.
Legend:
R = Readable bit W = Writable bit U = Un implemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. DS30325B-page 23
PIC16F7X
2.2.2.6 PIE2 Register
The PIE2 register cont ains the ind ividual enab le bits for
the CCP2 peripheral interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IE
bit 7 bit 0
bit 7-1 Unimplemented: Re ad as '0'
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2.2.2.7 PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt.
Note: Interrupt flag bits are set when an interru pt
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IF
bit 7 bit 0
bit 7-1 Unimplemented: Read as '0'
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
condition occurs, re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30325B-page 24 2002 Microchip Technology Inc.
PIC16F7X
2.2.2.8 PCON Register
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR
Reset.
Note: BOR is unknown on POR. It must be set b y
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
— — — — — — POR BOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as '0'
bit 1 POR
bit 0 BOR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurre d. The BOR st atus
bit is not predict able if the bro wn-out circu it
is disabled (by clearing the BODEN bit in
the configuration word).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. DS30325B-page 25
PIC16F7X
2.3 PCL and PCLATH
The program count er (PC) is 13 bit s wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLA TH reg is ter. On any RESET, the upper bits of the
PC will be cleared. Fig ure2-4 shows the two situation s
for the loading of the PC. The up per ex ample in th e figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 2-4: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
2.3.1 COMPUTED
87
PCLATH<4:3>
PCLATH
11
GOTO
A computed GOTO is accomplish ed by adding an offset
to the progr am counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercise d i f the t able loca tio n cros ses a PCL
memory boundary (each 256 byte block). Refer to the
Application Note, “Implementing a Table Read"
(AN556).
2.3.2 STACK
The PIC16F7X fami ly has an 8 -level de ep x 13-bi t wide
hardware s tack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writabl e. The PC i s PUSHed onto th e stac k
when a CALL instruction is executed, or an interrupt
causes a branch. The st ac k is POPed in the ev en t of a
RETURN, RETLW or a RETFIE instruction ex ecution.
PCLATH is not affected by a PUSH or POP operation.
The stack opera tes as a circular buf fer . This means that
after the stack has been PUSHed eight ti mes, the nin th
push overwrites the v alue tha t was stored fro m the first
push. The tenth pus h ov erwri t es the se co nd p us h (an d
so on).
8
Instruction with
PCL as
Destination
ALU
GOTO,CALL
Opcode <10:0>
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an interrupt address.
2.4 Program Memory Paging
PIC16F7X devices are cap able of add ressi ng a conti nuous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO ins truction, th e upper 2
bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruct ion, the user must
ensure that t he page select bits are progr ammed so
that the desired prog ram memory pa ge is addre ssed. If
a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the RETURN instructions (which P OPs
the address from the stack).
Note: The contents of the PCLATH are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
setup the PCLATH for any subsequent
CALLS or GOTOS.
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory . Thi s example as sumes
that PCLATH is saved and restored by the Interrupt
Service Routine
EXAMPLE 2-1: CALL OF A SUBROUTINE
SUB1_P1
RETURN ;return to Call
(if interrupts are used).
IN PAGE 1 FROM PAGE 0
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
: ;called subroutine
: ;page 1 (800h-FFFh)
:
;subroutine in page 0
;(000h-7FFh)
DS30325B-page 26 2002 Microchip Technology Inc.
PIC16F7X
2.5 Indirect Addressing, INDF and FSR Registers
The INDF register is not a physi cal register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruc tion using the INDF register actual ly
accesses the register pointed to by the File Sele ct Register, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly result s in a no op era tion ( alth oug h status bits
may be affected ). An ef fective 9- bit add ress is obt ained
by concatenating the 8 -bit FSR regi ster and the IRP b it
(STATUS<7>), as shown in F igure 2-5.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
FIGURE 2-5: DIRECT/INDIRECT ADDRESSING
RP1:RP 0 6
Bank Sele ct Location Select
From Opcode
0
00 01 10 11
00h
80h
100h
EXAMPLE 2-2: INDIRECT ADDRESSING
MOVLW 0x20 ;initialize pointer
NEXT CLRF INDF ;clear INDF register
CONTINUE
MOVWF FSR ;to RAM
INCF FSR,F ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
: ;yes continue
Indirect AddressingDirect Addressing
IRP FSR Register
Bank Select
180h
7
Location Select
0
Data
(1)
Memory
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: For register file map detail, see Figure 2-2.
FFh
17Fh
1FFh
2002 Microchip Technology Inc. DS30325B-page 27
PIC16F7X
NOTES:
DS30325B-page 28 2002 Microchip Technology Inc.
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