MICROCHIP PIC16F72 Technical data
M
PIC16F72
Data Sheet
28-Pin, 8-Bit CMOS FLASH
Microcontroller with A/D Converter
2002 Microchip Technology Inc. DS39597B
Note the following details of the code protection feature on PICmicro® MCUs.
• The PICmicro family meets the specifications contained in the Microchip Data Sheet.
• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
K
EELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV , MXLAB, PICC , PICDEM, PICDEM.net, rfP IC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hoppin g
DS39597B - page ii 2002 Microchip Technology Inc.
M
PIC16F72
28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter
Device Included:
• PIC16F72
High Performance RISC CPU:
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches, which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of Program Memory,
128 x 8 bytes of Data Memory (RAM)
• Pinout compatible to PIC16C72/72A and
PIC16F872
• Interrupt capability
• Eight-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
Peripheral Features:
• High Sink/Source Current: 25 mA
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM (CCP) module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit, 5-channel analog-to-digital converter
• Synchronous Serial Port (SSP) with
SPI™ (Master/Slave) and I
2
C™ (Slave)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
CMOS Technology:
• Low power, high speed CMOS FLASH technology
• Fully static design
• Wide operating voltage range: 2.0V to 5.5V
• Industrial temperature range
• Low power consumption:
- < 0.6 mA typical @ 3V, 4 MHz
-20 µA typical @ 3V, 32 kHz
-< 1 µA typical standby current
Pin Diagrams
PDIP, SOIC, SSOP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
RC0/T1OSO/T1CKI
RC3/SCK/SCL
REF
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKI
OSC2/CLKO
RC1/T1OSI
RC2/CCP1
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
PIC16F72
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
QFN
/VPP
RA1/AN1
RA0/AN0
MCLR
RB7/PGD
RB6/PGC
RB5
RB4
PIC16F72
10 118 9 12 13 14
RC2/CCP1
RC1/T1OSI
RC3/SCK/SCL
232425262728 22
RC4/SDI/SDA
21
20
19
18
17
16
15
RC6
RC5/SDO
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RC7
RA2/AN2
RA3/AN3/V
RA4/T0CKI
RA5/AN4/SS
OSC1/CLKI
OSC2/CLKO
REF
V
1
2
3
4
SS
5
6
7
RC0/T1OSO/T1CKI
Special Microcontroller Features:
• 1,000 erase/write cycle FLASH program memory
typical
• Power-on Reset (POR), Power-up Timer (PWR T)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscilla tor opti ons
• In-Circuit Serial Programming™ (ICSP ™) vi a 2 pins
• Processor read access to program memo ry
2002 Microchip Technology Inc. DS39597B-page 1
PIC16F72
FLASH Program Memory - (14-bit words, 1000 E/W cycles) 2K
Key Reference Manual Features PIC16F72
Operating Frequency DC - 20 MHz
RESETS and (Delays) POR, BOR, (PWRT, OST)
Data Memory - RAM (8-bit bytes) 128
Interrupts 8
I/O Ports PORTA, PORTB, PORTC
Timer s Timer0, Timer1, Time r2
Capture/Compare/PWM Modules 1
Serial Communications SSP
8-bit A/D Converter 5 channels
Instruction Set (No. of Instructions) 35
DS39597B-page 2 2002 Microchip Technology Inc.
PIC16F72
Table of Contents
1.0 Device Overview.......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................... 7
3.0 I/O Ports.................. ........................................ ..................... ...................................................................................................... 21
4.0 Reading Program Memory ......................................................................................................................................................... 27
5.0 Timer0 Module ........................................................................................................................................................................... 29
6.0 Timer1 Module ........................................................................................................................................................................... 31
7.0 Timer2 Module ........................................................................................................................................................................... 35
8.0 Capture/Compare/PWM (CCP) Module..................................................................................................................................... 37
9.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 43
10.0 Analog-to-Digital Converter (A/D) Module..................................................................................................................................53
11.0 Special Features of the CPU............................... .......................................................................................................................59
12.0 Instruction Set Summary............................................................................................................................................................ 73
13.0 Development Support.................................................................................................................................................................81
14.0 Electrical Characteristics............................................................................................................................................................ 87
15.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................107
16.0 Package Marking Information.. ................................................................................................................................................. 117
Appendix A: Revision History ........................................................................................................................................................ 123
Appendix B: Conversion Considerations.............................................................................. .... .. .. .... .............................................. 123
Index .................................................................................................................................................................................................. 125
On-Line Support................................................................................................................................................................................. 131
Reader Response..............................................................................................................................................................................132
Product Identification System ............................................................................................................................................................ 133
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or c omm ents regarding th is publication, p lease c ontact the M a rketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include
literature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
2002 Microchip Technology Inc. DS39597B-page 3
PIC16F72
NOTES:
DS39597B-page 4 2002 Microchip Technology Inc.
PIC16F72
1.0 DEVICE OVERVIEW
This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the operation of the PIC16F 72 de vic e. Additi ona l inf ormation may be found in the PICmicro™ Mid-Range
MCU Reference Manual (DS33023), which may be
downloaded from the Microchip website. The Reference Manual should be considered a complementary
document to this data sheet, and is highly recommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
The PIC16F72 belongs to the Mid-Range family of the
PICmicro devices. A block diagram of the device is
shown in Figure 1-1.
FIGURE 1-1: PIC16F72 BLOCK DIAGRAM
13
Program Counter
8-Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
(13-bit)
RAM Addr
7
Timer
Reset
Timer
Reset
Program
Bus
OSC1/CLKI
OSC2/CLKO
FLASH
Program
Memory
2K x 14
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
3
8
The program memory contains 2K words, which translate to 2048 instructions, since each 14-bit program
memory word is the same width as each device
instruction. The data memory (RAM) cont ains 128 bytes.
There are 22 I/O pins that are user configurable on a
pin-to-pin basis. Some pins are multiplexed with other
device functions. These functions include:
• External interrupt
• Change on PORTB interrupt
• Timer0 clock input
• Timer1 clock/oscillator
• Capture/Compare/PWM
• A/D converter
2
• SPI/I
C
Table 1-1 details the pinout of the device with
descriptions and details for each pin.
Data Bus
RAM
File
Registers
128 x 8
(1)
Addr MUX
FSR reg
STATUS reg
ALU
W reg
9
8
MUX
8
Indirect
Addr
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
MCLR
VDD, VSS
Timer0
A/D
Note 1: Higher order bits are from the STATUS register.
Timer1 Timer2
Synchronous
Serial Por t
CCP1
2002 Microchip Technology Inc. DS39597B-page 5
PIC16F72
TABLE 1-1: PIC16F72 PINOUT DESCRIPTION
PDIP,
Pin Name
OSC1/CLKI 9 6 I
OSC2/CLKO 10 7 O — Oscillator crystal output. Connects to crystal or resonator in Crystal
MCLR
/VPP
RA0/AN0 2 27 I/O TTL RA0 can also be analog input0.
RA1/AN1 3 28 I/O TTL RA1 can also be analog input1.
RA2/AN2 4 1 I/O TTL RA2 can also be analog input2.
RA3/AN3/V
RA4/T0CKI 6 3 I/O ST RA4 can also be the clock input to the Timer0 module. Output is
RA5/AN4/SS
RB0/INT 21 18 I/O TTL/ST
RB1 22 19 I/O TTL
RB2 23 20 I/O TTL
RB3 24 21 I/O TTL
RB4 25 22 I/O TTL Interrupt-on-change pin.
RB5 26 23 I/O TTL Interrupt-on-change pin.
RB6/PGC 27 24 I/O TTL/ST
RB7/PGD 28 25 I/O TTL/ST
RC0/T1OSO/
T1CKI
RC1/T1OSI 12 9 I/O ST RC1 can also be the Timer1 oscillator input.
RC2/CCP1 13 10 I/O ST RC2 can also be the Capture1 input/Compare1 output/
RC3/SCK/SCL 14 11 I/O ST RC3 can also be the synchronous serial clock input/output for both
RC4/SDI/SDA 15 12 I/O ST RC4 can also be the SPI Data In (SPI mode) or
RC5/SDO 16 13 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6 17 14 I/O ST
RC7 18 15 I/O ST
SS 8, 19 5, 16 P — Ground reference for logic and I/O pins.
V
V
DD 20 17 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
— = Not used TTL = TTL input ST = Schmitt Trigger input
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
SOIC,
SSOP
Pin#
REF 5 2 I/O TTL RA3 can also be analog input3 or analog reference voltage.
MLF
Pin#
1 26 I/P ST Master Clear (Reset) input or programming voltage input. This pin is
7 4 I/O TTL RA5 can also be analog input4 or the slave select for the
11 8 I/O ST RC0 can also be the Timer1 oscillator output or Ti mer1 clock input.
I/O/P
Type
Buffer
Type
ST/CMOS
Description
(3)
Oscillator crystal input/external clock source input.
Oscillator mode. In RC mode, the OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
an active low RESET to the device.
PORTA is a bi-directional I/O port.
open drain type.
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt-on-change pin. Serial programming clock.
Interrupt-on-change pin. Serial programming data.
PORTC is a bi-directional I/O port.
PWM1 output.
2
SPI and I
Data I/O (I
C modes.
2
C mode).
DS39597B-page 6 2002 Microchip Technology Inc.
PIC16F72
2.0 MEMORY ORGANIZATION
There are two memo ry b loc ks in the PIC16F72 device.
These are the program memory and the data memory.
Each block has separate buses so that concurrent
access can occur. Program memory and data memory
are explained in this section. Program memory can be
read internally by the user code (see Section 4.0).
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
Additional informa tion on devi ce memory may be found
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
PIC16F72 devices have a 13-bit program counter capable of addressing a 8K x 14 program memory space.
The address range for this program memory is 0000h 07FFh. Accessing a location above the physically
implemented address will cause a wraparound.
The RESET Ve ctor is at 0000h an d the Interrup t V ector
is at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
2.2 Data Memory Organization
The Data Memo ry is partiti oned into mult iple banks th at
contain the Ge neral Purpose Reg isters and the Special
Function Registers. Bits RP1 (STATUS<6>) and RP0
(STATUS<5>) are the bank select bits.
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Abo ve the Speci al Function Re gisters are General Purpose Registers, implemented as
static RAM.
All implemented ban ks co nta in SFR s. Some “h igh use”
SFRs from one bank m ay be m irro red in an othe r b ank ,
for code reduction and quicker access (e.g., the
STATUS register is in Banks 0 - 3).
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file can be acces sed either directly, or indirectly, through the File Select Register FSR (see
Section 2.5).
CALL, RETURN
RETFIE, RETLW
Space
User Memory
On-chip Program
PC<12:0>
13
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
Memory
0000h
0004h
0005h
07FFh
0800h
1FFFh
2002 Microchip Technology Inc. DS39597B-page 7
PIC16F72
FIGURE 2-2: PIC16F72 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRES
ADCON0 ADCON1
General
Purpose
Register
96 Bytes
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*)
OPTION
STATUS
PCLATH
INTCON
SSPADD
SSPSTAT
General
Purpose
Register
32 Bytes
accesses
40h-7Fh
PCL
FSR
TRISA
TRISB
TRISC
PIE1
PCON
PR2
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
PMDATL
PMADRL
PMDATH
PMADRH
accesses
20h-7Fh
File
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
11Fh
120h
Indirect addr.(*)
OPTION
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
PMCON1
accesses
A0h -BFh
accesses
40h -7Fh
File
Address
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
19Fh
1A0h
1BFh
1C0h
Bank 0
7Fh
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
DS39597B-page 8 2002 Microchip Technology Inc.
Bank 1
FFh
Bank 2
17Fh
Bank 3
1FFh
PIC16F72
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
(1)
00h
01h TMR0 Timer0 Module’s Register xxxx xxxx 29,13
02h
03h
04h
05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 23
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 25
08h — Unimplemented — —
09h — Unimplemented — —
0Ah
0Bh
0Ch PIR1
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 31
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 31
10h T1CON
11h TMR2 Timer2 Module’s Register 0000 0000 35
12h T2CON
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 43,48
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 45
15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 38,39,41
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 38,39,41
17h CCP1CON
18h-1Dh — Unimplemented — —
1Eh ADRES A/D Result Register xxxx xxxx 53
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
Legend: x = unknown, u = unchanged, q = value depend s on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: These registers can be addressed from any bank.
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19
(1)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 18
(1)
STATUS IRP RP1 RP0 TO P D Z DC C 0001 1xxx 12
(1)
FSR Indirect Data Memory Address Pointer xxxx xxxx 19
— — PORTA Data Latch when written: PORTA pins when read --0x 0000 21
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 18
(1)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14
— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 16
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 31
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 36
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 37
— ADON 0000 00-0 53
Shaded locations are unimplemented, read as ‘0’.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Th i s bi t always reads as a ‘1’.
Value on
POR, BOR
Details on
page:
2002 Microchip Technology Inc. DS39597B-page 9
PIC16F72
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
(1)
80h
81h OPTION RBPU
82h
83h
84h
85h TRISA
86h TRISB PORTB Data Direction Register 1111 1111 23
87h TRISC PORTC Data Direction Register 1111 1111 25
88h — Unimplemented — —
89h — Unimplemented — —
8Ah
8Bh
8Ch PIE1
8Dh — Unimplemented — —
8Eh PCON
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Regis ter 1111 1111 41
93h SSPADD Synchronous Serial Port (I
94h SSPSTAT SMP CKE D/A
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1
Legend: x = unknown, u = unchanged, q = value depend s on condition, - = unimplemented, read as ‘0’, r = reserved.
Note 1: These registers can be addressed from any bank.
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13
(1)
PCL Program Counter’s (PC) Least Significant Byte 0000 0000 18
(1)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12
(1)
FSR Indirect Data Memory Address Pointer xxxx xxxx 19
— — PORTA Data Direction Register --11 1111 21
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 18
(1)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14
— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 15
— — — — — — POR BOR ---- --qq 17
2
C mode) Address Register 0000 0000 43,48
PSR/WUA BF 0000 0000 44
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 54
Shaded locations are unimplemented, read as ‘0’.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Th i s bi t always reads as a ‘1’.
Value on
POR, BOR
Details on
page:
DS39597B-page 10 2002 Microchip Technology Inc.
PIC16F72
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Bank 2
(1)
100h
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19
101h TMR0 Timer0 Module’s Register xxxx xxxx 29
(1
102h
103h
104h
PCL Program Counter's (PC) Least Significant Byte 0000 0000 18
(1)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12
(1)
FSR Indirect Data Memory Address Pointer xxxx xxxx 19
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 23
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
(1,2)
10Ah
10Bh
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 18
(1)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14
10Ch PMDATL Data Register Low Byte xxxx xxxx 27
10Dh PMADRL Address Register Low Byte xxxx xxxx 27
10Eh PMDATH
10Fh PMADRH
— — Data Register High Byte --xx xxxx 27
— — — Address Register High Byte ---x xxxx 27
Bank 3
(1)
180h
181h OPTION RBPU
182h
183h
184h
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13
(1)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 18
(1)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12
(1)
FSR Indirect Data Memory Address Pointer xxxx xxxx 19
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 23
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
(1,2)
18Ah
18Bh
PCLATH — — —
(1)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14
18Ch PMCON1
—
(3)
— — — — — — RD 1--- ---0 27
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 18
18Dh — Unimplemented — —
18Eh — Reserved, maintain clear 0000 0000 —
18Fh — Reserved, maintain clear 0000 0000 —
Legend: x = unknown, u = unchanged, q = value depend s on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Th i s bi t always reads as a ‘1’.
Details on
page:
2002 Microchip Technology Inc. DS39597B-page 11
PIC16F72
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains
the arithmetic st atus of th e ALU, the RE SET statu s and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destinatio n may be different than
intended.
and PD bits are not
For example, CLRF STATUS will clear the up per three
bits and set t he Z bit. T his leaves the STA TUS reg ister
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the ST ATUS register . F or
other instructions, not affecting any status bits, see
Section 12.0, Instruction Set Summary.
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow
bit 0 C: Carry/borrow
: Tim e-out bit
1 = After power-up, CLRWDT instru cti on, or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
PD ZDCC
(1,2)
(1)
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand.
2: For rotate (RRF, RLF) i nstruc tions, th is bit is loade d with e ither th e high or low orde r
bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39597B-page 12 2002 Microchip Technology Inc.
2.2.2.2 OPTION Register
The OPTION register is a readable and writable register that contains various control bits to configure the
TMR0 prescaler/WDT postscaler (single assignable
register known also as the p res ca ler), the External INT
Interrupt, TMR0, and the weak pull-ups on PORTB.
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
REGISTER 2-2: OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU
bit 7 bit 0
INTEDG T0CS T0SE PSA PS2 PS1 PS0
PIC16F72
bit 7 RBPU
bit 6 INTEDG: Interrupt Edge Select bit
bit 5 T0CS: TMR0 Clock Source Select bit
bit 4 T0SE: TMR0 Source Edge Select bit
bit 3 PSA: Prescaler Assignment bit
bit 2-0 PS2:PS0: Prescaler Rate Select bits
: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock ( CLKO)
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. DS39597B-page 13
PIC16F72
2.2.2.3 INTCON Register
The INTCON Register is a readabl e and writ able register that contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
Note: Interrupt flag bits get set when an interru pt
condition occurs, re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-3: INTCON: INT ERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
A mismatch condit ion w il l c on tinu e t o s et flag bi t R BIF. Re adi ng PORTB will end the mismat ch
condition and allow flag bit RBIF to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39597B-page 14 2002 Microchip Technology Inc.
PIC16F72
2.2.2.4 PIE1 Regist er
This register contains the individual enable bits for the
peripheral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4 Unimplemented: Read as ‘0’
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enable s the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enable s the CCP1 interru pt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
ADIE
— —
SSPIE CCP1IE TMR2IE TMR1IE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. DS39597B-page 15
PIC16F72
2.2.2.5 PIR1 Register
This register contains the individual flag bits for the
Peripheral interrupts.
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT FLAG REGISTER 1 (ADDRESS 0Ch)
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D convers ion comp le ted
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ‘0’
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred, and must be cleared in software before re turning
from the Interrupt Service Routine.
The conditions that will set this bit are a transmission/reception has taken place.
0 = No SSP interrupt condition has occurred
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare mat c h occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39597B-page 16 2002 Microchip Technology Inc.
PIC16F72
2.2.2.6 PCON Register
Note: Interrupt flag bits get set when an interrupt
condition occur s, re ga rdle ss of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset, an external MCLR
and WDT Reset.
Reset
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOR
clear , indicati ng a brow n-out has occ urred.
The BOR status bit is a ‘don't care’ and is
not necessarily predic table if the brown-o ut
circuit is disabled (by clearing the BOREN
bit in the Configuration word).
REGISTER 2-6: PCON: POWER CONTROL REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x
— — — — — — POR BOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as ‘0’
bit 1 POR
bit 0 BOR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
is
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. DS39597B-page 17
PIC16F72
2.3 PCL and PCLATH
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13-bits
wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not d irec tly re ada ble or writable. All updates
to the PCH register go through the PCLATH register.
Figure 2-3 shows the four situations for the loading of
the PC.
• Example 1 shows how the PC is loa ded on a writ e
to PCL (PCLATH<4:0> → PCH).
• Example 2 shows how the PC is loaded during a
GOTO instruction (PCLATH<4:3> → PCH).
• Example 3 shows how the PC is loaded during a
CALL instruction (PCLATH<4:3> → PCH), with
the PC loaded (PUSH’d) onto the Top-of-Stack.
• Example 4 shows how the PC is loaded during
one of the return instructions, where the PC is
loaded (POP’d) from the Top-of-Stack.
FIGURE 2-3: LOADING OF PC IN DIFFERENT SITUATIONS
Example 1 - Instruction with PCL as destination
PCH PCL
12 8 7 0
PC
11
8
ALU result
Opcode <10:0>
PCLATH<4:0>
5
PCLATH
Example 2 - GOTO Instruction
PCH PCL
12 11 10 0
PC
2
87
PCLATH<4:3>
Stack (13-bits x 8)
Top-of-Stack
Stack (13-bits x 8)
Top-of-Stack
PCLATH
Example 3 - CALL Instruction
13
PCH PCL
12 11 10 0
PC
2
Example 4 - RETURN, RETFIE, or RETLW Instruction
12 11 10 0
PC
Note: PCLATH is not updated with the contents of PCH.
87
PCLATH
PCH PCL
87
PCLATH
11PCLATH<4:3>
11
Opcode <10:0>
13
Opcode <10:0>
Stack (13-bits x 8)
Top-of-Stack
Stack (13-bits x 8)
Top-of-Stack
DS39597B-page 18 2002 Microchip Technology Inc.
PIC16F72
2.3.1 COMPUTED GOTO
A computed GOTO is accomplish ed by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercise d i f the t able loca tio n cros ses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note, “Implementing a Table Read"
(AN556).
2.3.2 STACK
The stack allows a combination of up to eight program
calls and interrupts to occur. The stack contains the
return address from this branch in program execution.
Mid-range devices have an 8-level deep x 13-bit wide
hardware s tack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSH’d onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POP’d in the event of a
RETURN, RETLW or a RETFIE instruction ex ecution.
PCLATH is not modified when the stack is P USH’d or
POP’d.
After the stack has bee n PUSH ’d eight times, the ninth
push overwrites the v alue tha t was stored fro m the first
push. The tenth pus h ov erwri t es the se co nd p us h (an d
so on). An example of the overwriting of the stack is
shown in Figure 2-4.
FIGURE 2-4: STACK MODIFICATION
2.4 Program Memory Paging
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper two bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensu re tha t the p age select bits are
programmed so that the desired program memory
page is addressed. If a return from a CALL instruction
(or interrupt) is executed, the en tire 13-bit PC is pushed
onto the stack. Therefore, manipulation of the
PCLATH<4:3> bits is not required for the return
instructions (which POPs the address from the stack).
Note: The PIC16F72 device ignores th e paging
bit PCLATH<4:3>. The use of
PCLATH<4:3> as a general purpose read/
write bit is not recommended, since this
may affect upwa rd comp ati bility with future
products.
2.5 Indirect Addressing, INDF and FSR Registers
The INDF register is no t a phy sica l reg ist er. Addressing INDF actually addresses the register whose
address is contained in the FSR regis ter (FSR is a
pointer). This is indirect addressing.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
Stack
Push1 Push9
Push2 Push10
Push3
Push4
Push5
Push6
Push7
Push8
Note 1: There are no status bi ts to indi cate stack
overflow or stack underfl ow cond iti ons .
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
Top-of-Stack
EXAMPLE 2-1: INDIR ECT ADDRESS ING
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
An effective 9-bit address is obtai ned by conca tenating
the 8-bit FSR register and the IRP bi t (ST ATUS<7>), as
shown in Figure 2-5.
2002 Microchip Technology Inc. DS39597B-page 19
PIC16F72
FIGURE 2-5: DIRECT/INDIRECT ADDRESSING
RP1:RP 0 6
From Opcode
0
Indirect AddressingDirect Addressing
IRP FSR Register
7
0
Bank Select Location Select
00 01 10 11
80h
FFh
Data
Memory
00h
(1)
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: For register file map detail, see Figure 2-2.
100h
17Fh
180h
1FFh
Bank Select
Location Select
DS39597B-page 20 2002 Microchip Technology Inc.
PIC16F72
3.0 I/O PORTS
Some pins for th ese I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional inform atio n o n I/O ports may be found i n th e
PICmicro™ Mid-Range MCU Reference Manual,
(DS33023).
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PO RT A pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the correspondin g POR TA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register, reads the status of the
pins, whereas writing to i t will wri te to th e po rt latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an ope n drai n o utput.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and analog V
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
Note: On a Power-on Reset, these pins are c on-
The TRISA register controls the direction of the RA
pins, even when they are be ing us ed as ana lo g inputs.
The user must ensure the bits in the TRISA regi ster are
maintained set when using them as analog inputs.
EXAMPLE 3-1: INITIALIZING PORTA
BANKSEL PORTA ; select bank for PORTA
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BANKSEL ADCON1 ; Select Bank for ADCON1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ‘0’.
REF input. The operation of each pin is
figured as analog inputs and read as ‘0’.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
Data
Bus
WR
Port
WR
TRIS
RD Port
To A/D Converter
CK
Data Latch
CK
TRIS Latch
QD
Q
QD
Q
RD TRIS
VDD
DD
V
P
N
VSS
V
SS
Analog
Input
Mode
QD
EN
I/O pin
TTL
Input
Buffer
FIGURE 3-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data
Bus
WR
Port
WR
TRIS
RD Port
TMR0 Clock Input
QD
Q
CK
Data Latch
QD
Q
CK
TRIS Latch
RD TRIS
N
VSS
SS
V
Schmitt
Trigger
Input
Buffer
QD
EN
EN
I/O pin
2002 Microchip Technology Inc. DS39597B-page 21
PIC16F72
TABLE 3-1: PORTA FUNCTIONS
Name Bit# Buffer Function
RA0/AN0 bit 0 TTL Input/output or analog input.
RA1/AN1 bit 1 TTL Input/output or analog input.
RA2/AN2 bit 2 TTL Input/output or analog input.
RA3/AN3/VREF bit 3 TTL Input/output or analog input or VREF.
RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0. Output is open drain type.
RA5/AN4/SS bit 5 TTL Input/output or analog input or slave select input for synchronous serial port.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all other
RESETS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
05h PORTA
85h TRISA
9Fh ADCON1
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.
Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled , th e A/ D Po rt Conf igu rati on Con trol bits
(PCFG2:PCFG0) in the A/D C ontrol Re gister ( ADCON 1) must be set to o ne of the follow ing con figurat ion s:
100, 101, 11x.
— — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
— — PORTA Data Direction Register --11 1111 --11 1111
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
DS39597B-page 22 2002 Microchip Technology Inc.
PIC16F72
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding POR TB pin an output (i.e. , put
the contents of the output latch on the selected pin).
EXAMPLE 3-2: INITIALIZING PORTB
BANKSEL PORTB ; Select bank for PORTB
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BANKSEL TRISB ; Select Bank for TRISB
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pi ns has a w eak i nternal pul l-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU
pull-up is automatically turned off when the port pin is
configured as an outpu t. The pull-ups are disable d on a
Power-on Reset.
(OPTION<7>). The weak
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’d together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch c ond it i on wi ll cont i n ue to s et f lag bi t RB IF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt-on-mismatch feature, together with software configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION<6>).
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
DD
EN
TTL
Input
Buffer
V
Weak
P
Pull-up
RD Port
V
VSS
DD
I/O pin
(1)
RBPU
Data
Data Latch
Bus
WR
Port
WR
TRIS
RB0/INT
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION<7>).
CK
TRIS Latch
CK
RD TRIS
RD Port
QD
QD
QD
Schmitt Trigger
Buffer
Four of PORTB’s pins , RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
DD
TTL
Input
Buffer
EN
EN
V
P
Weak
Pull-up
V
DD
VSS
Buffer
Q1
RD Port
Q3
(1)
RBPU
Data
Bus
WR
Port
WR
TRIS
Set RBIF
From Other
RB7:RB4 Pins
RB7:RB6 in Serial Programming Mode
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
Data Latch
QD
CK
TRIS Latch
QD
CK
RD TRIS
RD Port
and clear the RBPU bit (OPTION<7>).
Latch
QD
QD
I/O pin
ST
2002 Microchip Technology Inc. DS39597B-page 23
PIC16F72
TABLE 3-3: PORTB FUNCTIONS
Name Bit# Buffer Function
RB0/INT bit 0 TTL/ST
RB1 bit 1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit 2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit 3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit 4 TTL Input/output pin (with interrupt-on-change). In ternal software pro grammable
RB5 bit 5 TTL Input/output pin (with interrupt-on-change). In ternal software pro grammable
RB6 bit 6 TTL/ST
RB7 bit 7 TTL/ST
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
weak pull-up.
weak pull-up.
(2)
Input/output pin (with interrup t-on-change). In ternal software pro grammable
weak pull-up. Serial pr ogramming clock.
(2)
Input/output pin (with interrup t-on-change). In ternal software pro grammable
weak pull-up. Serial programming data.
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION RBPU
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Value on
POR, BOR
Value on
all other
RESETS
DS39597B-page 24 2002 Microchip Technology Inc.
PIC16F72
3.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the correspondi ng PORTC pin an output (i.e., p ut
the contents of the output latch on the selected pin).
PORTC is mul tiplexed with s everal peri pheral function s
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bit s fo r each POR TC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination shoul d be avoided. The us er should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
EXAMPLE 3-3: INITIALIZING PORTC
BANKSEL PORTC ; Select Bank for PORTC
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
BANKSEL TRISC ; Select Bank for TRISC
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
Port/Peripheral Select
Peripheral Data Out
Data
Bus
WR
Port
WR
TRIS
Peripheral
(2)
OE
Peripheral Input
Note 1: Port/Peripheral select signal selects
CK
Data Latch
CK
TRIS Latch
RD TRIS
RD
Port
between port data and peripheral output.
2: Peripheral OE (output enable) is only
activated if peripheral select is active.
(1)
0
QD
1
Q
QD
Q
QD
EN
VSS
Schmitt
Trigger
DD
V
VDD
P
I/O
pin
VSS
N
2002 Microchip Technology Inc. DS39597B-page 25
PIC16F72
TABLE 3-5: PORTC FUNCTIONS
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI
RC1/T1OSI bit 1 ST Input/output port pin or Timer1 oscillator input.
RC2/CCP1 bit 2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
RC3/SCK/SCL bit 3 ST
RC4/SDI/SDA bit 4 ST
RC5/SDO bit 5 ST Input/output port pin or Synchronous Serial Port data output.
RC6 bit 6 ST Input/output port pin.
RC7 bit 7 ST Input/output port pin.
Legend: ST = Schmitt Trigger input
TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
bit 0
ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.
output.
RC3 can also be the synchronous serial clock for both SPI and I
modes.
RC4 can also be the SPI Data In (SPI mode) or data I/O (I
Value on
POR, BOR
2
2
C mode).
Value on
all other
RESETS
C
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged
DS39597B-page 26 2002 Microchip Technology Inc.
PIC16F72
4.0 READING PROGRAM MEMORY
The FLASH Program Memory is readable during normal operation over the entire V
addressed through Special Function Registers (SFR).
Up to 14-bit wide num bers can be sto red in mem ory for
use as calibration parameters, serial numbers, packed
7-bit ASCII, etc. Exe cut ing a p rogram memory location
containing data that forms an invalid instruction results
in a NOP.
There are five SFRs used to read the program and
memory:
• PMCON1
• PMDATL
• PMDATH
• PMADRL
• PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading calibration t abl es .
When interfacing to the program memory block, the
PMDATH:PMDATL registers form a two-byte word,
which holds the 14-bit data for reads. The
PMADRH:PMADRL registers form a two-byte word,
which holds the 13-bit address of the FLASH location
being accessed. This device has up to 2K words of
program FLASH, with an address range from 0h to
07FFh. The unused upper bits PMDATH<7:6> and
PMADRH<7:5> are not implemented and read as
zeros.
DD range. It is indirectly
4.1 PMADR
The address registers can address up to a maxim um of
8K words of program FLASH.
When selecting a program address value, the MSByte
of the address is written to the PMADRH register and
the LSByte is written to the PMADRL register. The
upper MSbits of PMADRH must always be clear.
4.2 PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cleared, only set, in so ftware . I t is cleare d in
hardware at the completion of the read operation.
REGISTER 4-1: PMCON1: PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS 18Ch)
R-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0
reserved — — — — — — RD
bit 7 bit 0
bit 7 Reserved: Read as ‘1’
bit 6-1 Unimplemented: Read as ‘0’
bit 0 RD: Read Control bit
1 = Initiates a FLASH read, RD is cleare d in hard ware. Th e RD bit c an only be set (not cleared )
in software.
0 = Does not initiate a FLASH read
Legend:
W = Writable bit U = Unimplemented bit, read as ‘0’
R = Readable bit S = Settable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. DS39597B-page 27
PIC16F72
4.3 Reading the FLASH Program Memory
To read a program memory location, the user must
write two bytes of the address to the PMADRL and
PMADRH registers and then set control bit, RD
(PMCON1<0>). Once the read control bit is set, the
program memory F LASH con trol ler will use t he se cond
instruction cycle afte r to read the data . This ca uses the
second instruction immediately following the “BSF
PMCON1,RD” instruction to be ignored. The data is
available in the very next cycle in the PMDATL and
PMDATH registers; therefore, it can be read as two
bytes in the following instructions. PMDATL and
PMDATH registers will hold this value until another
read, or until it is written to by the user (during a write
operation).
4.4 Operation During Code Protect
The FLASH program memory control can read anywhere within the program memory, whether or not the
program memory is code protected.
This does not compromise the code, because there is
no way to rewrite a portion of the program memory, or
leave contents of a progra m me mo ry read in a regist er
while changing modes.
EXAMPLE 4-1: FLASH PROGRAM READ
BANKSEL PMADRH ; Select Bank for PMADRH
MOVLW MS_PROG_EE_ADDR ;
MOVWF PMADRH ; MS Byte of Program Address to read
MOVLW LS_PROG_EE_ADDR ;
MOVWF PMADRL ; LS Byte of Program Address to read
BANKSEL PMCON1 ; Select Bank for PMCON1
BSF PMCON1, RD ; EE Read
;
NOP ; Any instructions here are ignored as program
NOP ; memory is read in second cycle after BSF PMCON1,RD
;
; First instruction after BSF PMCON1,RD executes normally
BANKSEL PMDATL ; Select Bank for PMDATL
MOVF PMDATL, W ; W = LS Byte of Program PMDATL
MOVF PMDATH, W ; W = MS Byte of Program PMDATL
TABLE 4-1: REGISTERS ASSOCIATED WITH PROGRAM FLASH
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
10Dh PMADRL Address Register Low Byte xxxx xxxx uuuu uuuu
10Fh PMADRH
10Ch PMDATL Data Register Low Byte xxxx xxxx uuuu uuuu
10Eh PMDATH — — Data Register High Byte xxxx xxxx uuuu uuuu
18Ch PMCON1
Legend: x = unknown, u = unchanged, r = reserved , - = unim pleme nted, read as ' 0'.
Shaded cells are not used during FLASH access.
Note 1: This bit always reads as a ‘1’.
DS39597B-page 28 2002 Microchip Technology Inc.
— — — Address Register High Byte xxxx xxxx uuuu uuuu
(1)
—
— — — — — — RD 1--- ---0 1--- ---0
Value on
POR, BOR
Value on
all other
RESETS
Loading...