MICROCHIP PIC16F688 Technical data

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PIC16F688

Data Sheet

14-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

nanoWatt Technology

Note the following details of the code protection feature on Microchip devices:

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• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, an d SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

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Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartT el, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

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All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC® DSCs, KEELOQ EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

code hopping devices, Serial

PIC16F688

14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

High-Performance RISC CPU:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instr uction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%

- Software selectable frequency range of 8 MHz to 125 kHz

- Software tunable

- Two-Speed Start-Up mo de

- Crystal fail detect for critical applications

- Clock mode switching during operation for power savings

• Power-Saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended tempera ture range

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Brown-out Reset (BOR) with software control option

• Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable

• Multiplexed Master Clear with weak pull-up or input only pin

• Programmable code protection

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

Low-Power Features:

• Standby Current:

- 50 nA @ 2.0V, typical

• Operating Current:

-11μA @ 32 kHz, 2.0V, typical

-220μA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

Peripheral Features:

• 12 I/O pins with indiv idual direction control:

- High-current source/sink for direct LED drive

- Interrupt-on-change pin

- Individually programmable weak pull-ups

- Ultra Low-Power Wake-up

• Analog Comparator module with:

- Two analog comparators

- Programmable On-chip Voltage Reference (CV

REF) module (% of VDD)

- Comparator inputs and outputs externally accessible

• A/D Converter:

- 10-bit resolution and 8 channels

• Timer0: 8-bit timer/counter with 8-bit programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Timer1 Gate (count enable)

- Option to use OSC1 and OSC2 in LP mode as

Timer1 oscillator if INTOSC mode selected

• Enhanced USART Module:

- Supports RS-485, RS-232, and LIN 1.2

- Auto-Baud Detect

- Auto-wake-up on Start bit

• In-Circuit Serial Programming™ (ICSP™) via two pins

Program

Memory

Device

Flash

(words)

PIC16F688 4096 256 256 12 8 2 1/1

Data Memory

SRAM (bytes)

EEPROM

(bytes)

I/O

10-bit A/D

(ch)

Comparators

Timers

8/16-bit

PIC16F688

Pin Diagram (PDIP, SOIC, TSSOP)

14-pin PDIP, SOIC, TSSOP

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G

/OSC2/CLKOUT

RA3/MCLR

RC4/C2OUT/TX/CK

VDD

/VPP

RC5/RX/DT

RC3/AN7

1 2 3 4

5 6 7

14 13 12 11 10

PIC16F688

9 8

VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C1IN-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C2INRC2/AN6

TABLE 1: PIC16F688 14-PIN SUMMARY (PDIP, SOIC, TSSOP)

I/O Pin Analog Comparators Timers EUSART Interrupt Pull-up Basic

RA0 13 AN0/ULPWU C1IN+ — — IOC Y ICSPDAT RA1 12 AN1 C1IN- — — IOC Y V RA2 11 AN2 C1OUT T0CKI — IOC/INT Y — RA3 4 — — — — IOC Y RA4 3 AN3 — T1G — IOC Y OSC2/CLKOUT RA5 2 — — T1CKI — IOC Y OSC1/CLKIN RC0 10 AN4 C2IN+ — — — — — RC1 9 AN5 C2IN- — — — — — RC2 8 AN6 — — — — — — RC3 7 AN7 — — — — — — RC4 6 — C2OUT — TX/CK — — — RC5 5 — — — RX/DT — — —

— 1 — — — — — — VDD —14 — — — — — — VSS

Note 1: Pull-up activated only with external MCLR configuration.

(1)

REF/ICSPCLK

MCLR/VPP

Pin Diagram (QFN)

16-pin QFN

VDD

NCNCVSS

PIC16F688

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G

/OSC2/CLKOUT

RA3/MCLR

/VPP

RC5/RX/DT

1 2

PIC16F688

3 4

RC4/C2OUT/TX/CK

RC3/AN7

RC2/AN6

RC1/AN5/C2IN-

RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C1IN-/V RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

REF/ICSPCLK

T ABLE 2: PIC16F688 16-PIN SUMMARY (QFN)

I/O Pin Analog Comparators Timers EUSART Interrupt Pull-up Basic

RA0 12 AN0/ULPWU C1IN+ — — IOC Y ICSPDAT RA1 11 AN1 C1IN- — — IOC Y VREF/ICSPCLK RA2 10 AN2 C1OUT T0CKI — IOC/INT Y — RA3 3 — — — — IOC Y RA4 2 AN3 — T1G — IOC Y OSC2/CLKOUT RA5 1 — — T1CKI — IOC Y OSC1/CLKIN RC0 9 AN4 C2IN+ — — — — — RC1 8 AN5 C2IN- — — — — — RC2 7 AN6 — — — — — — RC3 6 AN7 — — — — — — RC4 5 — C2OUT — TX/CK — — — RC5 4 — — — RX/DT — — —

— 16 — — — — — — VDD —13 — — — — — — VSS — 14 — — — — — — NC —15 — — — — — — NC

Note 1: Pull-up activated only with external MCLR

configuration.

(1)

MCLR/VPP

PIC16F688

Table of Contents

1.0 Device Overview ......................................................................................................................................................................... 5

2.0 Memory Organization. ................................................................................................................................................................. 7

3.0 Clock Sources ........................................................................................................................................................................... 21

4.0 I/O Ports .................................................................................................................................................................................... 33

5.0 Timer0 Module .......................................................................................................................................................................... 45

6.0 Timer1 Module with Gate Control.............................................................................................................................................. 49

7.0 Comparator Module............................................................. .. ......... .... .. .... .... ....... .... .. .... .... ........................................................ 55

8.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................. 65

9.0 Data EEPROM and Flash Program Memory Control................................................................................................................ 77

10.0 Enhanced Universal Asynchronous Receiver Transmitter (EUSART) ...................................................................................... 83

11.0 Special Features of the CPU......................................... .......................................................................................................... 109

12.0 Instruction Set Summary......................................................................................................................................................... 129

13.0 Development Support .............................................................................................................................................................. 139

14.0 Electrical Specifications........................................................................................................................................................... 143

15.0 DC and AC Characteristics Graphs and Tables...................................................................................................................... 163

16.0 Packaging Information...................................................................... ....................................................................................... 185

Appendix A: Data Sheet Revision History......................................................................................................................................... 191

Appendix B: Migrating from other PIC® Devices................................................................................. ............................................. 191

Index ................................................................................................................................................................................................. 193

On-line Support .................................................................................................................................................................................197

Systems Information and Upgrade Hot Line..................................................................................................................................... 197

Reader Response............................................................................................................................................................................. 198

Product Identification System............................................................................................................................................................ 199

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Customer Notification System

1.0 DEVICE OVERVIEW

The PIC16F688 is covered by this data sheet. It is available in 14-pin PDIP, SOIC, TSSOP and QFN packages. Figure 1-1 shows a block diagram of the PIC16F688 device. Table 1-1 shows the pinout description.

FIGURE 1-1: PIC16F688 BLOCK DIAGRAM

PIC16F688

OSC1/CLKIN

OSC2/CLKOUT

T1G

Program

Bus

Internal

Oscillator

Block

Configuration

Flash 4k x 14

Program

Memory

Instruction Reg

Instruction

Decode &

Control

Timing

Generation

MCLR

INT

Program Counter

8-Level Stack

(13 bit)

Direct Addr

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VSS

RAM Addr

Data Bus

RAM

256 bytes

File

Registers

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

RX/DT TX/CK

PORTA

RA0 RA1 RA2 RA3 RA4 RA5

PORTC

RC0 RC1 RC2 RC3 RC4 RC5

T1CKI

T0CKI

VREF

Timer0 Timer1

Analog-to-Digital Converter

AN0 AN1 AN2 AN3

AN4 AN5 AN6 AN7

Analog Comparators

and Referen ce

C1IN- C1IN+ C1OUT

C2IN- C2IN+ C2OUT

EUSART

EEDAT

256 bytes

EEPROM

EEADDR

DATA

PIC16F688

TABLE 1-1: PIC16F688 PINOUT DESCRIPTION

Name Function

RA0/AN0/C1IN+/ICSPDAT/ULPWU RA0 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change

AN0 AN — A/D Channel 0 input

C1IN+ AN — Comparator 1 input

ICSPDAT TTL CMOS Serial Programming Data I/O

ULPWU AN — Ultra Low-Power Wake-up input

RA1/AN1/C1IN-/V

RA2/AN2/T0CKI/INT/C1OUT R A 2 ST CMOS PORTA I/O w/prog pull-up and interrupt-on-change

RA3/MCLR

RA4/AN3/T1G

RA5/T1CKI/OSC1/CLKIN

RC0/AN4/C2IN+ RC0 TTL CMOS PORTC I/O

RC1/AN5/C2IN- RC1 TTL CMOS PORTC I/O

RC2/AN6 RC2 TTL CMOS PORTC I/O

RC3/AN7 RC3 TTL CMOS PORTC I/O

RC4/C2OUT/TX/CK RC4 TTL CMOS PORTC I/O

RC5/RX/DT RC5 TTL CMOS Port C I/O

SS VSS Power — Ground reference

DD VDD Power — Positive supply

V Legend: AN = Analog input or output CMOS = CMOS compatible input or output OC = Open collector output

REF/ICSPCLK RA1 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change

AN1 AN — A/D Channel 1 input

C1IN- AN — Comparator 1 input

REF AN — External Voltage Reference for A/D

ICSPCLK ST — Serial Programming Clock

AN2 AN — A/D Channel 2 input

T0CKI ST — Timer0 clock input

INT ST — External Interrupt

C1OUT — CMOS Comparator 1 output

/VPP RA3 TTL — PORTA input with interrupt-on-change

MCLR

PP HV — Programming voltage

/OSC2/CLKOUT RA4 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change

AN3 AN — A/D Channel 3 input T1G

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS F

RA5 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change T1CKI ST — Timer1 clock OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection

AN4 AN — A/D Channel 4 input C2IN+ AN Comparator 2 input

AN5 AN — A/D Channel 5 input

C2IN- AN Comparator 2 input

AN6 AN — A/D Channel 6 input

AN7 AN — A/D Channel 7 input

C2OUT — CMOS Comparator 2 output

TX — CMOS USART asynchronous output CK ST CMOS USART asynchronous clock

RX ST CMOS USART asynchronous input DT S T CMOS USART asynchronous data

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal

Input

Type

ST — Master Clear w/internal pull-up

ST — Timer1 gate

Output

Type

Description

OSC/4 output

PIC16F688

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F688 has a 13-bit program counter capable of addressin g a 4 K x 14 prog r a m memo r y spac e. On ly the first 4K x 14 (0000h-01FFF) for the PIC16F688 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 4K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).

FIGURE 2-1 : PR OG RA M M EMO RY MA P

AND STACK FOR THE PIC16F688

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1 Stack Level 2

Stack Level 8

Reset Vector

0000h

2.2 Data Memory Organization

The data memory is partitioned into multiple banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP0 and RP1 are bank select bits.

RP1

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Abo ve the Speci al Function Re gisters are th e Genera l Purpos e Regist ers, im plement ed as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank are mirrored in another bank for code reduction and quicker access.

2.2.1 GENERAL PURPOSE REGISTER

The register file is organized as 256 x 8 in the PIC16F688. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”).

RP0

00→ Bank 0 is selected 01→ Bank 1 is selected 10→ Bank 2 is selected 11→ Bank 3 is selected

FILE

Interrupt Vector

On-chip Program

Memory

Wraps to 0000h-07FFh

0004h 0005h

01FFh 02000h

1FFFh

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Tables 2-1, 2-2,

2-3 and 2-4). These registers are static RAM.

The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “c ore” are des cribed in thi s sectio n. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

PIC16F688

FIGURE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS

File File File File Address Address Address Address

Indirect addr.

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h PORTA 105h TRISA 185h

PORTC 07h TRISC 87h PORTC 107h TRISC 187h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch

TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh T1CON 10h OSCTUNE 90h

BAUDCTL 11h ANSEL 91h 111h 191h

SPBRGH 12h 92h 112h 192h

SPBRG 13h RCREG 14h 94h 114h 194h

TXREG 15h WPUA 95h 115h 195h

TXSTA 16h IOCA 96h RCSTA 17h EEDATH 97h 117h 197h

WDTCON 18h EEADRH 98h 118h 198h

CMCON0 19h VRCON 99h CMCON1 1Ah EEDAT 9Ah 11Ah 19Ah

ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh ADCON0 1Fh ADCON1 9Fh

(1)

00h Indirect addr.

06h 86h 106h 186h

08h 88h 108h 188h 09h 89h 109h 189h

0Dh 8Dh 10Dh 18Dh

1Bh EEADR 9Bh 11Bh 19Bh 1Ch EECON1 9Ch 11Ch 19Ch 1Dh EECON2

20h

(1)

80h Indirect addr.

93h 113h 193h

(1)

9Dh 11Dh 19Dh

A0h

(1)

100h Indirect addr.

10Ch 18Ch

110h 190h

116h 196h

119h 199h

11Fh 19Fh 120h

(1)

180h

1A0h

General

General Purpose Register

96 Bytes

7Fh FFh 17Fh 1FFh

Bank 0Bank 1Bank 2Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

Purpose Register

80 Bytes

accesses

Bank 0

EFh 16Fh F0h accesses

General Purpose Register

80 Bytes

Bank 0

170h accesses

Bank 0

1EFh 1F0h

PIC16F688

TABLE 2-1: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117 01h TMR0 Timer0 Module’s register xxxx xxxx 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 03h STATUS IRP RP1 RP0 TO 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 05h PORTA 06h — Unimplemented — — 07h PORTC 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h BAUDCTL ABDOVF RCIDL 12h SPBRGH USART Baud Rate High Generator 0000 0000 95, 117 13h SPBRG USART Baud Rate Generator 0000 0000 95, 117 14h RCREG USART Receive Register 0000 0000 87, 117 15h TXREG USART Transmit Register 0000 0000 87, 117 16h TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 92, 117 17h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 93, 117 18h WDTCON 19h CMCON0 C2OUT C1OUT 1Ah CMCON1 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 1Fh ADCON0 ADFM VCFG

Legend: – = Unimplemented locations rea d as ‘0’, u = unchanged, x = unknow n, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

mismatched exists.

— — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000

— — RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 42, 117

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000

EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 17, 117

— SCKP BRG16 —WUEABDEN01-0 0-00 94, 117

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 124, 117

C2INV C1INV CIS CM2 CM1 CM0 0000 0000 61, 117

— — — — — — T1GSS C2SYNC ---- --10 62, 117

— CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000

Reset and Watchdog Timer Reset dur ing nor mal operation.

and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the

PD ZDCC0001 1xxx 13, 117

TMR1CS TMR1ON 0000 0000 51, 117

Value on

POR/BOR

(2)

0000 000x 15, 117

Page

45, 117 19, 117

20, 117 33, 117

19, 117

48, 117 48, 117

72, 117 71, 117

PIC16F688

TABLE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117 81h OPTION_REG RAPU 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19, 117 83h STATUS IRP RP1 RP0 TO 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 20, 117 85h TRISA 86h — Unimplemented — — 87h TRISC 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 8Ch PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 16, 117 8Dh — Unimplemented — — 8Eh PCON 8Fh OSCCON 90h OSCTUNE 91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 34, 118 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h WPUA 96h IOCA 97h EEDATH 98h EEADRH 99h VRCON VREN 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 78, 118 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 78, 118 9Ch EECON1 EEPGD 9Dh EECON2 EEPROM Control 2 Register (not a physical register) ---- ---- 77, 118 9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 72, 118 9Fh ADCON1

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR

(2)

2: RA3 pull-up is enabled when pin is configured as MCLR 3: MCLR

and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the

mismatched exists.

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14, 117

PD ZDCC0001 1xxx 13, 117

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 33, 117

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 42, 117

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 19, 117

— — ULPWUE SBOREN — —PORBOR --01 --qq 18, 117 — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 22, 118 — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 26, 118

— — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 35, 118 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 35, 118 — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 78, 118 — — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 78, 118

—VRR — VR3 VR2 VR1 VR0 0-0- 0000 63, 118

— — — WRERR WREN WR RD x--- x000 79, 118

— ADCS2 ADCS1 ADCS0 — — — — -000 ---- 71, 118

Reset and Watchdog Timer Reset during normal operation.

in the Configuration Word register.

Value on

POR/BOR

(3)

0000 000x 15, 117

Page

PIC16F688

TABLE 2-3: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2

AddrNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0

Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117 101h TMR0 Timer0 Module’s register xxxx xxxx 45, 117 102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19, 117 103h STATUS IRP RP1 RP0 TO 104h FSR Indirect Data Memory Address Pointer xxxx xxxx 20, 117 105h PORTA 106h — Unimplemented — — 107h PORTC 108h — Unimplemented — — 109h — Unimplemented — — 10Ah PCLATH 10Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 10Ch — Unimplemented — — 10Dh — Unimplemented — — 10Eh — Unimplemented — — 10Fh — Unim plemented — — 110h — Unimplemented — — 111h — Unimplemented — — 112h — Unimplemented — — 113h — Unimplemented — — 114h — Unimplemented — — 115h — Unimplemented — — 116h — Unimplemented — — 117h — Unimplemented — — 118h — Unimplemented — — 119h — Unimplemented — — 11Ah — Unimplemented — — 11Bh — Unimplemented — — 11Ch — Unimplemented — — 11Dh — Unimplemented — — 11Eh — Unimplemented — — 11Fh — Unimplemented — —

Legend: – = Unimplemented locations rea d as ‘0’, u = unchanged, x = unknow n, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

mismatched exists.

— — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000

— — RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 42, 117

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 19, 117

Reset and Watchdog Timer Reset dur ing nor mal operation.

and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the

PD ZDCC0001 1xxx 13, 117

Value on

POR/BOR

(2)

0000 000x 15, 117

Page

33, 117

PIC16F688

TABLE 2-4: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117 181h OPTION_REG RAPU 182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19, 117 183h STATUS IRP RP1 RP0 TO 184h FSR Indirect Data Memory Address Pointer xxxx xxxx 20, 117 185h TRISA 186h — Unimplemented — — 187h TRISC 188h — Unimplemented — — 189h — Unimplemented — — 18Ah PCLATH 18Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 18Ch — Unimplemented — — 18Dh — Unimplemented — — 190h — Unimplemented — — 191h — Unimplemented — — 192h — Unimplemented — — 193h — Unimplemented — — 194h — Unimplemented — — 195h — Unimplemented — — 196h — Unimplemented — — 19Ah — Unimplemented — — 19Bh — Unimplemented — — 199h — Unimplemented — — 19Ah — Unimplemented — — 19Bh — Unimplemented — — 19Ch — Unimplemented — — 19Dh — Unimplemented — — 19Eh — Unimplemented — — 19Fh — Unimplemented — —

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power- up) Resets includ e M C LR

2: MCLR

and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the

mismatched exists.

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14, 117

PD ZDCC0001 1xxx 13, 117

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 33, 117

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 42, 117

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 19, 117

Reset and Watchdog Timer Reset during normal operation.

Value on

POR/BOR

(2)

0000 000x 15, 117

Page

PIC16F688

2.2.2.1 STATUS Register

The STATUS register, shown i n R e gis ter2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (SRAM) The STATUS register can be the destination for any

instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destin ation may be diffe rent than intended.

and PD bits are not

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any S t atus bi ts (see Sec tion 12.0 “Instruction Set

Summary”).

Note 1: Bits IRP and RP1 of the ST ATUS register

are not used by the PIC16F688 and should be maintained as clear. Use of these bits is n ot reco mmen ded, s ince this may affect upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PD ZDC

(1)

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh)

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow

For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

(1)

PIC16F688

2.2.2.2 OPTION Register

The OPTION register is a readable and writable register, which contains various control bits to configure:

• Timer0/WDT prescaler

• External RA2/INT interrupt

•Timer0

• Weak pull-ups on PORTA

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

INTEDG T0CS T0SE PSA PS2 PS1 PS0

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. See Section 5.1.3 “Software Programmable Prescaler”.

bit 7 RAPU

: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on R A2/T0CKI pi n 0 = Internal instruction cycle clock (F

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

OSC/4)

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

PIC16F688

2.2.2.3 INTCON Register

The INTCON register is a readable and writable register , which c ontains the various en able and fl ag bit s for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regard less of the st ate of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensu re the appropriate interrupt flag bits are clear prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RAIE T0IF INTF RAIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: Timer0 Overfl ow Interru pt E nab le bit

1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt

bit 4 INTE: RA2/INT External Interrupt Enable bit

1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt

bit 3 RAIE: PORTA Change Interrupt Enable bit

1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit

1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow

bit 1 INTF: RA2/INT External Interrupt Flag bit

1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur

bit 0 RAIF: PORTA Change Interrupt Flag bit

1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state

(1)

(2)

Note 1: IOCA register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

PIC16F688

2.2.2.4 PIE1 Register

The PIE1 register contai ns th e in terru pt enable bits, as shown in Register 2-4.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt 0 = Disables the ADC interrupt

bit 5 RCIE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt

bit 4 C2IE: Comparator 2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt

bit 3 C1IE: Comparator 1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt

bit 2 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt

bit 1 TXIE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIC16F688

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.

R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0

EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started

bit 5 RCIF: EUSART Receive Interrupt Flag bit

1 = The EUSART receive buffer is full (cleared by reading RCREG) 0 = The EUSART receive buffer is not full

bit 4 C2IF: Comparator C2 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed

bit 3 C1IF: Comparator C1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed

bit 2 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating

bit 1 TXIF: EUSART Transmit Interrupt Flag bit

1 = The EUSART transmit buffer is empty (cleared by writing to TXREG) 0 = The EUSART transmit buffer is full

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow

Note: Interrupt flag bits are set when an interrupt

condition occurs, regar dless of the st ate of its corresponding enable bit or the global enable bit, GIE bit of the I NTC ON r egiste r. User software shoul d ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

PIC16F688

2.2.2.6 PCON Register

The Power Control (PCON) register (see Register 2-6) contains flag bit s to differentiate between a:

Reset

)

(1)

— —PORBOR

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR The PCON register also controls the Ultra Low-Power

Wake-up and software enable of the BOR

U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x

— — ULPWUE SBOREN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit

1 = Ultra low-power wake-up enabled 0 = Ultra low-power wake-up disabled

bit 4 SBOREN: Software BOR Enable bit

1 = BOR enabled 0 = BOR disabled

bit 3-2 Unimplemented: Read as ‘0’ bit 1 POR

bit 0 BOR

Note 1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

(1)

PIC16F688

h s n

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-3: LO AD IN G O F P C IN

DIFFERENT SI T UA T IONS

PCH PCL

12 8 7 0

PCLATH<4:0>

PCLATH

PCH PCL

12 11 10 0

PCLATH<4:3>

Instruction wit

PCL a

Destinatio

ALU Result

GOTO, CALL

OPCODE<10:0>

2.3.2 STACK

The PIC16F688 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operat es as a circular buf fer . This means th at after the stack has been PUSHed eight times, the ninth push overwrites th e valu e that was s tored fro m the firs t push. The tenth pus h ov erwr i tes the se co nd push (and so on).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interrupt address.

PCLATH

2.3.1 COMPUTED GOTO

A computed GOTO is accomplish ed by adding an offs et to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercise d i f the t able loca tio n cros ses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556).

PIC16F688

2.4 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physi cal register. Addres sing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be

A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next

CONTINUE ;yes continue

affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit of the STATUS register, as shown in Figure 2-4.

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F688

RP1 RP0 6

Bank Select Location Select

From Opcode

00h

00 01 10 11

IRP File Select Register

Bank Select

180h

Indirect AddressingDirect Addressing

Location Select

Data Memory

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Note: For memory map detail, see Figure 2-2.

1FFh

PIC16F688

3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

3.1 Overview

The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applicati ons while maximiz ing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module.

Clock sources can be configured from external oscillators, quartz cryst al resonators , ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds select able via software. Additional clo ck feat ures inc lud e:

• Selectable system clock source between external

or internal via software.

• Two -Spe ed Start-Up mo de, whic h min im iz es

latency between external oscillator start-up and code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator.

The Oscillator mod ule can be c onfigured in one of eig ht clock modes.

1. EC – External clock with I/O on OSC2/CLKOUT.

2. LP – 32 kHz Low-Power Crystal mode.

3. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode.

4. HS – High Gain Crystal or Ceramic Resonator mode.

5. RC – External Resistor-Capacitor (RC) with

OSC/4 output on OSC2/CLKOUT.

6. R CIO – External Resistor- Capacitor (RC) with I/O on OSC2/CLKOUT.

7. INTOSC – Internal oscillator with F

OSC/4 output

on OSC2 and I/O on OSC1/CLKIN.

8. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT.

Clock Source modes are configured by the FOSC <2:0> bits in the Configuration Word register (CONFIG). The internal clock can be generated from two internal oscillators. The HFINTOSC is a calibrated highfrequency oscillator. The LFINTOSC is an uncalibrated low-frequency oscillator.

FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

External Oscillator

OSC2

OSC1

Internal Oscillator

HFINTOSC

8 MHz

LFINTOSC

31 kHz

Sleep

Postscaler

IRCF<2:0>

(OSCCON Register)

8 MHz 4 MHz 2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

31 kHz

111

110

101

100

011

010

001

000

LP, XT, HS, RC, RCIO, EC

MUX

FOSC<2:0>

(Configuration Word Register)

SCS<0>

(OSCCON Register)

MUX

(CPU and Peripherals)

INTOSC

Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)

System Clock

PIC16F688

3.2 Oscillator Control

The Oscillator Control (OSCCON) register (Figure3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits:

• Frequency selection bits (IRCF)

• Frequency Status bits (HTS, LTS)

• System clock control bits (OSTS, SCS)

U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0

(1)

HTS LTS SCS

— IRCF2 IRCF1 IRCF0 OSTS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits

111 =8MHz 110 = 4 MHz (default) 101 =2MHz 100 =1MHz 011 =500kHz 010 =250kHz 001 =125kHz 000 = 31 kHz (LFINTOSC)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)

bit 2 HTS: HFINTOSC Status bit (High Frequency – 8MHz to 125 kHz)

1 = HFINTOSC is stable 0 = HFINTOSC is not stable

bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)

1 = LFINTOSC is stable 0 = LFINTOSC is not stabl e

bit 0 SCS: Syst em Clock Select bit

1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> of the Configuration Word

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

PIC16F688

3.3 Clock Source Modes

Clock Source modes can be classified as external or internal.

• External Clock mod es rely on e xternal circui try fo r the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits.

• Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and the 31 kHz Low-Freq uency Inte rnal Osci llator (LFINTOSC).

The system clock can be selected between extern al or internal clock sources via the System Clock Select (SCS) bit of the OSCCON register. See Section 3.6

“Clock Switching” for additional information.

3.4 External Clock Modes

3.4.1 OSCILLATOR START-UP TIMER (OST)

If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator o r ce ramic res onator, has started and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1.

In order to minimize laten cy between externa l oscillator start-up and code execution, the Two-Speed Clock Start -up mode ca n be selected (s ee Section 3.7 “Two-

Speed Clock Start-up Mode”).

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay

Sleep/POR Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles

LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each

Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)

LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 μs (approx.)

LFINTOSC HFINTOSC

31 kHz

125 kHz to 8 MHz

Oscillator Warm-Up Delay (T

WARM)

3.4.2 EC MODE

The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

MCU design is fully

FIGURE 3-2: EXTERNAL CLOCK (EC)

MODE OPERATION

Clock from Ext. System

I/O

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

OSC1/CLKIN

PIC

MCU

OSC2/CLKOUT

(1)

PIC16F688

3.4.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figu re 3-3). The mod e selects a low , medium or high gain setting of the internal inverteramplifier to support v arious resonato r types and spee d.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonator s with a low drive lev el specification, for example, tuning fork type crystals. This mode is designed to drive only 32.768 kHz tuningfork type crystals (watch crystals).

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medi um of the three modes. This mode is best suited to drive resonators with a medium drive level specification.

HS Oscillator mode select s the highest gain setting of the internal inverter-amplifie r. H S mode current consum ption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting.

Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively.

Note 1: Quartz cryst al characterist ics vary accor ding

to type, package and manufacturer. The user should consult the manu facturer data sheets for sp ecifica tions and re comm ende d application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

and PIC®

Devices” (DS00826)

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work” (DS00949)

FIGURE 3-4: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

FIGURE 3-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

PIC® MCU

OSC1/CLKIN

Quartz Crystal

Note 1: A series resistor (RS) may be required for

2: The value of R

(1)

quartz crystals with low drive level.

selected (typically between 2 MΩ to 10 MΩ).

F varies with the Oscillator mode

(2)

OSC2/CLKOUT

To Internal Logic

Sleep

PIC® MCU

OSC1/CLKIN

(3)

Ceramic Resonator

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

selected (typically between 2 MΩ to 10 M Ω).

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator operation.

(1)

F varies with the Oscillator mode

(2)

OSC2/CLKOUT

To Internal Logic

Sleep

PIC16F688

3.4.4 EXTERN AL RC MODES

The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO.

In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the external RC mode connections.

FIGURE 3-5: EXTERNAL RC MODES

VDD

REXT

OSC1/CLKIN

CEXT

VSS

OSC/4 or

(2)

I/O

Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V

Note 1: Alternate pin functions are listed in

2: Output depends upon RC or RCIO clock mod

OSC2/CLKOUT

Section 1.0 “Device Overview”.

In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin.

The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacito r (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance The user also needs to take into account variation due

to tolerance of external RC components used.

PIC® MCU

(1)

3 kΩ ≤ R C

EXT ≤ 100 kΩ, 3-5V

EXT > 20 pF, 2-5V

Internal

Clock

3.5 Internal Clock Modes

The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source.

1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequ ency of t he HFINT OSC can be user-adju ste d via software using the OSCTUNE register (Register 3-2).

2. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz.

The system cloc k speed ca n be selec ted via sof tware using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register.

The system clock ca n be se lec ted betw ee n external or internal cloc k sourc es via th e System Cl ock Select ion (SCS) bit of the OSCCON register. See Section 3.6 “Clock Switching” for more information.

3.5.1 INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is progra mmed usi ng the osc illator se lectio n or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 11.0 “Special Features of the CPU” for more information.

In INTOSC mode, OSC1/CLKIN i s available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator fre quency divide d by 4. The CLKO UT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements.

In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O.

3.5.2 HFINTOSC

The High-Frequency Int ernal Oscillato r (HFINT OSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 3-2).

The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” for more information.

The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz by setting the IRCF<2:0> bits of the OSCCON register ≠ 000. Then, set the System Clock Source (SCS) bit of the OSCCON register to ‘1’ or en able Two-Speed Start-up by se tting the IESO bit in the Configuration Word register (CONFIG) to ‘1’.

The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not.

PIC16F688

3.5.2.1 OSCTUNE Register

The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register3-2).

The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number.

When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not af fected by the change in frequency.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits

01111 = Maximum frequen cy 01110 =

•

00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 =

•

• 10000 = Minimum frequency

PIC16F688

3.5.3 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure3-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTO SC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Mo nitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz (IRCF<2:0> bits of the OSCCON register= 000) as the system clock source (SCS bit of the OSCCON register = 1), or when any of the fo llow ing are ena bled:

• Two-Spe ed Star t-up IESO bi t of the C o nfi gura tio n Word register = 1 and IRCF<2:0> bits of the OSCCON register = 000

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The LF Internal Oscillator (LTS) bit of the OSCCON register indicates whether the LFINTOSC is stable or not.

3.5.4 FREQUENCY SELECT BITS (IRCF)

The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency Select b its IRCF<2:0> of the OSCCON register select the frequency output of the internal oscillators. One of eight frequencies can be selected via software:

•8 MHz

• 4 MHz (Default after Reset)

•2 MHz

•1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

• 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF <2:0 > bit s of

the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.

3.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING

When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6). If this is the case, there is a delay after the IRCF<2:0> bits of the OSCCON register are modified before the frequency selection takes place. The LTS and HTS bits of the OSCCON register will reflect the current active status of the LFINTOSC and HFINTOSC oscillators. The timing of a frequency selection is as follows:

1. IRCF<2:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. CLKOUT is held low and the clock switch

circuitry waits fo r a ris ing edge in the new clock.

5. CLKOUT is now connected with the new clock.

LTS and HTS bits of the OS CCON regi ster are updated as required.

6. Clock switch is complete.

See Figure 3-1 for more details. If the internal oscillator speed selected is between

8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and new frequencies are derived from the HFINTOSC via the postscaler and multi ple xe r.

Start-up delay specifications are located in the Section 14.0 “Electrical Specifications”, under the AC Specifications (Oscillator Module).

PIC16F688

FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING

(1)

HF HFINTOSC LFINTOSC (FSCM and WDT disabled)

HFINTOSC

Start-up Time

LFINTOSC

2-cycle Sync Running

IRCF <2:0>

System Clock

Note 1: When going from LF to HF.

HFINTOSC LFINTOSC (Either FSCM or WDT enabled)

HFINTOSC

LFINTOSC

IRCF <2:0>

System Clock

LFINTOSC HFINTOSC

LFINTOSC

HFINTOSC

≠ 0 = 0

2-cycle Sync Running

≠ 0 = 0

LFINTOSC turns off unless WDT or FSCM is enabled

Start-up Time 2-cycle Sync

Running

IRCF <2:0>

System Clock

= 0 ≠ 0

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MICROCHIP PIC16F688 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual