MICROCHIP PIC16F5X Technical data

PIC16F5X

Data Sheet

Flash-Based, 8-Bit CMOS

Microcontroller Series

 2004 Microchip Technology Inc. DS41213C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Mic rochip’s products as critical components in life support systems is not authorized except with e xpress written a pproval by M icrochip. No licenses are con veyed, implicitly or otherwise, u nder any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and T ot al Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

DS41213C-page ii  2004 Microchip Technology Inc.

PIC16F5X

Flash-Based, 8-Bit CMOS Microcontroller Series

High-Performance RISC CPU

• Only 33 single-word instructions to learn

• All instructions are singl e cycle ex cep t for

program branches which ar e two -cy c le

• Two-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

for data and instructions

• Operating speed:

- DC – 20 MHz clock speed

- DC – 200 ns instruction cycle time

• On-chip Flash program memory:

- 512 x 12 on PIC16F54

- 2048 x 12 on PIC16F57

- 2048 x 12 on PIC16F59

• General Purpose Registers (SRAM):

- 25 x 8 on PIC16F54

- 72 x 8 on PIC16F57

- 134 x 8 on PIC16F59

Special Microcontroller Features

• Power-on Reset (POR)

• Device Reset Tim er (DRT)

• Watchdog Timer (WDT) with its own on-chip

RC oscillator for reliable operation

• Programmable Code Protection

• Power-saving Sleep mo de

• In-Circuit Serial Programming™ (ICSP™)

• Selectable oscillator options:

- RC: Low-cost RC oscillator

- XT: Stand ard cry stal/resonator

- HS: High-speed crystal/resonator

- LP: Power-saving , low-frequency crystal

• Packages:

- 18-pin PDIP and SOIC for PIC16F54

- 20-pin SSOP for PIC16F54

- 28-pin PDIP, SOIC and SSOP for PIC16F57

- 40-pin PDIP for PIC16F59

- 44-pin TQFP for PIC16F59

Low-Power Features

• Operating Current:

-170µA @ 2V, 4 MHz, typical

-15µA @ 2V, 32 kHz, typical

• Standby Current:

- 500 nA @ 2V, typical

Peripheral Features

• 12/20/32 I/O pins:

- Individual direction control

- High current source/sink

• 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

CMOS Technology

• Wide operating voltage range:

- Industrial: 2.0V to 5.5V

- Extended: 2.0V to 5.5V

• Wide temperature range:

- Industrial: -40°C to 85°C

- Extended: -40°C to 125°C

• High-endurance Flash:

- 100K write/erase cycles

- > 40-year retention

Device

PIC16F54 512 25 12 1 PIC16F57 2048 72 20 1 PIC16F59 2048 134 32 1

 2004 Microchip Technology Inc. DS41213C-page 1

Program Memory Data Memory

I/O

Flash (words) SRAM (bytes)

Timers

8-bit

PIC16F5X

Pin Diagrams

PDIP, SOIC

T0CKI

MCLR

SSOP

T0CKI

MCLR

RA2 RA3

/VPP

VSS RB0 RB1 RB2 RB3

RA2 RA3

/VPP

VSS

VSS RB0 RB1 RB2 RB3

PDIP, SOIC

PIC16F54

18 17 16 15 14

13 12

11 10

•1 2 3 4 5 6 7 8 9

RA1 RA0 OSC1/CLKIN OSC2/CLKOUT V

RB7/ICSPDAT RB6/ICSPCLK RB5 RB4

T0CKI

N/C

N/C RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4

•1

2 3 4 5 6 7 8 9 10 11 12 13 14

PIC16F57

28 27 26 25 24 23 22 21 20 19 18 17 16 15

MCLR

/VPP OSC1/CLKIN OSC2/CLKOUT

RC7 RC6

RC5 RC4 RC3

RC2 RC1 RC0 RB7/ICSPDAT

RB6/ICSPCLK RB5

SSOP

VSS

T0CKI

VDD RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 VSS

PIC16F54

20 19 18 17 16 15 14 13 12 11

•1 2 3 4 5 6 7 8 9 10

RA1 RA0 OSC1/CLKIN OSC2/CLKOUT V

VDD RB7/ICSPDAT RB6/ICSPCLK RB5 RB4

•1 2 3 4 5 6 7 8 9 10 11 12 13 14

PIC16F57

28 27 26 25 24 23 22 21 20 19 18 17 16 15

MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7/ICSPDAT RB6/ICSPCLK RB5

PDIP, 0.600"

RA0 RA1 RA2 RA3

GND

RB0 RB1 RB2 RB3 RB4

RB5 RB6/ICSPCLK RB7/ICSPDAT

/VPP

MCLR

VDD RC0 RC1 RC2 RC3 RC4

TQFP

•1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

PIC16F59

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

T0CKI RE7

RE6 RE5 RE4

OSC1/CLKIN OSC2/CLKOUT RD7 RD6 RD5 RD4

RD3 RD2 RD1 GND RD0 RC7 RC6 RC5

GND GND

RB0 RB1 RB2 RB3 RB4

MCLR

RB5

/VPP

RB6/ICSPCLK RB7/ICSPDAT

RA3

4443424140

1 2 3 4 5 6 7 8 9 10 11

121314

RA2

RA1

RA0

PIC16F59

RC1

RC0

T0CKI

RC2

RE7

RC3

RE6

RE5

RE4

VDDVDD

363435

1819202122

RC7

RC6

RC5

RC4

33 32 31 30 29 28 27 26 25 24 23

RD0

OSC1/CLKIN OSC2/CLKOUT RD7 RD6 RD5 RD4 RD3 RD2 RD1 GND GND

DS41213C-page 2  2004 Microchip Technology Inc.

PIC16F5X

Table of Contents

1.0 General Description............................................................................ ....... .... .. .... .. .... ...................................................................5

2.0 Architectural Overview................................................................................................................................................................. 7

3.0 Memory Organization................................................................................................................................................................. 13

4.0 Oscillator Configurations............................................................................................................................................................21

5.0 Reset.......................................................................................................................................................................................... 23

6.0 I/O Ports............................................. ............................................................. ........................................................................... 29

7.0 Timer0 Module and TMR0 Register........................................................................................................................................... 33

8.0 Special Feature s of th e CPU.......... ............................... ................................ ............................................................................. 37

9.0 Instruction Set Summary ............................................................................................................................................................ 41

10.0 Development Support.................................................................................................................................................................53

11.0 Electrical Specificat io n s for PIC16F54/57...................................... ................................ ............................................................59

12.0 Electrical Specificat io n s for PIC16F59...................................................... ................ ................................................................. 60

13.0 Packaging Information. ............................... ............................................... ................................................................................. 71

On-Line Support................................................................................................................................................................................... 85

Systems Information and Upgrade Hot Line........................................................................................................................................ 85

Reader Response................................................................................................................................................................................86

Product Identification System .............................................................................................................................................................. 87

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

 2004 Microchip Technology Inc. DS41213C- page 3

PIC16F5X

NOTES:

DS41213C-page 4  2004 Microchip Technology Inc.

PIC16F5X

1.0 GENERAL DESCRIPTION

The PIC16F5X from Microchip Technology is a family of low-cost, high-performance, 8-bit, fully static, Flashbased CMOS microcontrollers. It employs a RISC architecture with only 33 single-word/single-cycle instruction s. All inst ruc tions are si ngle cy cle ex cept for program branches which take two cycles. The PIC16F5X delivers p erformanc e an orde r of ma gnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in i ts class . The easy-to-us e and easyto-remember instr ucti on se t reduc es de velop ment time significantly.

The PIC16F5X products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. Powersaving Sleep mode, Watchdog T i me r and co de p r ote ction features impro ve system cost, p ower and reliab ility .

The PIC16F5X products are supported by a full-featured macro assembler, a software simulator, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM machines.



PC and compatible

1.1 Applications

The PIC16F5X series fit s perfectly in a pplications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. The Flash technology makes customizing application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, lowpower , high pe rformance, ea se of use and I/O fl exibilit y make the PIC16F5X series very versatile, even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of “glue” logic in larger systems, co-processor applications).

TABLE 1-1: PIC16F5X FAMILY OF DEVICES

Features PIC16F54 PIC16F57 PIC16F59

Maximum Operation Frequency 20 MHz 20 MHz 20 MHz Flash Program Memory (x12 words) 512 2K 2K RAM Data Memory (bytes) 25 72 134 Timer Module(s) TMR0 TMR0 TMR0 I/O Pins 12 20 32 Number of Instructions 33 33 33 Packages 18-pin DIP, SOIC;

20-pin SSOP

Note: All PICmicro

and high I/O current capability.

Family devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect

28-pin DIP, SOIC;

28-pin SSOP

40-pin DIP, 44-pin TQFP

 2004 Microchip Technology Inc. DS41213C-page 5

PIC16F5X

NOTES:

DS41213C-page 6  2004 Microchip Technology Inc.

PIC16F5X

2.0 ARCHITECTURAL OVERVIEW

The high per formance of the P IC16F5X f amily c an be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F5X uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the sam e bus. Sep arating pro gram and da ta memory further allows instructions to be sized differently than the 8-bit wide data w ord. Instruction o pcodes are 12-bits wide, making it possible to have all singleword instructions. A 12-bit wide program memory access bus fetches a 12-b it instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Con sequently , all instructions (3 3) execute in a single cycle except for program branches.

The PIC16F54 addresses 512x 12 of program memory, the PIC16F57 and PIC16F59 addresses 2048 x 12 of program memory. All program memory is internal.

The PIC16F5X can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the program counter, are mapped in the data memory. The PIC16F5X has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any op eration on a ny register using any Addressing mode. This symmetrical nature and lack o f ‘special opti mal situations ’ make programming with the PIC16F5X simple, yet efficient. In addition, the learning curve is reduced significantly.

The PIC16F5X device c ont ains an 8- bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In sing le ope ran d inst ruction s, the operan d is either the W register or a file register.

The W register is an 8-bit workin g register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the Status Register. The C and DC bits operate as a borrow respectively, in subtraction. See the SUBWF and ADDWF instructions for examples.

A simplified block diagram is shown in Figure 2-1 with the corresponding device pins described in Table 2-1 (for PIC16F54), Table 2-2 (for PIC16F57) and Table 2-3 (for PIC16F59).

and digit borrow out bit,

 2004 Microchip Technology Inc. DS41213C-page 7

PIC16F5X

FIGURE 2-1: PIC16F5X SERIE S BLO CK DI AGRAM

Flash

512 X 12 (F54)

2048 X 12(F57)

2048 x 12(F59)

Instruction

Decoder

Literals

9-11

Direct Address

Status

ALU

9-11

Stack 1 Stack 2

Time-out

From W

WDT

Direct RAM

Address

TMR0

T0CKI

Watchdog

WDT/TMR0

Prescaler

Data Bus

Configuration Word

“Disable”

Timer

Option Reg.

From W

“Code-

Protect”

CLKOUT

“Option”

SFR

OSC1 OSC2 MCLR

“Osc

Select”

5-7

From W

Oscillator/

Timing &

Control

“Sleep”

General Purpose Register

File

(SRAM)

25, 72 or 134

Bytes

TRISA PORTA

“TRIS 5”

RA<3:0> RB<7:0>

From W

TRISE

“TRIS 9”

PORTE

RE<7:4>

PIC16F59

only

TRISB

“TRIS 6”

From W

TRISD

“TRIS 8”

RD<7:0>

PIC16F59

only

PORTD

PORTB

TRISC

“TRIS 7”

PORTC

RC<7:0>

PIC16F57/59

only

DS41213C-page 8  2004 Microchip Technology Inc.

PIC16F5X

TABLE 2-1: PIC16F54 PINOUT DESCRIPTION

Name Function

RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirectional I/O pin RB6/ICSPCLK RB6 TTL CMOS Bidirectional I/O pin

ICSPCLK ST — Serial Programming Clock

RB7/ICSPDAT RB7 TTL CMOS Bidirectional I/O pin

ICSPDAT ST CMOS Serial Programming I/O

T0CKI T0CKI ST — Clock input to Timer0. Must be tied to V

MCLR/VPP MCLR ST — Active-low Reset to device. Voltage on the MCLR/VPP pin must

VPP HV —

OSC1/CLKIN OSC1 XTAL — Oscillator crystal input

CLKIN ST — External clock source input

OSC2/CLKOUT OSC2 — XTAL Oscillator crystal output. Connects to crystal or resonator in

CLKOUT — CMOS In RC mode, OSC2 pin can output CLKOUT, which has 1/4 the

DD VDD Power — Positive supply for logic and I/O pins

VSS VSS Power — Ground reference for logic and I/O pins Legend: I = input I/O = input/output CMOS = CMOS output

O = output — = Not Used XTAL = Crystal input/output ST = Schmitt Trigger input TTL = TTL input HV = High Voltage

Input Type

Output

Type

Description

reduce curr ent consumption.

not exceed V mode.

Programming voltage input

Crystal Oscillator mode.

frequency of OSC1.

DD to avoid unintended entering of Programming

SS or VDD, if not in use, to

 2004 Microchip Technology Inc. DS41213C-page 9

PIC16F5X

TABLE 2-2: PIC16F57 PINOUT DESCRIPTION

Name Function

ICSPCLK ST — Serial programming clock

RB7/ICSPDAT RB7 TTL CMOS Bidirectional I/O pin

MCLR/VPP MCLR ST — Active-low Reset to device. Voltage on the MCLR/VPP pin must

VPP HV —

OSC1/CLKIN OSC1 XTAL — Oscillator crystal input

CLKIN ST — External clock source in put

OSC2/CLKOUT OSC2 — XTAL Oscillator crystal output. Connects to crystal or resonator in

CLKOUT — CMOS In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the

DD VDD Power — Positive supply for logic and I/O pins

SS VSS Power — Ground reference for logic and I/O pins

V N/C N/C — — Unused, do no t connect Legend: I = input I/O = input/output CMOS = CMOS output

O = output — = Not Used XTAL = Crystal input/output ST = Schmitt Trigger input TTL = TTL input HV = High Voltage

Input

Type

Output

Type

Description

reduce curr ent consumption.

not exceed V mode.

Programming voltage input

Crystal Oscillator mode.

frequency of OSC1.

DD to avoid unintended entering of Programming

SS or VDD, if not in use, to

DS41213C-page 10  2004 Microchip Technology Inc.

PIC16F5X

TABLE 2-3: PIC16F59 PINOUT DESCRIPTION

Name Function

ICSPCLK ST — Serial programming clock

RB7/ICSPDAT RB7 TTL CMOS Bidirectional I/O pin

ICSPDAT ST C MOS Serial programming I/O RC0 RC0 TTL CMOS Bidirectional I/O pin RC1 RC1 TTL CMOS Bidirectional I/O pin RC2 RC2 TTL CMOS Bidirectional I/O pin RC3 RC3 TTL CMOS Bidirectional I/O pin RC4 RC4 TTL CMOS Bidirectional I/O pin RC5 RC5 TTL CMOS Bidirectional I/O pin RC6 RC6 TTL CMOS Bidirectional I/O pin RC7 RC7 TTL CMOS Bidirectional I/O pin RD0 RD0 TTL CMOS Bidirectional I/O pin RD1 RD1 TTL CMOS Bidirectional I/O pin RD2 RD2 TTL CMOS Bidirectional I/O pin RD3 RD3 TTL CMOS Bidirectional I/O pin RD4 RD4 TTL CMOS Bidirectional I/O pin RD5 RD5 TTL CMOS Bidirectional I/O pin RD6 RD6 TTL CMOS Bidirectional I/O pin RD7 RD7 TTL CMOS Bidirectional I/O pin RE4 RE4 TTL CMOS Bidirectional I/O pin RE5 RE5 TTL CMOS Bidirectional I/O pin RE6 RE6 TTL CMOS Bidirectional I/O pin RE7 RE7 TTL CMOS Bidirectional I/O pin T0CKI T0CKI ST — Clock input to Timer0. Must be tied to V

MCLR

/VPP MCLR ST — Active-low Reset to device. Voltage on the MCLR/VPP pin must not

PP HV —

OSC1/CLKIN OSC1 XTAL — Oscillator crystal input

CLKIN ST — External clock source input

OSC2/CLKOUT OSC2 — XTAL Oscillator crystal output. Connects to crystal or resonator in Crystal

CLKOUT — CMOS In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of

DD VDD Power — Positive supply for logic and I/O pins

SS VSS Power — Ground reference for logic and I/O pins

V Legend: I = input I/O = input/output CMOS = CMOS output

O = output — = Not Used XTAL = Crystal input/output ST = Schmitt Trigger input TTL = TTL input HV = High Voltage

Input

Type

Output

Type

Description

SS or VDD, if not in use, to reduce

current consumption.

exceed VDD to avoid unintended entering of Programming mode. Programming voltage input

Oscillator mode.

OSC1.

 2004 Microchip Technology Inc. DS41213C-page 11

PIC16F5X

2.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1 and the instruction is fetched from program memory and latched into the instru cti on register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 2-2 and Example 2-1.

FIGURE 2-2 : CLOCK/INS T RU CTI O N CYC L E

Q2 Q3 Q4

OSC1

Q1 Q2 Q3 Q4

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC - 1) Fetch INST (PC + 1)

2.2 Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the Program Counter to change (e.g., GOTO), then two cycles are req uired to c omplete the ins truction (Example 2-1).

A fetch cycle begins with the Program Counter (PC) incrementing in Q1.

In the execution cy cle, the fetched instruction i s latched into the instruction register in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

Execute INST (PC) Fetch INST (PC + 2)

Q2 Q3 Q4

Execute INST (PC + 1)

Internal phase clock

EXAMPLE 2-1: INSTRUCTION PIPELINE FLOW

1. MOVLW H'55'

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTA, BIT3

All instructions are sing le cycle, except fo r any program branc hes. These take two cycles since the fetch instructio n is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

DS41213C-page 12  2004 Microchip Technology Inc.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC16F5X

3.0 MEMORY ORGANIZATION

PIC16F5X memory is organized into program memory and data memory. For the PIC16F57 and PIC16F59, which have more than 512 words of program memory, a paging scheme is used. Program memory pages are accessed using one or two Status register bits. For the PIC16F57 and PIC16F59, which have a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Selection Register (FSR).

3.1 Program Memory Organization

The PIC16F54 has a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space (Figure 3-1). The PIC16F57 and PIC16F59 have an 11-bit Program Counter capable of addressing a 2K x 12 program memory sp a ce (Fi gure3-2). Accessing a location above the ph ysicall y implem ented addres s will cause a wraparound.

A NOP at the Reset vector location will cause a restart at location 000h. The R eset v ec tor fo r the P IC16F 54 i s at 1FFh. The Reset vector for the PIC16F57 and PIC16F59 is at 7FFh. See Section 3.5 “Program

Counter” for additional information using CALL and GOTO instructions.

FIGURE 3-2: PIC16F57/PIC16F59

PROGRAM MEMORY MAP AND STACK

PC<10:0>

CALL, RETLW

Space

User Memory

Stack Level 1 Stack Level 2

On-chip Program

Memory (Page 0)

On-chip Program

Memory (Page 1)

On-chip Program

Memory (Page 2)

On-chip Program

Memory (Page 3)

Reset Vector

000h 0FFh

100h 1FFh

200h 2FFh

300h 3FFh

400h 4FFh

500h 5FFh

600h 6FFh

700h 7FFh

FIGURE 3-1: PIC16F54 PROGRAM

MEMORY MAP AND STAC K

PC<8:0>

CALL, RETLW

Space

User Memory

Stack Level 1 Stack Level 2

On-chip Program Memory

Reset Vector

000h

0FFh 100h

1FFh

 2004 Microchip Technology Inc. DS41213C-page 13

PIC16F5X

3.2 Data Memory Organization

Data memory is composed of registers or bytes of RAM. Therefore, d ata memory for a dev ic e i s sp ec ifie d by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR).

The Special Function Registers include the TMR0 register , the Program Counter (PC), the S t atus register , the I/O registers (ports) and the File Select Register (FSR). In addition, Special Purpose Registers are used to control the I/O port configuration and prescaler options.

The General Purpose Registers are used for data and control information under com mand of the instructions .

For the PIC16F54, the register file is composed of 7 Special Function Registers and 25 General Purpose Registers (Figure 3-3).

For the PIC16F57, the register file is composed of 8 Special Function Registers, 8 General Purpose Registers and 64 additional General Purpose Registers that may be addressed using a banking scheme (Figure 3-4).

For the PIC16F59, the register file is composed of 10 Special Function Registers, 6 General Purpose Registers and 128 additional General Purpose Registers that may be addressed using a banking scheme (Figure 3-5).

3.2.1 GENERAL PURPOSE REGISTER FILE

The register file is accessed either directly or indirectly through the File Select Register (FSR). The FSR register is described in Section3.7 “Indirect Data

Addressing; INDF and FSR Registers”.

FIGURE 3-3: PIC16F54 REGISTER FILE

MAP

File Address

(1)

INDF

TMR0

PCL

STATUS

FSR

PORTA

PORTB

General

Purpose

Registers

00h 01h 02h 03h 04h 05h 06h

07h

1Fh

Note 1: Not a physical register. See Section 3.7

“Indirect Data Addressing; INDF and FSR Registers”

FIGURE 3-4: PIC16F57 REGISTER FILE MAP

FSR<6:5> 00 01 10 11

File Address

00h 01h 02h 03h 04h 05h 06h 07h

08h

0Fh 10h

1Fh

Note 1: Not a physical register. See Section 3.7 “Indirect Data Addressing; INDF and FSR Registers”.

(1)

INDF

TMR0

PCL

STATUS

FSR PORTA PORTB

PORTC

General Purpose Registers

Bank 0 Bank 1 Bank 2 Bank 3

20h

2Fh 30h

3Fh

General Purpose Registers

40h

Addresses map back to addresses in Bank 0.

4Fh

50h

General Purpose Registers

5Fh

60h

6Fh 70h

General Purpose Registers

7Fh

DS41213C-page 14  2004 Microchip Technology Inc.

FIGURE 3-5: PIC16F59 REGISTER FILE MAP

PIC16F5X

FSR<7:5>

File Address

00h 01h

02h 03h 04h 05h 06h 07h 08h

09h

0Ah

0Fh 10h

1Fh

000 001 010 011

(1)

INDF

TMR0

PCL

STATUS

FSR PORTA PORTB

PORTC PORTD

PORTE

General Purpose Registers

Bank 0 Bank 1 Bank 2 Bank 3

20h

2Fh

30h

General Purpose Registers

3Fh

40h

4Fh

50h

General Purpose Registers

5Fh

60h

6Fh

70h

General Purpose Registers

7Fh

100 101 110 111

80h

Addresses map back to addresses in Bank 0.

8Fh

90h

General Purpose Registers

9Fh

Bank 4 Bank 5 Bank 6 Bank 7

A0h

AFh

B0h

General Purpose Registers

BFh

C0h

CFh

D0h

General Purpose Registers

DFh

E0h

EFh

F0h

General Purpose Registers

FFh

Note 1: Not a physical register.

 2004 Microchip Technology Inc. DS41213C-page 15

PIC16F5X

3.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFR) are registers used by the CPU and per ipheral functio ns to con trol the operation of the devic e (Table 3-1).

The Special Function Registers can be classified into two sets. The Special Function Re gisters associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

TABLE 3-1: SPECIAL FUNCTION REGISTER SUMMARY

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Power-on

Reset

N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC, TRISD, TRISE) 1111 1111 29 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT

--11 1111 18

prescaler

00h INDF Uses contents of FSR to address data memory (not a physical

xxxx xxxx 20

(1)

03h STATUS 04h FSR 04h FSR 04h FSR

(3) (4) (5)

05h PORTA

Low order 8 bits of PC 1111 1111 19

PA2 PA1 PA0 TO PD ZDCC0001 1xxx 17 Indirect data memory address pointer 111x xxxx 20 Indirect data memory address pointer 1xxx xxxx 20 Indirect data memory address pointer xxxx xxxx 20

(6)

— — — — RA3 RA2 RA1 RA0 ---- xxxx 29 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 29 07h PORTC 08h PORTD 09h PORTE

(2) (7) (6), (7)

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 29 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 29 RE7 RE6 RE5 RE4 — — — — xxxx ---- 29

Legend: Shaded cells = unimplemented or unused, – = unimplemented, read as ‘0’ (if applicable), x = unknown,

u = unchanged

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 3.5 “Program Counter”

for an explanation of how to access these bits.

2: File address 07h is a General Purpose Register on the PIC16F54. 3: PIC16F54 only. 4: PIC16F57 only. 5: PIC16F59 only. 6: Unimplemented bits are read as ‘0’s. 7: File address 08h and 09h are General Purpose Registers on the PIC16F54 and PIC16F57.

Details

on Page

DS41213C-page 16  2004 Microchip Technology Inc.

PIC16F5X

3.3 Status Register

This register contains the arithmetic status of the ALU, the Reset status and the page preselect bits for program memories larger than 512 words.

The Status register can be the destination for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO

and PD bits are not

For example, CLRF STATUS will clear the upper three bits and set the Z bit. Thi s leav es the Status register as 000u u1uu (where u = unchanged).

Therefore, it is recommended that only BCF, BSF, MOVWF and SWAPF instructions be used to alter the Stat us register be cause the se instruct ions do not af fect the Z, DC or C bits from the Status register. For other instructions which do affect Status bits, see Section 9.0 “Instruction Set Summary”.

writable. Therefore, the result of an instruction with the Status register as destination may be different than intended.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

PA2 PA1 PA0 TO PD ZDCC

bit 7 bit 0

bit 7 PA2: Reserved, do not use

Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products.

bit 6-5 PA<1:0>: Program Page Preselect bits (PIC16F57/PIC16F59)

00 = Page 0 (000h-1FFh) 01 = Page 1 (200h-3FFh) 10 = Page 2 (400h-5FFh) 11 = Page 3 (600h-7FFh)

Each page is 512 words. Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended. This may affect upward compatibility with future products.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Bo

bit 0 C: Carry/Bo

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

rrow bit (for ADDWF and SUBWF instructions)

ADDWF

1 = A carry to the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of th e result did not occur

SUBWF

1 = A borrow to the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred

rrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF

1 = A carry occurred 1 = A borrow did not occur Loaded with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred

SUBWF RRF or RLF

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. DS41213C-page 17

PIC16F5X

3.4 Option Register

The Option register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0.

By executin g the OPTION instruction, the contents of the W register will be transfe rred to the Option registe r. A Reset sets the Option<5:0> bits.

U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1

— — T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

bit 2-0 PS<2:0>: Prescaler rate select bits

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41213C-page 18  2004 Microchip Technology Inc.

PIC16F5X

3.5 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one, every instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO inst ruction word . The PC Latch (P CL) is mapped to PC<7:0> (Figure 3-6 and Figure 3-7).

For the PIC16F57 and PIC16F59, a page number must be supplied as well. Bit 5 and bit 6 of the S t atus register provide page information to bit 9 and bit 10 of the PC (Figure 3-6 and Figure 3-7).

For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruct ion word, but is alway s cleared (Figure 3-6 and Figure 3-7).

Instructions where t he PCL is the des tinati on or modif y PCL instructions, include MOVWF PCL, ADDWF PCL, and BSF PCL,5.

For the PIC16F57 and PIC16F59, a page number again must be supplied. Bit 5 and bit 6 of the Status register provide page information to bit 9 and bit 10 of the PC (Figure 3-6 and Figure 3-7).

FIGURE 3-7: LOADING OF PC BR ANCH

INSTRUCTIONS – PIC16F57 AND PIC16F59

GOTO Instruction

910

87 0

PA<1:0>

Status

CALL or Modify PCL Instruction

87 0

910

Reset to ‘0’

PA<1:0>

Status

PCL

Instruction Word

PCL

Instruction Word

Note: Because PC<8> is cleared in the CALL

instruction or any modified PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long).

FIGURE 3-6: LOADING OF PC BRANCH

INSTRUCTIONS – PIC16F54

GOTO Instruction

87 0

CALL or Modify PCL Instruction

87 0

Reset to '0'

PCL

Instruction Word

PCL

Instruction Word

3.5.1 PAGING CONSIDERATIONS PIC16F57 AND PIC16F59

If the PC is pointing to the last address of a selected memory page, when i t incremen ts, it w ill cause t he program to continue in the next h igher p age . Howe ver, the page preselect bits in the Status register will not be updated. Therefore, the next GOTO, CALL or MODIFY PCL instruction will send the program to the page specified by the page preselect bits (PA0 or PA<1:0>).

For example, a NOP at location 1FFh (page 0) increments the PC to 200h (page 1). A GOTO xxx at 200h will return the program to address xxh on page 0 (assuming that PA<1:0> are clear).

To prevent this, the page preselect bits must be updated under program control .

3.5.2 EFFECTS OF RESET

The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the Reset vector).

The Status register page preselect bits are cleared upon a Reset , whic h me ans that page 0 is prese lecte d.

Therefore, upon a Reset, a GOTO instruction at the Reset vector location will automatically cause the program to jump to page 0.

 2004 Microchip Technology Inc. DS41213C-page 19

PIC16F5X

3.6 Stack

The PIC16F54 device has a 9- bi t wide, tw o-l ev el ha rdware PUSH/POP stack. The PIC16F57 and PIC16F59 devices have an 11-bit wide, two-level hardware PUSH/POP stack.

A CALL instruction will PUSH the current value of stack 1 into stack 2 and t hen PUSH the c urren t pr ogram c ounte r value, incre mented by one, into stack lev el 1. If more tha n two sequenti al CALL’ s are executed, only the most recent two return addresse s are stored .

A RETLW i nstruction will POP th e contents of s tack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled with the address previously stored in level 2.

Note: The W register will be loaded with the

literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.

For the RETLW instruction, the PC is loaded with the Top-of-Stack (TOS) contents. All of the devices covered in this data sheet have a two-level stack. The stack has the same bit width as the devic e PC, there fore, paging is not an issue when returning from a subroutine.

3.7 Indirect Data Addressing; INDF and FSR Registers

The INDF register is not a physi cal register. Addressing INDF actually address es the reg ister whos e addres s is contained in the FSR Register (FSR is a pointer). T h is is indirect addressing.

EXAMPLE 3-1: INDIRECT ADDRESSING

• Register file 08 contains the value 10h

• Register file 09 contains the value 0Ah

• Load the value 08 into the FSR regi ster

• A read of the INDF register will return the value of 10h

• Increment the value of the FSR register by one (FSR = 09h)

• A read of the INDF register now will return the value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although Status bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 3-2.

EXAMPLE 3-2: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

MOVLW H'10' ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF Register

INCF FSR,F ;inc pointer BTFSC FSR,4 ;all done? GOTO NEXT ;NO, clear next

CONTINUE

: ;YES, continue

The FSR is either a 5-bit (PIC 16F54 ), 7-bit (PIC1 6F57) or 8-bit (PIC16F59) wide register. It is used in conj unc tion with the INDF register t o indirectly addr ess the dat a memory area.

The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.

PIC16F54: This does not us e banking. FSR<7 :5> bits are unimplemented and read as ‘1’s.

PIC16F57: FSR<7> bit is unimp lemented and read a s ‘1’. FSR<6:5> are the bank select bits and are used to select the bank to be addressed (00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3).

PIC16F59: FSR<7:5> are the bank select bits and are used to select the bank to be addressed (000 = Bank 0, 001 = Bank 1, 010 = Bank 2,

011 = Bank 3, 100 = Bank 4, 101 = Bank 5, 110 = Bank 6, 111 = Bank 7).

Note: A CLRF FSR instruction may not result in

an FSR value of 00h if there are unimplemented bits present in the FSR.

DS41213C-page 20  2004 Microchip Technology Inc.

PIC16F5X

4.0 OSCILLATOR CONFIGURATIONS

4.1 Oscillator Types

The PIC16F5X devices can be operated in four different oscillator mode s. The user can progra m two configuration bits (FOS C1:FOSC0) to select one of these four modes:

• LP: Low-power Crystal

• XT: Crystal/Resonator

• HS: High-speed Crystal/Resonator

• RC: Resistor/Capacitor

4.2 Crystal Oscillator/Ceramic Resonators

In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 4-1). The PIC16F5X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency outside of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source drive the OSC1/CLKIN pin (Figure 4-2).

FIGURE 4-1 : CRYST AL/C E RAMI C

RESONATO R OPER ATI ON (HS, XT OR LP OSC CONFIGURATION)

(1)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required. 3: RF varies with the Oscillator mode chosen

(approx. value = 10 MΩ).

FIGURE 4-2: EXTERNAL CLOCK INPUT

Clock from ext. system

Open

XTAL

(2)

OSC1

OSC2

PIC16F5X

(3)

OPERATION (HS, XT OR LP OSC CONFIGURATION)

OSC1

PIC16F5X

OSC2

Sleep

To internal

logic

T ABLE 4-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Osc

Type

XT 455 kHz

HS 8.0 MHz

These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator man ufa ctu rer for appropriate values of external components.

Resonator

Freq.

2.0 MHz

4.0 MHz

16.0 MHz

Cap. RangeC1Cap. Range

68-100 pF

15-33 pF 10-22 pF

10-22 pF

10 pF

68-100 pF

15-33 pF 10-22 pF

10-22 pF

10 pF

T ABLE 4-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc

Type

LP 32 kHz XT 100 kHz

HS 4 MHz

Note 1: For V

These values are for design guidance only. Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specifications. Since each crystal has its own characteristics, the user sho uld c onsul t the cryst al manu fact urer for appropriate values of external components.

Note 1: This device has been des igned to perform

Crystal

Freq.

200 kHz 455 kHz

1MHz 2MHz 4MHz

8MHz

20 MHz

DD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

to the parame ter s of i ts da ta s he e t. I t ha s been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application tha n the earlier v ersion of this device.

2: The user should verify that the device

oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the Os cillator mode ma y be required.

(1)

Cap.Range

15 pF 15 pF

15-30 pF 15-30 pF 15-30 pF 15-30 pF

15 pF 15 pF

15 pF 15 pF 15 pF

Cap. Range

200-300 pF 100-200 pF

15-100 pF

15-30 pF

15 pF 15 pF

15 pF 15 pF 15 pF

 2004 Microchip Technology Inc. DS41213C-page 21

PIC16F5X

4.3 External Crystal Oscillator Circuit

Either a pre-packaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Pre-packaged oscillators provide a wide operating range and better stability. A well designed cryst al oscilla tor will provide g ood performance with TTL gates. Two types of crystal oscillator circuits can b e used: one with parallel resonance or one with series resonance.

Figure 4-3 shows an implementation example of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS 04 i nvert er perf orm s th e 180° phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10 kΩ potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.

FIGURE 4-3: EXTERNAL PARALLEL

RESONANT CRY ST A L OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE)

+5V

10k

4.7k

74AS04

10k

XTAL

10k

20 pF

Figure 4-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverters perform a 360° phase shift in a series resonant oscillator circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.

74AS04

Open

To Other Devices

PIC16F5X

CLKIN

OSC2

FIGURE 4-4: EXTERNAL SERIES

RESONANT CRY ST A L OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE)

74AS04

To Other Devices

Open

PIC16F5X

CLKIN

OSC2

330

74AS04

330

74AS04

0.1 µF XTAL

4.4 RC Oscillator

For applications where precise timing is not a requirement, the RC oscillator option is available. The operation and functionality of the RC oscillator is dependent upon a number of variables. The RC oscillator frequency is a function of:

• Supply voltage

• Resistor (R

• Operating temperature. The oscillator frequency will vary from unit to unit due

to normal process parameter variation. The difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to account for the tolerance of the external R and C components. Figure 4-5 shows how the R/C combination is connected.

The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin and can be used for test purposes or to synchronize other logic.

FIGURE 4-5: RC OSCILLA TOR M ODE

REXT

CEXT VSS

EXT) and capacitor (CEXT) values

VDD

OSC1

Internal clock

PIC16F5X

OSC/4

DS41213C-page 22  2004 Microchip Technology Inc.

OSC2/CLKOUT

PIC16F5X

5.0 RESET

The PIC16F5X devices may be reset in one of the following ways:

• Power-on Reset (POR)

•MCLR

•MCLR Wake-up Reset (from Sleep)

• WDT Reset (normal operation)

• WDT Wake-up Reset (from Sleep) Table 5-1 shows these Reset conditions for the PCL

and Status registers. Some registers are no t af fected in a ny Rese t conditio n.

Their status is unk nown on POR and uncha nged in any other Reset. Most other registers are reset to a “Reset state” on Power-on Reset (POR), MCLR Reset. A MCLR results in a device Reset and not a continuation of operation before Sleep.

Reset (normal operation)

or WDT

or WDT wake-up from Sleep also

The TO depending on the different Reset conditions (Table 5-1). These bits may be used to determine the nature of the Reset.

Table 5-3 lists a full description of Reset states of all registers. Figure 5-1 shows a simplified block diagram of the on-chip Reset circuit.

and PD bits (Status <4:3>) are set or cleared

TABLE 5-1: STATUS BITS AND THEIR SIGNIFICANCE

Condition TO PD

Power-on Reset 11

Reset (normal operation) uu

MCLR

Wake-up (from Sleep) 10

MCLR WDT Reset (normal operation) 01 WDT Wake-up (from Sleep) 00

Legend: u = unchanged, x = unknown, — = unimplemented read as ‘0’.

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH RESET

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

03h STA TUS Legend: u = unchanged, x = unknown, q = see Table 5-1 for possible values.

PA2 PA1 PA0 TO PD Z DC C 0001 1xxx 000q quuu

Value on

POR

Value on

MCLR

and

WDT Reset

 2004 Microchip Technology Inc. DS41213C-page 23

PIC16F5X

TABLE 5-3: RESET CONDITIONS FOR ALL REGISTERS

WN/Axxxx xxxx uuuu uuuu TRIS N/A 1111 1111 1111 1111 OPTION N/A --11 1111 --11 1111 INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000q quuu

(1)

FSR

(2)

FSR

(3)

FSR PORTA 05h ---- xxxx ---- uuuu PORTB 06h xxxx xxxx uuuu uuuu PORTC PORTD PORTE

(4) (5)

(5)

Legend: u = unchanged, x = unknown, — = unimplemented, read as ‘0’, q = see tables in Table 5-1 for possible

values.

Note 1: PIC16F54 only.

2: PIC16F57 only. 3: PIC16F59 only. 4: General purpose register file on PIC16F54. 5: General purpose register file on PIC16F54 and PIC16F57.

04h 111x xxxx 111u uuuu 04h 1xxx xxxx 1uuu uuuu 04h xxxx xxxx uuuu uuuu

07h xxxx xxxx uuuu uuuu 08h xxxx xxxx uuuu uuuu 09h xxxx ---- uuuu ----

FIGURE 5-1: SIMPLIFIE D BLOC K DIAG RAM O F ON-C HIP RE SE T CIRC UIT

VDD

POR

MCLR/VPP

MCLR

Filter

WDT

Module

DRT

Reset

Chip Reset

DS41213C-page 24  2004 Microchip Technology Inc.

PIC16F5X

5.1 Power-on Reset (POR)

The PIC16F5X family of devices incorporate on-chip Power-on Reset (POR) circuitry which provides an internal chip Reset for most power-up situations. To use this feature, the user merely ties the MCLR

DD. A simplified block diagram of the on-chip

to V Power-on Reset circuit is shown in Figure 5-1.

The Power-on Reset circuit and the Device Reset Timer (Section 5.2) circuit are closely related. On power-up, the Reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the Res et lat ch and thus end th e onchip Reset signal.

A power-up example where MCLR shown in Figure 5-3. V before bringing MCLR out of Reset T

DRT msec after MCLR goes high.

DD is allowed to rise and stabilize

high. The chip will actual ly come

is not tied to VDD is

In Figure 5-4, the on-chip Power-on Reset feature is being used (MCLR and VDD are ti ed together). The VDD is stable bef ore the st art-up tim er times out and the re is no problem in getting a proper Reset. However, Figure 5-5 depic ts a pro blem situ ation whe re VDD rises too slowly. The time between when the DRT senses a high on the MCLR V

DD) actually reach their full va lue is too long. In this sit-

/VPP pin and the MCL R/VPP pin (and

uation, when the start-up timer times out, V reached the V

DD (min) value and the chip is, therefo r e,

not ensured to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 5-2).

Note 1: When the device starts normal operation

(exits the Reset condition), device operating parameters (voltage, frequency , tempe rature, etc.) m ust be met to ensure operation. If these conditions are not met, the device must be hel d in Reset until the operating conditions are met.

2: The POR is disabled when the device is

in Sleep.

For more information on the PIC16F5X POR, see Application Note AN522, “Power-Up Considerations” at www.microchip.com.

/VPP pin

DD has not

FIGURE 5-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW V

VDDVDD

• External Power-on Reset circuit is required only if V helps dischar ge the capacito r quickly when VDD powers down.

•R < 40kΩ is recommended to make sure th at voltage drop across R does not violate the device electrical specification.

•R1 = 100Ω to 1 kΩ will limit any current flowing into MCLR from external capacitor C in the event of MCLR Electrostatic Discha rge (ESD) or Electric al Overstress (EOS).

DD power-up is too slow. The diode D

DD POWER-UP)

MCLR

PIC16F5X

pin breakdown due to

 2004 Microchip Technology Inc. DS41213C-page 25

+ 63 hidden pages

MICROCHIP PIC16F5X Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 GENERAL DESCRIPTION

TABLE 1-1: PIC16F5X FAMILY OF DEVICES

2.0 ARCHITECTURAL OVERVIEW

FIGURE 2-1: PIC16F5X SERIE S BLO CK DI AGRAM

TABLE 2-1: PIC16F54 PINOUT DESCRIPTION

TABLE 2-2: PIC16F57 PINOUT DESCRIPTION

TABLE 2-3: PIC16F59 PINOUT DESCRIPTION

FIGURE 2-2 : CLOCK/INS T RU CTI O N CYC L E

3.0 MEMORY ORGANIZATION

FIGURE 3-4: PIC16F57 REGISTER FILE MAP

FIGURE 3-5: PIC16F59 REGISTER FILE MAP

TABLE 3-1: SPECIAL FUNCTION REGISTER SUMMARY

4.0 OSCILLATOR CONFIGURATIONS

FIGURE 4-5: RC OSCILLA TOR M ODE

5.0 RESET

TABLE 5-1: STATUS BITS AND THEIR SIGNIFICANCE

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH RESET

TABLE 5-3: RESET CONDITIONS FOR ALL REGISTERS

FIGURE 5-1: SIMPLIFIE D BLOC K DIAG RAM O F ON-C HIP RE SE T CIRC UIT