Features
• High-performance, Low-power Atmel
• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 32Kbytes of In-System Self-programmable Flash program memory
– 1024Bytes EEPROM
– 2Kbyte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
• I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
• Operating Voltages
– 2.7V - 5.5V for ATmega32L
– 4.5V - 5.5V for ATmega32
• Speed Grades
– 0 - 8MHz for ATmega32L
– 0 - 16MHz for ATmega32
• Power Consumption at 1 MHz, 3V, 25⋅C
– Active: 1.1mA
– Idle Mode: 0.35mA
– Power-down Mode: < 1µA
®
AVR® 8-bit Microcontroller
(1)
8-bit
Microcontroller
with 32KBytes
In-System
Programmable
Flash
ATmega32
ATmega32L
Summary
2503QS–AVR–02/11
Pin
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
(OC2) PD7
VCC
GND
(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3
PB4 (SS)
PB3 (AIN1/OC0)
PB2 (AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PDIP
TQFP/MLF
Note:
Bottom pad should
be soldered to ground.
Configurations
Figure 1. Pinout ATmega32
ATmega32(L)
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2
ATmega32(L)
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC
SPI
ADC
INTERFACE
COMP.
INTERFACE
PORTA DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
+
-
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
RESET
CONTROL
LINES
VCC
GND
MUX &
ADC
AREF
PA0 - PA7 PC0 - PC7
PD0 - PD7PB0 - PB7
AVR CPU
TWI
AVCC
INTERNAL
CALIBRATED
OSCILLATOR
Overview The Atmel
®
AVR® ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
Block Diagram Figure 2. Block Diagram
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ATmega32(L)
The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The ATmega32 provides the following features: 32Kbytes of In-System Programmable Flash
Program memory with Read-While-Write capabilities, 1024bytes EEPROM, 2Kbyte SRAM, 32
general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundaryscan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented
Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with
programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops
the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters,
SPI port, and interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low-power consumption. In Extended Standby mode, both the main Oscillator
and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the Application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.
The Atmel AVR ATmega32 is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7
are used as inputs and are externally pulled low, they will source current if the internal pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
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ATmega32(L)
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega32 as listed on page
57.
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins
PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.
The TD0 pin is tri-stated unless TAP states that shift out data are entered.
Port C also serves the functions of the JTAG interface and other special features of the
ATmega32 as listed on page 60.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega32 as listed on page
62.
RESET
Reset Input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
37. Shorter pulses are not guaranteed to generate a reset.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.
AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally con-
nected to V
, even if the ADC is not used. If the ADC is used, it should be connected to V
CC
CC
through a low-pass filter.
AREF AREF is the analog reference pin for the A/D Converter.
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ATmega32(L)
Resources A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note: 1.
Data Retention Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C Compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documentation for more details.
2503QS–AVR–02/11
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ATmega32(L)
Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
$3F ($5F) SREG I T H S V N Z C 10
$3E ($5E) SPH – – – – SP11 SP10 SP9 SP8 12
$3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12
$3C ($5C) OCR0
$3B ($5B) GICR INT1 INT0 INT2 – – – IVSEL IVCE 47, 67
$3A ($5A) GIFR INTF1 INTF0 INTF2 – – – – –68
$39 ($59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 82, 112, 130
$38 ($58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 83, 112, 130
$37 ($57) SPMCR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 248
$36 ($56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 177
$35 ($55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 32, 66
$34 ($54) MCUCSR JTD ISC2 – JTRF WDRF BORF EXTRF PORF 40, 67, 228
$33 ($53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 80
$32 ($52) TCNT0 Timer/Counter0 (8 Bits) 82
(1)
$31
($51)
$30 ($50) SFIOR ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 56,85,131,198,218
$2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 107
$2E ($4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 110
$2D ($4D) TCNT1H Timer/Counter1 – Counter Register High Byte 111
$2C ($4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 111
$2B ($4B) OCR1AH
$2A ($4A) OCR1AL
$29 ($49) OCR1BH
$28 ($48) OCR1BL
$27 ($47) ICR1H Timer/Counter1 – Input Capture Register High Byte 111
$26 ($46) ICR1L Timer/Counter1 – Input Capture Register Low Byte 111
$25 ($45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 125
$24 ($44) TCNT2 Timer/Counter2 (8 Bits) 127
$23 ($43) OCR2
$22 ($42) ASSR – – – – AS2 TCN2UB OCR2UB TCR2UB 128
$21 ($41) WDTCR – – – WDTOE WDE WDP2 WDP1 WDP0 42
(2)
$20
($40)
$1F ($3F) EEARH – – – – – – EEAR9 EEAR8 19
$1E ($3E) EEARL EEPROM Address Register Low Byte 19
$1D ($3D) EEDR EEPROM Data Register 19
$1C ($3C) EECR – – – – EERIE EEMWE EEWE EERE 19
$1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 64
$1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 64
$19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 64
$18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 64
$17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 64
$16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 65
$15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 65
$14 ($34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 65
$13 ($33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 65
$12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 65
$11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 65
$10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 65
$0F ($2F) SPDR SPI Data Register 138
$0E ($2E) SPSR SPIF WCOL
$0D ($2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 136
$0C ($2C) UDR USART I/O Data Register 159
$0B ($2B) UCSRA RXC TXC UDRE FE DOR PE U2X MPCM 160
$0A ($2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 161
$09 ($29) UBRRL USART Baud Rate Register Low Byte 164
$08 ($28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 199
$07 ($27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 214
$06 ($26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 216
$05 ($25) ADCH ADC Data Register High Byte 217
$04 ($24) ADCL ADC Data Register Low Byte 217
$03 ($23) TWDR Two-wire Serial Interface Data Register 179
$02 ($22) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 179
OSCCAL Oscillator Calibration Register 30
(1)
OCDR On-Chip Debug Register 224
UBRRH URSEL – – – UBRR[11:8] 164
(2)
UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 162
Timer/Counter0 Output Compare Register
Timer/Counter1 – Output Compare Register A High Byte
Timer/Counter1 – Output Compare Register A Low Byte
Timer/Counter1 – Output Compare Register B High Byte
Timer/Counter1 – Output Compare Register B Low Byte
Timer/Counter2 Output Compare Register
– – – – – SPI2X 138
82
111
111
111
111
127
2503QS–AVR–02/11
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