MediaTek MT6227 Schematics
MT6227 GSM/GPRS Baseband
Processor Technical Brief
Revision 1.00
July 07, 2005
MT6227 GSM/GP RS Baseband Processor Technical Brief Revision 1.00
Revision History
Revision Date Comments
1.00 July 07, 2005 First Release
2/32 MediaTek Inc. Confidential
MT6227 GSM/GP RS Baseband Processor Technical Brief Revision 1.00
TABLE OF CONTENTS
Revision History ...................................................................................................................................... 2
1. System Overvie w............................................................................................................................... 4
1.1 Platform Feature ............................................................................................................................................................................7
1.2 MODEM Features.........................................................................................................................................................................9
1.3 Multi-Media Features.................................................................................................................................................................10
1.4 General Description ....................................................................................................................................................................12
2 Product Descriptio n ........................................................................................................................ 14
2.1 Pin Outs.........................................................................................................................................................................................14
2.2 Top Marking Definition.............................................................................................................................................................17
2.3 Pin Description............................................................................................................................................................................18
2.4 Power Description.......................................................................................................................................................................26
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MT6227 GSM/GP RS Baseband Processor Technical Bri ef Re vision 1.00
1. System Overview
The revolutionary MT6227 is a lead ing edge single-chip
solution for GSM/GPRS mobile phones targeting the
emerging applications in digital audio and video. Based on
32-bit ARM7EJ-STM RISC processor, MT6227 not only
features high performance GPRS Class 12 MODEM, but
also provides comprehensive and advanced solutions for
handheld multi-media.
Typical application is shown in Figure 1.
Multi-media Subsystem
The MT6227 mu lti-media subsystem provides connection
to CMOS/CCD image sensor and supports resolution up to
2M pixels. With its advanced image signal and data
processing technology, MT6227 allows efficient
processing of image and video data. It also has built-in
JPEG CODEC and MPEG-4/H.263 CODEC, thus enabling
real-time creation and playback of h igh-quality images and
video. In addition to advanced image and video features,
MT6227 also utilizes high resolution DAC, digital audio,
and audio synthesis technology to provide superior audio
features for all future multi-media needs.
In order to provide more flexibility and bandwidth for
multi-media products, an additional 18-bit parallel
interface is incorporated. This interface enables connection
to LCD modules as well as connection to NAND flash
devices to allow fo r multi-media data storage capabilities.
User Interface
To provide complete user interface, MT6227 brings
together all the necessary peripheral blocks for
multi-media GSM/GPRS phone. The peripheral blocks
consists of the Keypad Scanner with the capability to
detect multiple key presses, SIM Controller, Alerter, Real
Time Clock, PWM, Serial LCD Controller, and General
Purpose Programmable I/Os. For connectivity and data
storage, the MT6227 supports UART, IrDA, USB 1.1
Slave and MMC/SD/MS/MS Pro. Furthermore, for la rge
amount of data transfer, high performance DMA (Direct
Memory Access) and hardware flow control are
implemented, which greatly enhances the performance and
reduces MCU processing load.
Audio Interface
Using a highly integrated mixed-signal Audio Front-End,
the MT6227 architecture allo ws for easy audio interfacing
with direct connection to the audio transducers. The audio
interface integrates D/A and A/D Converters for Voice
band, as well as high resolution Stereo D/A Converters for
Audio band. In addition, MT6227 also provides Stereo
Input and Analog Mux.
MT6227 supports AMR codec to adaptively optimize
speech and audio quality. Moreover, aacPlus codec is
implemented to deliver CD-quality audio at low bit rates.
External Me mory Interface
Providing the greatest capacity for expansion, MT6227
supports up to 8 state-of-the-art devices through its 16-b it
host interface. Devices such as burst/page mode Flash,
page mode SRAM, Pseudo SRAM, Color/Parallel LCD,
and multi-media co mpanion chip are all supported through
this interface. To minimize power consumption and ensure
low noise, this interface is designed for flexible I/O voltage
and allows lowering of supply voltage down to 1.8V. The
driving strength is configurable for signal integrity
adjustment. The data bus also employs retention
technology to prevent the bus from floating during turn
over.
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Overall, MT6227’s audio features provide a rich platform
for mu lti-media applications.
Radio Interface
MT6227 integrates a mixed-signal Baseband front-end in
order to provide a well-organized radio interface with
flexibility for efficient customization. It contains gain and
offset calibration mechanisms, and filters with
programmable coefficients for comprehensive
compatibility control on RF modules. This approach also
allows the usage of a high resolution D/A Converter for
controlling VCXO or crystal, thus reducing the need for
expensive TCVCXO. MT6227 achieves great MODEM
performance by utilizing 14-bit high resolution A/D
MT6227 GSM/GP RS Baseband Processor Technical Brief Revision 1.00
Converter in the RF downlink path. Fu rthermore, to reduce
the need for extra exte rnal current-driv ing component, the
driving strength of some BPI outputs is designed to be
configurable.
Debug Function
The JTAG interface enables in-circuit debugging of
software program with the ARM 7EJ-S core. With this
standardized debugging interface, the MT6227 provides
developers with a wide set of options in choosing ARM
development kits from different third party vendors.
Power Management
The MT6227 offers various low-power features to help
reduce system power consumption. These features include
Pause Mode of 32KHz clocking at Standby State, Power
Down Mode for individual peripherals, and Processor
Sleep Mode. In addition, MT6227 is also fabricated in
advanced low leakage CMOS process, hence providing an
overall u ltra low leakage solution.
Package
The MT6227 device is offered in a 13mm×13mm, 296-ball,
0.65 mm pitch, TFBGA package.
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MT6227 GSM/GP RS Baseband Processor Technical Brief Revision 1.00
DEBUGGER
AUDIO
DAC
SRAM
PSRAM
JTAG
SPEECH/AUDIO
INPUT
SPEECH/AUDIO
OUTPUT
FM STEREO
RADIO INPUT
HIFI STEREO
OUTPUT
ALERTER
PWM
SIM
I2S
USIM
FLASH
SERIAL
LCD
IMAGE
SENSOR
IMAGE INPUT
MT6227
CHIP UID
MMC/SD/MS
USB
MSPRO
NAND
FLASH
LCD
18-BIT PARALLEL
INTERFACE
SYS CLK
TX I/Q
RX I/Q
B2PSI
AUXADC
SUPPLY
VOLTAGES
UART
IRDA
KEYPAD
AFC
APC
BPI
BSI
TCVCXO
RF
MODULE
POWER
MANAGEMENT
CIRCUITRY
Figure 1 Typical application of MT6227
SERIAL
LCD
1 2 3
4 5 6
7 8 9
0 #
*
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MT6227 GSM/GP RS Baseband Processor Technical Brief Revision 1.00
1.1 Platform Feature
General
Integrated voice-band, audio-band and base-band
analog front ends
TFBGA 13mm×13mm, 296-ball, 0.65 mm pitch
package
MCU Subsystem
ARM7EJ-S 32-bit RISC processor
High performance multi-layer AMBA bus
Java hardware acceleration for fast Java-based
games and applets
Operating frequency: 26/52 MHz
Dedicated DMA bus
14 DMA channels
284K Bytes zero-wait-state on-chip SRAM
On-chip boot ROM for Factory Flash
Programming
Flexible I/O voltage of 1.8V ~ 2.8V for memory
interface
Configurable driving strength for memo ry
interface
User In terfaces
6-row × 7-column keypad controller with
hardware scanner
Supports mu ltiple key presses for gaming
SIM/USIM Controller with hardware T=0/T=1
protocol control
3 UARTs with hardware flow control and speed up
to 921600 bps
IrDA modulator/demodulator with hardware
framer supports SIR mode of operation
Real Time Clock (RTC) operating with a separate
power supply
General Purpose I/Os (GPIOs)
Watchdog timer for system crash recovery
2 sets of General Purpose Timer
Circuit Switch Data coprocessor
Div ision coprocessor
External Me mory Inter face
Supports up to 8 external devices
Supports 8-bit or 16-bit me mory components with
maximum size of up to 64M Bytes each
Supports Flash and SRAM with Page Mode or
Burst Mode
Supports Pseudo SRAM
Industry standard Parallel LCD Interface
Supports multi-media companion chips with 8/16
bits data width
2 Sets of Pulse Width Modulation (PWM) Output
Alerter Output with Enhanced PWM or PDM
4~10 external interrupt lines
Connecti vity
Full-speed USB 1.1 Device controller
Multi Media Card/Secure Digital Memory
Card/Memory Stick/Me mory Stick Pro host
controller
Security
Supports security key for code protection
56-bit unique chip ID
Power Management
Power Down Mode for analog and digital circuits
Processor Sleep Mode
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MT6227 GSM/GP RS Baseband Processor Technical Brief Revision 1.00
Pause Mode of 32KHz clocking at Standby State
7-channel Auxiliary 10-bit A/D Converter for
charger and battery monitoring and photo sensing
Test and Debug
Built-in digital and analog loop back modes for
both Audio and Baseband Front-End
DAI port co mplying with GSM Rec.11.10
JTAG port for debugging embedded MCU
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MT6227 GSM/GP RS Baseband Processor Technical Brief Revision 1.00
1.2 MODEM Features
Radi o Interface and B ase band Fron t End
GMSK modulator with analog I and Q channel
outputs
10-bit D/A Converter for uplink baseband I and Q
signals
14-bit high resolution A/D Converter for downlink
baseband I and Q signals
Calibration mechanism of offset and gain
mismatch for baseband A/D Converter and D/A
Converter
10-bit D/A Converter for Automatic Power
Control
13-bit high resolution D/A Converter for
Automatic Frequency Control
Programmable Radio RX filter
2 Channels bi-directional Baseband Serial
Interface (BSI) with 3-wire or 4-wire control
GSM channel coding, equalization and A5/1 and
A5/2 ciphering
GPRS GEA 1 and GEA 2 c iphering
Programmab le GSM/ GPRS Modem
Packet Switched Data with CS1/CS2/CS3/CS4
coding schemes
GSM Circuit Switch Data
GPRS Class 12
Voice Interface an d Voice Front End
Two microphone inputs sharing one low noise
amplifier with programmable gain and automatic
gain control (AGC) mechanis m
Voice power amp lifier with programmable gain
nd
2
D/A Converter for voice downlin k path
order Sig ma-Delta A/D Converter for voice
uplink path
10-Pin Baseband Parallel Interface (BPI) with
programmab le driving strength
Multi-band support
Voice and Modem CODEC
Dial tone generation
Voice Me mo
Noise Reduction
Echo Suppression / Echo Cancellation
Advanced Sidetone Oscillat ion Reduction
Digital sidetone generator with programmable
gain
Two programmable acoustic compensation filters
GSM/GPRS quad vocoders for adaptive multirate
(AMR), enhanced full rate (EFR), full rate (FR)
and half rate (HR)
Supports half-duplex hands-free operation
Compliant with GSM 03.50
FR erro r concealment
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MT6227 GSM/GP RS Baseband Processor Technical Brief Revision 1.00
1.3 Multi-Media Features
LCD/ NAND Flash Inter face
18-bit Parallel Interface supports 8/16 bit NAND
flash and 8/9/16/18 b it Parallel LCD
8/16 bit NAND Flash Controller with 1 -bit ECC
correction for mass storages
2 Chip selects available for high-density NAND
flash device
Serial LCD Interface with 8/9 bit format support
LCD Con troller
Hardware accelerated display
Supports simultaneous connection to up to 2
parallel LCD and 1 serial LCD modules
Supports format: RGB332, RGB444, RGB565,
RGB666, RGB888
Supports LCD panel maximum resolution up to
800x600 at 16bpp
Automatic Exposure Control
Automatic focus control
Automatic White Balance Control
Edge Enhancement Support
Flexible I/O voltage of 1.8V ~ 2.8V
JPEG Decoder
ISO/IEC 10918-1 JPEG Baseline and Progressive
modes
Supports all possible YUV fo rmats, including
grayscale format
Supports all DC/AC Huffman table parsing
Supports all quantization table parsing
Supports restart interval
Supports SOS, DHT, DQT and DRI marker
parsing
Supports hardware display rotation
Capable of combining display memories with up to
4 blending layers
Accelerated Gamma correction with
programmable gamma table.
Image Signal Processor
8/10 bit Bayer format image input
YUV422 format image input
Capable of processing image of size up to 2M
pixels
Lens shading compensation
Defect pixel correction
Synchronous flash light control
Optical black correction
Color Correction Matrix
IEEE Std 1180-1990 IDCT Standard Co mpliant
Supports progressive image processing to
minimize storage space requirement
Supports reload-able DMA for VLD stream
JPEG Enc oder
ISO/IEC 10918-1 JPEG baseline mode
ISO/IEC 10918-2 Compliance
Supports YUV422 and grayscale formats
Standard DC and AC Huffman tables
Provides 14 levels of encode quality
Image Data Processing
High throughput hardware scalar capable of
tailoring image to arbitrary size
Horizontal scaling in averaging method
Vertical scaling in bilinear method
Gamma Co rrection
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