Maxon MX5010 Service Manual Block Diagram
N
F
N
2
R
FVRF
C
A
r
K
N
C
A
N
N
A
R
VPW
VCCDVBAT VTI
VUH
VBAT
VCCD
SIM and Power
Management
(5)
TAPRESNT
LAM
PWRON0
SRLDATA
SRLCLK
BOOSTE
SIME
SIMDATA
SIMCLK
SIMRST
VUHF VBAT
VRF VTIC VCCD VBAT VPWRVCCD
PACOUT
TXEN1
RXEN1
Radio
Interface
Block
(2)
SYNDAT
SYNLE
SYNCLK
SYNE
TXEN0
SYNRE
VC4
VC1
Baseband
udio Interface
(3)
TXIP
TXI
TXQP
TXQN
RXIP
RXIN
RXQP
RXQN
PO
PCONT
RESETB
FRT
HDSTDET
BPDET
CTLRT
CTLCLK
CTLDATA
RPNSDAT
SYSCLK
RXCL
RXDAT
RXRT
CDCCLK
CDCRT
ENCDATA
DECDATA
VCONT
SDI
SYN
SCLK
IRQ
GSM Processo
(4)
Title
MX-5010 System Block Diagram
System
MX-5010
FCC ID
AWWMX5010
PROPRIETARY INFORMATION
Any part of this document must not be disclosed to third parties without prior written permission.
HW Rev.
2.50
Date
2002/05/08
Drawn by
K.Tsuchida
Page
1 of 5
Chk’d by
S.Ohmomo
Approved by
K.Sakayori
Maxon Telecom Co., Ltd.
N
N
E
A
r
A
2
2
A
l
A
CONT
VC1
VC4
IC101
T/R SW
F_tx
Q101
VRF
IC201 PA CX77304
MP101
NTENNA
P101
RF
Connecto
F_tx
F201
Coupler
D201
RF Detector
VTIC
PACOUT2
TXEN0
PACOUT2
F_rx
F101
GSM Rx SAW
[ARFCN Allocation]
EGSM: 975-1023, 0-124
DCS: 512-885
PCS: 512-810
[Frequency Calculation]
F_Tx = K/3 * (2-D2/D1) * F_lo
F_Rx = 2 / 3 * F_lo
(EGSM band)
F_Rx = 4 / 3 * F_lo
(DCS/PCS band)
F102
DCS Rx SAW
F103
PCS Rx SAW
Table A. T/R Switch Control
Symbol EGSM DCS PCS
Tx Rx Tx Rx Tx Rx
VC1Mo L L H L H L
CONT2 L L L L L H
VC4 H L L L L L
Table B. Frequency Plan
Mode Symbol Frequency Plan [MHz]
EGSM DCS PCS
Transmit F_Tx 880.2 - 914.8 1710.2 - 1784.8 1850.2 - 1909.8
F_lo 1473.0 - 1543.7 1344.0 - 1414.5 1449.7 - 1516.6
F_tx_if 90.5 - 114.4 74.8 - 104.8 80.5 - 112.3
Receive F_Rx 925.2 - 959.8 1805.2 - 1879.8 1930.2 - 1989.8
F lo 1387.8 - 1439.7 1359.9 - 1409.9 1447.7 - 1492.4
IC203
PAC AMP
-
+
VRF
F_tx_if
K
X2
TXIFP
TXIFN
D2
D1
X2
Rx Path
DC offset
Canceller
DC offset
Canceller
LPF
V-BAT
TXDCS/PCS
PC /
Band
Sel.
TXGSM
TXINP
-
+
VUHF
LPF
PCO
PCO1
Fractional-N
PLL
Band
Select
TXVCO
TUNE
Sx (Synthesizer)
F_lo
ux Contro
TXCPO
CP
PFD
1/3
PSN
PSN
FILTP
FILTN
Tx Path
LPF
PSN
LPF LPF LPF
LPF LPF LPF
LPF
X2
Rx/Tx Control
ux Control
IP2 Calibration
DC Offset Timing
Sx Register 1/2
DC offset
Canceller
LPF
DC offset
Canceller
VCCD
Control
Registers
DC offset
Canceller
DC offset
Canceller
TXIP
TXI
TXQP
TXQ
SYNDAT
SYNL
SYNCLK
SYNEN
TXEN1
RXEN1
SYNREF
RXIP
RXIN
RXQP
RXQN
IC301 DCR CX74017
Title
Radio Interface Block Diagram
System
MX-5010
FCC ID
AWWMX5010
PROPRIETARY INFORMATION
Any part of this document must not be disclosed to third parties without prior written permission.
HW Rev.
2.50
Date
2002/05/08
Drawn by
K.Tsuchida
Page
2 of 5
Chk’d by
S.Ohmomo
Approved by
K.Sakayori
Maxon Telecom Co., Ltd.
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