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MAX14578AEETE
Schematic [ru]
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Maxim MAX14578AEETE, MAX14578AEEWC, MAX14578EETE, MAX14578EEWC Schematic [ru]

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MAX14578E/MAX14578AE
EVALUATION KIT AVAILABLE
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
USB Battery Charger Detectors
General Description
The devices implement USB Battery Charging Revision
1.1-compliant detection logic including data contact detection, D+/D- short detection, charging downstream port identification, and optional USB dead-battery charg­ing support. Dead-battery charging support features a 45-minute (max) charge timer and weak battery voltage monitor controlled by I only.) The MAX14578AE features an enable (EN) input and an LDO output.
In addition, the internal USB switch is compliant to Hi-Speed USB, full-speed USB, and low-speed USB signals. The devices feature low on-resistance, low on-resistance flatness, and very low capacitance. The devices also feature high-ESD protection up to Q15kV Human Body Model on the CD+ and CD- pins.
In addition, the MAX14578E/MAX14578AE feature Apple and Sony charger detection that allows identification of resistor-divider networks on D+/D-.
The MAX14578E/MAX14578AE are available in both a 12-bump, 0.4mm pitch, 1.3mm x 1.68mm WLP package and 16-pin TQFN package, and operate over the -40NC to +85NC extended temperature range.
2
C communication (MAX14578E
Features
S Compliant to USB Battery Charging Revision 1.1
S Data Contact Detection for Foolproof Connector
Insertion Detection
S USB Dead-Battery Charging Support
S Charging Downstream Detection
S Apple/Sony Charger Detection
S Dedicated Charger Detection
S China YD/T1591-Compliant Charger Detection
S Internal Switches Isolate the USB Transceiver
During the Charger Detection Process
S V
S Device Status Change Interrupt
S Low Supply Current
S High-ESD Protection on CD+ and CD-
Connection Capable of 28V
BUS
±15kV Human Body Model ±8kV IEC 61000-4-2 Contact Discharge
Applications
DSC and Camcorder
Media Players
Cell Phones
e-Book Readers
Mobile Internet Devices (MIDs)
Ordering Information/Selector Guide
PART I2C
MAX14578EEWC+T Yes No No
MAX14578EETE+T Yes No No MAX14578AEEWC+T No Yes Yes MAX14578AEETE+T No Yes Yes
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
T = Tape and reel.
EN
LDO TEMP RANGE PIN-PACKAGE TOP MARK
-40NC to +85NC
-40NC to +85NC
-40NC to +85NC
-40NC to +85NC
12 WLP +ABW
16 TQFN-EP* AJA
12 WLP +ABX
16 TQFN-EP* AJB
19-5821; Rev 2; 9/12
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) BAT, INT, SDA, SCL, CE0, CE1, CE2, EN LOUT
........................................... -0.3V to (VB + 0.3V, 6V) (min)
V
..........................................................................-0.3V to +30V
B
.......... -0.3V to +6.0V
Switch Disabled or CP_ENA = 1 (Note 1)
CD+, CD­TD+, TD-
........................................ -2.1V to (V
......................................... -0.3V to (V
SWPOS SWPOS
+ 0.3V) + 0.3V)
Switch Enabled or CP_ENA = 0 (Note 2)
CD+, CD-, TD+, TD-
.......................-0.3V to (V
VCCINT
+ 0.3V)
Continuous Current into LOUT Continuous Current into Any Other Terminal Continuous Power Dissipation (T
WLP (derate 13.7mW/NC above +70NC)
TQFN (derate 20.8mW/NC above +70NC)..................1667mW
Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature (reflow)
..................................... ±150mA
.................. ±50mA
= +70NC)
A
................. 1096mW
........................ -40NC to +85NC
.................................................. +150NC
......................... -65NC to +150NC
......................................+260NC
Note 1: V Note 2: V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SWPOS VCCINT
= (V
= (V
or 3.3V) (min)
VCCINT
[(VB or 4.2V) (min)]) (max)
BAT,
PACKAGE THERMAL CHARACTERISTICS (Note 3)
WLP
Junction-to-Ambient Thermal Resistance (B
) ..........73°C/W
JA
Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-lay-
er board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
TQFN
Junction-to-Ambient Thermal Resistance (BJA) ..........48°C/W
Junction-to-Case Thermal Resistance (B
) .............. 10°C/W
JC
ELECTRICAL CHARACTERISTICS
(V
= +2.8V to +5.5V, VB = +3.5V to +5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at V
BAT
V
= +5.0V, TA = +25NC.) (Note 4)
B
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS
Supply Voltage Range
Internal Positive Switch Regulator
Internal Negative Switch Regulator
V
UVLO V
BAT
UVLO V
V
BUS
V
BAT
V
B
V
SWPOS
V
SWNEG
BATUVLO
BUSUVLO
V
= 4.2V, VB = 0V 0.90 1.65 2.45 V
BAT
V
= 0V, VB = 5.5V 1.0 1.33 3.30 V
BAT
= +3.6V,
V
BAT
V
= 0V, CP_ENA = 0,
B
2.8 5.5
3.5 28
3.25 3.4 3.6 V
-2.06 -1.90 -1.76 V
USBSWC = 0
BAT Supply Current I
BAT
MAX14578E
= +4.2V,
V
BAT
V
= 0V, CP_ENA = 1,
B
USBSWC = 1, V
SDA
= V
SCL
= 1.8V
1 2.5
34.5 59
= +3.6V,
BAT
V
FA
2
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.8V to +5.5V, VB = +3.5V to +5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at V
BAT
V
= +5.0V, TA = +25NC.) (Note 4)
B
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
= +3.6V,
BAT
V
< V
B
V
= +3.6V
EN
V
= +4.2V,
BAT Supply Current I
BAT
MAX14578AE
BAT
V
= 0V, VEN = 0V
B
Supply current increase when V V
= +4.2V
BAT
= +5.5V,
V
B
MAX14578E
CP_ENA = 0, USBSWC = 0
V
= +5.5V,
B
V
Supply Current I
V
B
VB
MAX14578AE
= 0V
EN
= +5.0V,
V
B
V
= 0V
EN
= +5.5V,
V
B
V
= +5.5V
EN
LOUT (LDO OUT) (MAX14578AE ONLY)
LOUT Current Limit I
LOUT Voltage V
LOUT Debounce Time t
LOUT
LOUT
LOUT_DEB
I
= 10mA, VB = 5.0V 4.87 4.94
LOUT
= 0mA, VB = 6.0V 4.0 5.3 5.5
I
LOUT
VB = 5.0V to V
= 4.5V 20 ms
LOUT
LOUT Turn-On Time 100 Themal Shutdown +141 Themal Shutdown Hysteresis 20
CHARGER DETECTION
V V V I
DP_SRC
CD+ and CD- Sink Current
R TD+ Pulldown Resistor R TD- Pulldown Resistor R Charger Detection Weak Sink I
Voltage V
DP_SRC
DAT_REF
LGC
Voltage V
Voltage V
Current I
Resistance R
CD
DP_SRC
DAT_REF
LGC
DP_SRC
I
CD+_SINK
I
CD-_SINK
CD
TD+_DWN
TD-_DWN
WEAK
VBRAW
= 1.6V,
EN
,
1.3 30
1.3 3.5
190 295
4.1 mA
0.5 0.7 V
0.25 0.4 V
0.8 2.0 V
6.6 11
50 150
200 330 500
15 20 25
14.25 24.8
= +3.6V,
BAT
1 2.5
FA
87 140
FA
FA
75 125
FA
95 mA
V
Fs NC NC
FA
FA
kI kI kI
0.18
FA
3
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.8V to +5.5V, VB = +3.5V to +5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at V
BAT
V
= +5.0V, TA = +25NC.) (Note 4)
B
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VBUS25 Ratio VBUS25
VBUS47 Ratio VBUS47
Reference ratio for special charger as a percentage of V
voltage, VB = 5V
BUS
Reference ratio for special charger as a percentage of V
voltage, VB = 5V
BUS
24 26 29 %
44 47 50 %
VBUS60 Ratio VBUS60 57.5 60.3 63.5 % DCD M Time t DCD C Time t
MDEB
CDEB
All comparators 20 30 40 ms All comparators 5 ms
DCD Timer 2 s
Charger-Detect Source Time t
Charger-Detect-Type Detection Time
Charger-Detect Delay Time t
Attach to CE1 and CE2
V
B
Output Time
V
Raw-Detect Threshold V
B
-Detect Threshold V
V
B
V
-Detect Threshold
B
Hysteresis
DP_SRC_ON
t
DP_RES_ON
DP_SRC_HICRNT
t
VBSW
VBRAW
VBDET
V
VBDET_HYS
DCHK = 0 40 DCHK = 1 625
120 ms
40 80 ms
From VB > V
or CHG_TYP_M = 1
VBDET
(DCHK = 0) to CE1 and/or CE2 change
From V
B
> V
or CHG_TYP_M = 1
VBDET
(DCHK = 1) to CE1 and/or CE2 change
1.7 2.6 3.5 V
3.2 3.5 3.3 V
38 50 mV
1450
USB ANALOG SWITCHES (CD-, CD+)
Analog-Signal Range V
On- Resistance R
On -Resistance Match Between Channels
On -Resistance Flatness R
Off-Leakage Current I
DN2, VDP2
ONUSB
DR
ONUSB
FLATUSB
LUSB(OFF)
CP_ENA = 0 (MAX14578E) 0 V CP_ENA = 1 V
V
= +3.0V, I
BAT
V
, V
= 0 to +3.0V
CD-
= +3.0V, I
, V
= +400mV
CD-
= +3.0V, I
, V
= 0 to +3.3V
CD-
= 4.2V, switch open, V
= +0.3V or +2.5V; V
V V
V V
V V
CD+
BAT CD+
BAT CD+
BAT CD-
CD+
CD+
CD+
= I
= I
= I
= 10mA,
CD-
= 10mA,
CD-
= 10mA,
CD-
TD+
CD+
or V
=
TD-
SWNEG
3.3 6
0.06 0.26
=
-360 +360 nA
VCCINT
V
SWPOS
+2.5V or +0.3V
On-Leakage Current I
LUSB(ON)
= 4.2V, switch closed, V
BAT
V
= +0.3V or +2.5V
CD-
CD+
or
-360 +360 nA
V
DIGITAL SIGNALS (INT, SCL, SDA, EN, CE0, CE1, CE2)
Input Logic-High V Input Logic-Low V Input Leakage Current I Open-Drain Low V
INLEAK
ODOL
IH
IL
I
= 1mA 0.4 V
SINK
1.4 V
-1 +1
= +3.6V,
BAT
520
0.5
0.4 V
ms
ms
V
I
I
I
FA
4
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.8V to +5.5V, VB = +3.5V to +5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at V
BAT
V
= +5.0V, TA = +25NC.) (Note 4)
B
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
-
V
Output Logic-High V
Output Logic-Low V
DYNAMIC (Note 5)
OH
OL
I
SOURCE
I
SINK
= 1mA
= 1mA 0.2 V
IO
0.2
= +3.6V,
BAT
V
Charge-Pump Delay Time t
Analog-Switch Turn-On Time t
Analog-Switch Turn-Off Time t
Break-Before-Make Delay Time
Off-Capacitance C
OFF
t
BBM
CP
ON
OFF
CP_ENA from 0 to 1 until switch on 1 ms
MAX14578E, I2C STOP to switch on, R
= 50I
L
MAX14578E, I2C STOP to switch off, R
= 50I
L
RL = 50I, TA = +25NC
TD-, TD+, applied voltage is 0.5V
P-P
,
> 0
DC bias = 0V, f = 240MHz; CD-, CD+ not connected to TD-, TD+
On-Capacitance C
ON
-3dB Bandwidth BW V Off-Isolation V
2
C TIMING SPECIFICATIONS
I
2
C Max Clock f
I
Bus Free Time Between STOP and START Conditions
ISO
I2CCLK
t
BUF
TD-, TD+, applied voltage is 0.5V DC bias = 0V, f = 240MHz; CD-, CD+ connected to TD-, TD+; R
= 0.5V
CD_
P-P
RL = 50I, f = 20kHz, V
CD_
= 50I
L
= 0.5V
P-P
,
P-P
1.3
START Condition Setup Time 0.6
Repeat START Condition Setup Time
START Condition Hold Time t STOP Condition Setup Time t Clock Low Period t Clock High Period t Data Valid to SCL Rise Time t Data Hold Time to SCL Fall t
t
SU:STA
HD:STA
SU:STO
LOW
HIGH
SU:DAT
HD:DAT
90% to 90% 0.6
10% of SDA to 90% of SCL 0.6 90% of SCL to 10% of SDA 0.6 10% to 10% 1.3 90% to 90% 0.6 Write setup time 100 ns Write hold time 0 ns
ESD PROTECTION
CD+, CD-
Human Body Model ±15 IEC 61000-4-2 Contact Discharge ±8
0.1 1 ms
0.1 1 ms
Fs
2 pF
4.5 pF
1000 MHz
-60 dB
400 kHz
Fs
Fs
Fs
Fs Fs Fs Fs
kV
Note 4: All units are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by
Note 5: Guaranteed by design; not production tested.
design and not production tested.
5
Maxim Integrated
MAX14578E/MAX14578AE
01
USB Battery Charger Detectors
Typical Operating Characteristics
(V
= +4.2V, VB = +5.0V, C
BAT
= 1FF, CVB = 1FF, unless otherwise noted.)
BAT
BAT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.0
VB = 0V, CP_ENA = 0, USBSWC = 0
= V
V
1.5
1.0
BAT SUPPLY CURRENT (µA)
0.5
0
2.8 4.3
= 0V
SDA
SCL
TA = +85°C
BAT SUPPLY VOLTAGE (V)
TA = +25°C
3.83.3
BAT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
25
VB = 0V, CP_ENA = 0, USBSWC = 1
20
15
10
BAT SUPPLY CURRENT (µA)
5
TA = +85°C
TA = +25°C
TA = -40°C
TA = -40°C
10
VB = 0V, CP_ENA = 0, USBSWC = 0 V
MAX14578E toc01
MAX14578E toc04
8
6
4
BAT SUPPLY CURRENT (µA)
2
0
2.8 4.3
200
150
100
SUPPLY CURRENT (µA)
B
V
50
BAT SUPPLY CURRENT INCREASE
vs. SUPPLY VOLTAGE
= V
= 1.8V
SDA
SCL
TA = +85°C
TA = +25°C
TA = -40°C
3.83.3
BAT SUPPLY VOLTAGE (V)
VB SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX14578E)
V
= +3.6V, CP_ENA = 0, USBSWC = 0
BAT
TA = +85°C
TA = +25°C
TA = -40°C
50
VB = 0V, CP_ENA = 1, USBSWC = 0
40
MAX14578E toc02
30
20
BAT SUPPLY CURRENT (µA)
10
0
2.8 4.3
vs. SUPPLY VOLTAGE (MAX14578AE)
200
V
MAX14578E toc05
150
100
SUPPLY CURRENT (µA)
B
V
50
BAT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
TA = +85°C
TA = +25°C
BAT SUPPLY VOLTAGE (V)
VB SUPPLY CURRENT
= +3.6V, EN = HIGH
BAT
TA = +85°C
TA = +25°C
MAX14578E toc03
TA = -40°C
3.83.3
MAX14578E toc06
TA = -40°C
0
2.8 4.3 BAT SUPPLY VOLTAGE (V)
3.83.3
LOUT VOLTAGE REGULATION (MAX14578AE)
6.0
I
= 1mA
LOUT
5.5
5.0
4.5
LOUT VOLTAGE (V)
4.0
3.5
3.0
4.0 7.0 VB SUPPLY VOLTAGE (V)
TA = +85°C
TA = +25°C
TA = -40°C
6.56.05.55.04.5
6
MAX14578E toc07
LOUT VOLTAGE (V)
0
4.5 5.5 VB SUPPLY VOLTAGE (V)
5.35.14.94.7
LOUT LOAD REGULATION (MAX14578AE)
6.0
VB = 6V
5.5
5.0
4.5
4.0
3.5
3.0
TA = +25°C TA = -40°C
LOUT CURRENT (mA)
TA = +85°C
8642
0.5
0.4
MAX14578E toc08
0.3
0.2
0.1
-0.1
-0.2
DIFFERENTIAL SIGNAL (V)
-0.3
-0.4
-0.5
0
0
4.5 5.5 VB SUPPLY VOLTAGE (V)
ANALOG-SWITCH EYE DIAGRAM
0
0
TIME (x 10-9s)
5.35.14.94.7
MAX14578E toc09
2.01.81.4 1.60.4 0.6 0.8 1.0 1.20.2
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
Typical Operating Characteristics (continued)
(V
= +4.2V, VB = +5.0V, C
BAT
= 1FF, CVB = 1FF, unless otherwise noted.)
BAT
CD+/CD- ON-RESISTANCE
VOLTAGE
vs. V
5
= 10mA
I
CD_
4
3
TA = +25°C
2
CD+/CD- ON-RESISTANCE (Ω)
1
0
0 3.0
CD_
V
VOLTAGE (V)
CD_
2.0
1.5
1.0
TA = +85°C
MAX14578E toc10
-20
-40
TA = -40°C
2.52.01.51.00.5
-60
CD+/CD- FREQUENCY RESPONSE (dB)
-80
LOGIC-INPUT THRESHOLD
vs. SUPPLY VOLTAGE
V
IH
CD+/CD- FREQUENCY RESPONSE
0
ON-LOSS
OFF-ISOLATION
0.01 10,000 FREQUENCY (MHz)
1001
CE_ vs. V
USB CHARGING DOWNSTREAM PORT, USB COMPLIANT
(USB_CPL = 1, USBSWC = 0, V
MAX14578E toc13
CD+/CD- LEAKAGE CURRENT
50
40
MAX14578E toc11
30
20
10
CD+/CD- LEAKAGE CURRENT (nA)
0
-40 85
CONNECTION (MAX14578E)
BUS
TD+
MAX14578E toc14
vs. TEMPERATURE
ON-LEAKAGE
OFF-LEAKAGE
TEMPERATURE (°C)
= 3V)
V
B
5V/div
V
CD+
0.5V/div
MAX14578E toc12
603510-15
V
0.5
LOGIC-INPUT THRESHOLD (V)
0
2.8 5.5 BAT SUPPLY VOLTAGE (V)
CE_ vs. V
BUS
IL
CONNECTION (MAX14578E)
APPLE 1A CHARGER, USB COMPLIANT
(USB_CPL = 1, USBSWC = 0, V
20ms/div
5.24.94.64.34.03.73.43.1
= 3V)
TD+
MAX14578E toc15
V
B
5V/div
V
CD+
2V/div
V
CE2
5V/div
V
CE1
5V/div
40ms/div
CE_ vs. V
CONNECTION (MAX14578AE)
BUS
USB CHARGING DOWNSTREAM PORT
(V
= 3V)
TD+
100ms/div
MAX14578E toc16
V
CE2
5V/div
V
CE1
5V/div
V
B
5V/div
V
CD+
2V/div
V
CE2
5V/div
V
CE1
5V/div
7
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Pin/Bump Configurations
TOP VIEW
(BUMP SIDE DOWN)
A
B
C
() MAX14578AE ONLY.
MAX14578E/MAX14578AE
2413
+
CD+ CD- V
SCL
GND
(EN)
TD+ TD- BAT CE2
SDA
(CE0)
B
WLP
INT
(LOUT)
CE1
TOP VIEW
SDA
13
(CEO)
SCL
14
(EN)
15
TD-
16
N.C.
() MAX14578AE ONLY. *CONNECT EP TO GND.
N.C.
(LOUT_SNS)
CE2
12 10 9
11
MAX14578E
MAX14578AE
+
13
2
TD+
N.C. CE1
INT
EP*
4
N.C.
TQFN
(LOUT)
CD+
V
8
B
BAT
7
CD-
6
GND
5
Pin/Bump Description
PIN
NAME FUNCTIONMAX14578E MAX14578AE
TQFN-EP WLP TQFN-EP WLP
1 C1 1 C1 TD+ USB Transceiver D+ Connection
2, 3, 10, 16 — 2, 3, 16 — N.C. No Connection. Not internally connected.
4 A1 4 A1 CD+ USB Connector D+ Connection 5 B1 5 B1 GND Ground 6 A2 6 A2 CD- USB Connector D- Connection
7 C3 7 C3 BAT
8 A3 8 A3 V
9 A4 — —
INT
— — 9 A4 LOUT
— — 10 — LOUT_SNS Connect Externally to LOUT (MAX14578AE, TQFN Only) 11 B4 11 B4 CE1 Charger-Enable Control 1, Open-Drain Output 12 C4 12 C4 CE2 Charger-Enable Control 2, Open-Drain Output
13 B3 — — SDA
— — 13 B3 CE0 Charger-Enable Control 0, Open-Drain Output
— — 14 B2
EN
Battery Connection Input. Connect a 1FF capacitor as close as possible between BAT and GND.
USB Connector V as close as possible between V
B
Connection. Connect a 1FF capacitor
BUS
and GND for Q15kV ESD
B
protection.
Active-Low Interrupt Request, Open-Drain Output
+5.3V USB Transceiver V
Power Output. Connect a 1FF
BUS
capacitor as close as possible between LOUT and GND.
2
C Serial-Data Input/Output. Connect SDA to an external pullup
I resistor.
Active-Low Enable Input. Drive EN low to enable the charger ID detection and close the USB switches after charger detection is complete.
8
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
Pin/Bump Description (continued)
PIN
MAX14578E MAX14578AE
TQFN-EP WLP TQFN-EP WLP
14 B2 — — SCL
15 C2 15 C2 TD- USB Transceiver D- Connection
— — — — EP
MAX14578E Functional Diagram/Typical Application Circuit
NAME FUNCTION
I2C Serial-Clock Input. Connect SCL to an external pullup resistor.
Exposed Pad (TQFN Only). EP is internally connected to GND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point.
USB
TRANSCEIVER
PROCESSOR
AUDIO CODEC/
AMPLIFIER
V
CC
ID
D-
D+
INT
BATTERY
1µF
V
B
MAX14578E
V
IO
INT
SCLSCL
SDASDA
BAT
USB CHARGER DETECTION
CONTROL
LOGIC
CE1
CE2
V
V
IO
IO
PMIC/
CHARGER
GND
1µF
CD-TD-
CD+TD+
V
BUS
GND
D-
D+
ID
MICRO-B
USB
CONNECTOR
9
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
MAX14578AE Functional Diagram/Typical Application Circuit
USB
TRANSCEIVER
PROCESSOR
AUDIO CODEC/
AMPLIFIER
BATTERY
V
CC
ID
D-
D+
EN
LOUT
1µF 1µF
EN
BAT
1µF
V
IO
MAX14544
LDO
MAX14578AE
USB CHARGER DETECTION
CONTROL
LOGIC
CE2
CE1 CE0
V
B
V
BUS
CD-TD-
CD+TD+
GND
V
CC
GND
D-
D+
ID
MICRO-B
USB
CONNECTOR
BATTERY
10
IUSB DCM USUS
CHG
SWITCH MODE CHARGER
MAX8903/MAX8934
MAX8677
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
Table 1. Register Map
ADDRESS NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x00 DEVICE ID VENDOR_ID CHIP_REV
0x01
0x02 INTERRUPT CHG_TYP VBCOMP DBCHG DCD_T CHGRUN RFU
0x03
0x04
Table 2. Detailed Register Map
FIELD NAME READ/WRITE BIT DEFAULT DESCRIPTION
DEVICE ID (I
VENDOR_ID Read Only [7:4] 0010 Vendor Identification
CHIP_REV Read Only [3:0] 0001 Chip Revision
CONTROL 1 (I
INTPOL Read/Write 7 0
CONTROL
1
CONTROL
2
CONTROL
3
2
C ADDRESS = 0x00)
2
C ADDRESS = 0x01)
INTPOL INTEN USBSWC CP_ENA LOW_POW DCHK CHG_TYP_M USB_CHGDET
DCD_EN DB_EXIT DB_IDLE SUS_LOW CE_FRC CE
RFU RFU RFU CDP_DET USB_CPL SFOUT_EN SFOUTASRT DCD_EXIT
Interrupt Polarity 0 = Active low 1 = Active high
INTEN Read/Write 6 0
USBSWC Read/Write 5 0
CP_ENA Read/Write 4 0
LOW_POW Read/Write 3 1
DCHK Read/Write 2 0
CHG_TYP_M Read/Write 1 0
Interrupt Enable. If interrupt is disabled, pending interrupts are not cleared and the INT pin deasserts. INTEN is a global setting to mask all interrupts. 0 = Interrupt disabled 1 = Interrupt enabled
Opens/Closes USB Switch 0 = Switch open 1 = Switch closed
Charge-Pump Enable 0 = Charge pump disabled 1 = Charge pump enabled
Low-Power Mode 0 = Low-power mode disabled; oscillator/bandgap always on 1 = Low-power mode enabled; oscillator/bandgap turned off under the following conditions: no V and CP_ENA = 0
Charger-Type Source-Detection Time 0 = DCHK, t 1 = DCHK, t
Charger-Type Manual-Detection Enable. Set CHG_TYP_M to 1 to force the internal logic to open the USB switches and perform a charger-type detection. After the detection state matching completes, this bit resets to 0. 0 = Charger detection disabled 1 = Force a manual charge detection
DP_SRC_ON DP_SRC_ON
= 40ms = 625ms
, USBSWC = 0,
BUS
11
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Table 2. Detailed Register Map (continued)
FIELD NAME READ/WRITE BIT DEFAULT DESCRIPTION
Charger-Detection-Enable Start. Charger detection starts
USB_CHGDET Read/Write 0 1
INTERRUPT (I
CHG_TYP Read Only [7:5] 000
2
C ADDRESS = 0x02)
with any change in V 0 = Charger detection disabled 1 = Charger detection enabled
Output of USB Charger Detection 000 = Nothing attached 001 = USB cable attached 010 = Charging dowstream port: current depends on USB operating speed 011 = Dedicated charger: current up to 1.8A 100 = Special charger: 500mA max 101 = Special charger: current up to 1A 110 = RFU 111 = Dead-battery charging: 100mA max
.
B
VBCOMP Read Only 4 0
DBCHG Read Only 3 0
DCD_T Read Only 2 0
CHGRUN Read Only 1 0
RFU Read Only 0 0 Reserved
2
CONTROL 2 (I
DCD_EN Read/Write 7 1
C ADDRESS = 0x03)
Output of V interrupt. 0 = V 1 = VB R V
Dead-Battery Charger Mode. If DBCHG = 1, the 45-minute timer is running. 0 = Not in dead-battery charge mode 1 = In dead-battery charge mode
Data-Contact Detection (DCD) Time Wait. DCD_T generates an interrupt after a 0-to-1 transition. 0 = Data contact detection not running 1 = Data contact detection running for > 2s
Charger-Detection State Machine Running. For information only—no interrupt generated. 0 = Charger detection not running 1 = Charger detection running (DCD, dead battery, D+/D­short)
DCD Enable. If DCD_EN = 1, D+/D- is tested for a short after DCD passes. If DCD_EN = 0, DCD is skipped and D+/D- short detection begins when V CHG_TYP_M = 1. If DCD is stuck (DCD_T) = 1, setting DCD_EN = 0 bypasses DCD and D+/D- short detection begins. 0 = Disabled 1 = Enabled
Comparator. Changes in VBCOMP triggers
B
< V
B
VBDET
VBDET
BUS
is connected or
12
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
Table 2. Detailed Register Map (continued)
FIELD NAME READ/WRITE BIT DEFAULT DESCRIPTION
Exit Dead-Battery Charge Mode. If DBCHG = 1, setting DB_EXIT to 1 stops the 45-minute timer, sets DBCHG to 0,
DB_EXIT Read/Write 6 0
DB_IDLE Read/Write 5 0
SUS_LOW Read/Write 4 0 (1)*
CE_FRC Read/Write 3 0
and leaves CHG_EN = 1. DB_EXIT is automatically reset to 0 if V 0 = Do not exit dead-battery mode 1 = Exit dead-battery mode
Dead-Battery Idle Mode. DB_IDLE = 1 in dead-battery mode to forces the USB switch to close. DB_IDLE is automatically reset when the USB switch is closed. 0 = Dead-battery mode off or test completed 1 = Dead-battery mode on or test still needed
Suspend Mode Selection 0 = When the charger is disabled, CE1 = CE2 = 1 1 = When the charger is disabled, CE1 = CE2 = 0
CE Outputs Force Enable 0 = CE outputs follow the charger-detection finite state machine (FSM) 1 = CE outputs follow the CE[2:0] register regardless of the result from the charger-detection FSM
reaches the dead-battery threshold.
BAT
CE Outputs (CE2, CE1, CE0). If CE_FRC = 0, registers are
CE Read/Write [2:0] 000
2
CONTROL 3 (I
RFU Read/Write [7:5] 000 Reserved
CDP_DET Read/Write 4 0
USB_CPL Read/Write 3 1 (0)*
SFOUT_EN Read/Write 2 0 (1)*
SFOUTASRT Read/Write 1 1
DCD_EXIT Read/Write 0 1
Note: CP_ENA, DCHK, USB_CHGDET, DCD_EN, SUS_LOW, CE_FRC, CE, USB_CPL, SFOUT_EN, SFOUTASRT, and DCD_EXIT can be configured to have different default values. Contact the factory for more information.
*Default value for MAX14578AE only.
C ADDRESS = 0x04)
set by the result of charger FSM. If CE_FRC = 1, registers are set by I
0 = Normal detection 1 = Resistive detection
USB Compliance 0 = Device is not USB compliant 1 = Device is USB compliant
LOUT Enable 0 = LOUT off 1 = LOUT on as per SFOUTASRT
LOUT Assert Timing 0 = LOUT asserts when the charger-detection FSM completes 1 = LOUT asserts after valid V
Exit Charger-Type-Detection Routine After DCD_T is Set to 1 0 = Disabled 1 = Enabled
2
C command only.
voltage detection
BUS
13
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Detailed Description
The MAX14578E/MAX14578AE are USB charger detec­tors compliant with USB Battery Charging Revision 1.1. The USB charger-detection circuitry detects USB stan­dard downstream ports (SDPs), USB charging down­stream ports (CDPs), or dedicated charger ports (DCPs), and controls an external lithium-ion (Li+) battery charger.
2
The MAX14578E features I MAX14578AE features an EN pin and an LDO output pin.
The internal USB switch is compliant to Hi-Speed USB, full-speed USB, and low-speed USB signals. Both devic­es feature low on-resistance, low on-resistance flatness, and very low capacitance.
The typical Micro/Mini-USB connector has five signal lines: USB power, two USB signal lines (D-, D+), ID line, and ground. The USB power on the Micro/Mini-USB con­nector connects to V The two USB signal lines, D- and D+, connect to CD- and CD+.
The MAX14578E/MAX14578AE support Hi-Speed (480Mbps), full-speed (12Mbps), and low-speed USB (1.5Mbps) signal levels. The USB channel is bidirectional and has low 3.3I (typ) on-resistance and 4.5pF (typ) on-capacitance. The low on-resistance is stable as the analog input signals are swept from ground to V for low signal distortion.
B
C communication, while the
Input Sources and Routing
on the MAX14578E/MAX14578AE.
USB (CD-, CD+)
SWPOS
LOUT features a 100mA (typ) current limit to protect the device in the event of a short circuit.
Interrupts
The MAX14578E generates an interrupt for any change in VBCOMP, and when DBCHG or DCD_T transitions from 0 to 1. The INTEN bit in the CONTROL 1 register (0x01) enables interrupt output. When INTEN is set to zero, all interrupts are masked but not cleared. A read to the INTERRUPT register (0x02) is required to clear interrupts.
Detection Debounce
To avoid multiple interrupts at the insertion of an acces­sory and for added noise/disturbance protection, a 30ms (typ) debounce timer is present that requires an inserted or removed state hold for the debounce time before it sends an interrupt.
Low-Power Modes
The MAX14578E has two I2C bits in the CONTROL 1 register (0x01) dedicated to low-power operation: LOW_POW and CP_ENA.
LOW_POW sets low-power mode. In low-power mode, the internal oscillator is turned off under the following conditions: no V When enabled, all switches are high impedance (note that no negative rail voltage can be applied).
CP_ENA controls the charge pump required for proper operation of the analog switches. When set to disable, no negative rail voltage can be applied. A factory default sets CP_ENA = 0 automatically.
, USBSWC = 0, and CP_ENA = 0.
BUS
LOUT LDO Output (MAX14578AE Only)
The LOUT LDO provides a 5.3V (typ) output, used to power a USB transceiver. Most USB transceivers are powered from a 3.3V or higher voltage that is difficult to derive from a Li+ battery. One solution is to power the transceivers from the USB V can rise as high as +28V in a fault condition. The LOUT pin provides a voltage-limited supply that protects the USB transceiver from these high voltages. When V rises above 9.0V (typ), the MAX14578AE detects an overvoltage fault and LOUT goes to 0V. Additionally,
14
power; however, V
BUS
BUS
BUS
USB Charger Detection
The MAX14578E includes internal logic to detect if a valid USB charger is connected. When a valid V applied to V register is set to 1, the MAX14578E/MAX14578AE begin the charger-type-detection sequence (see Figure 1). During the charger-type-detection sequence, the CD­and CD+ switches are open, and once the sequence completes, the switches return to their previous state. Figure 2 shows a timing diagram for an example char­ger-type-detection sequence.
or when CHG_TYP_M in the CONTROL 1
B
BUS
voltage is
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
DORMANT
CE_ = HI-Z
V
> V
B
VB < V
VBDET
DCD
BEGIN DCD TEST
VBDET
MAX14578E: USB_CHGDET = 1 MAX14578AE: V
= 0V
EN
NOT DCD COMPLIANTDCD COMPLIANT
D+/D- SHORT TEST
DCP/CDP TEST
() MAX14578AE ONLY.
Figure 1. Charger-Type-Detection Sequence
V
B
DCD START
ENABLE STANDARD DOWNSTREAM
PORT DETECTION
CHARGER CONFIGURATION
(USB SWITCH CLOSED)
CONFIGURE CE_
t
MDEB
t
DP_SRC_ON
SPECIAL CHARGER
SONY CHARGER TEST
APPLE CHARGER TEST
VB < V
VBDET
t
MDEBtMDEBtMDEB
Figure 2. Charger-Detection Timing
ENABLE
COMPARATORS
ENABLE CHARGING DOWNSTREAM
PORT DETECTION
LOUT ENABLE (MAX14578AE)
(SFOUTASRT = 0)
CHGRUN
V
DCD PASS D+/D- SHORT DEDICATED CHARGER
VBDET
CHG_TYP = 011
15
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
STANDARD USB
HOST CHARGING
DOWNSTREAM PORT
V
PU
LOAD
3.6V
HLPU 300kΩ
D+
HPD
14.25kΩ TO 24.8kΩ
V
PU
LOAD
3.6V
HLPU 300kΩ
D-
HPD
14.25kΩ TO 24.8kΩ
APPLE CHARGER
V
BUS
5.0V
ADPPU
75.0kΩ
D+
ADPPD
49.9kΩ
V
BUS
5.0V
ADMPU
43.2kΩ (FOR 1A)
75.0kΩ (FOR 0.5A)
D-
ADMPD
49.9kΩ
SONY CHARGER
V
BUS
5.0V
D+
V
BUS
5.0V
D-
SDPPU
5.1kΩ
SDPPD 10kΩ
SDPPU
5.1kΩ
SDPPD 10kΩ
DEDICATED CHARGER
V
BUS
5.0V
2MΩ (MIN)
D+
D-
2MΩ (MIN)
Figure 3. Standard USB Host/Charging Downstream Port, Apple Charger, Sony Charger, and Dedicated Charger
Figure 3 shows D+/D- terminations for a standard USB host/charging downstream port, an Apple charger, a Sony charger, and a dedicated charger.
The MAX14578E/MAX14578AE feature digital open-drain outputs—CE0 (MAX14578AE only), CE1, and CE2—to
Charger-Enable Control Outputs
control an external charger autonomously. See Table 3.
Table 3. Charger-Enable Control Outputs
SUS_LOW
EN
0 1 X X 1 1 1 1 1 X X 0 0 1 0 0 000 X 1 1 1 1 0 000 X 0 0 1 0 0 110 X 1 1 1 1 0 110 X 0 0 1 X 0 001 0 1 0 0 0 0 001 1 1 1 1 1 0 001 1 0 0 1 X 0 010 X 0 1 0 X 0 011 X 0 1 0 X 0 100 X 1 0 0 X 0 101 X 0 1 0 X 0 111 X 0 0 0
Note: When CE_FRC = 1, CE[2:0] are set by an I2C command. X = Don’t care.
16
CHG_TYP USB_CPL CE2 CE1 CE0
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
I2C Serial Interface (MAX14578E)
Serial Addressing
The MAX14578E operates as a slave device that sends and receives data through an I interface. The interface uses a serial-data line (SDA) and a serial-clock line (SCL) to achieve bidirectional commu­nication between master(s) and slave(s). A master (typi­cally a microcontroller) initiates all data transfers to and from the MAX14578E and generates the SCL clock that synchronizes the data transfer. The SDA line operates as both an input and an open-drain output. A pullup resis­tor is required on SDA. The SCL line operates only as an input. A pullup resistor is required on SCL if there are multiple masters on the 2-wire interface, or if the master
SDA
t
LOW
SCL
t
HD:STA
2
C-compatible 2-wire
t
SU:DAT
t
HD:DAT
t
HIGH
t
R
in a single-master system has an open-drain SCL output. Each transmission consists of a START condition (Figure
4) sent by a master, followed by the MAX14578E 7-bit slave address plus a R/W bit, a register address byte, one or more data bytes, and finally a STOP condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high (see Figure 5). When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission.
t
R
t
t
SU:STA
t
HD:STA
t
SU:STO
BUF
START
CONDITION
Figure 4. I2C Interface Timing Details
SDA
SCL
S
START
CONDITION
Figure 5. START and STOP Conditions
REPEATED
START CONDITION
STOP
CONDITION
CONDITION
START
CONDITION
P
STOP
17
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Bit Transfer
One data bit is transferred during each clock pulse (Figure 6). The data on SDA must remain stable while SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data (Figure 7). Thus, each byte transferred effectively requires nine bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse. The SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX14578E, it generates the acknowledge bit because the MAX14578E is the
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
recipient. When the MAX14578E is transmitting to the master, the master generates the acknowledge bit because the master is the recipient.
Slave Address
The MAX14578E has a 7-bit long slave address. The bit following a 7-bit slave address is the R/W bit, which is low for a write command and high for a read command. The slave address is 01011001 for read commands and 01011000 for write commands. See Figure 8.
Bus Reset
The MAX14578E resets the bus with the I2C START condition for reads. When the R/W bit is set to 1, the MAX14578E transmits data to the master, thus the mas­ter is reading from the device.
Figure 6. Bit Transfer
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
Figure 7. Acknowledge
SDA
SCL
Figure 8. Slave Address
0
MSB
START
CONDITION
S
CLOCK PULSE FOR
ACKNOWLEDGE
1 2 8 9
1
01 00
1 R/W
ACK
LSB
18
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
0101 001
S
REGISTER 0x01 WRITE DATA
d7 d6 d5 d4 d2 d1d3
Figure 9. Format for I2C Write
0101 001
S
REGISTER 0x01 WRITE DATA
ADDRESS = 0x58
ADDRESS = 0x58
0 = WRITE
0A A
Pd0 A
0 = WRITE
0A A
0000 0010
0000 0010
REGISTER ADDRESS = 0x01
S = START BIT
P = STOP BIT
A = ACK
N = NACK
d_ = DATA BIT
REGISTER ADDRESS = 0x01
REGISTER 0x02 WRITE DATA
d7 d6 d5 d4 d2 d1 d0d3 A
Figure 10. Format for Writing to Multiple Registers
Format for Writing
A write to the MAX14578E comprises the transmission of the slave address with the R/W bit set to zero, fol­lowed by at least one byte of information. The first byte of information is the register address or command byte. The register address determines which register of the MAX14578E is to be written by the next byte, if received. If a STOP (P) condition is detected after the register address is received, the MAX14578E takes no further action beyond storing the register address (Figure 9). Any bytes received after the register address are data bytes. The first data byte goes into the register selected by the register address, and subsequent data bytes go into subsequent registers (Figure 10). If multiple data bytes are transmitted before a STOP condition, these
d7 d6 d5 d4 d2 d1d3 d0
A/N
P
bytes are stored in subsequent registers because the register addresses autoincrements.
Format for Reading
The MAX14578E is read using the internally stored reg­ister address as an address pointer, the same way the stored register address is used as an address pointer for a write. The pointer autoincrements after each data byte is read using the same rules as for a write. Thus, a read is initiated by first configuring the register address by performing a write (Figure 11). The master can now read consecutive bytes from the MAX14578E, with the first data byte being read from the register address pointed by the previously written register address. Once the master sends a NACK, the MAX14578E stops send­ing valid data.
19
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
ADDRESS = 0x58
0101 0001
S P
ADDRESS = 0x59
0101 0011
S d7 d6 d5 d4 d2 d1 d0d3
Figure 11. Format for Reads (Repeated START)
0 = WRITE
1 = READ
A
A
0000 0010
Table 4. CE_ Outputs for Different Charger Control
SUS_LOW = 0
SUS_LOW = 1
() MAX14578AE only.
CE_
OUTPUTS
(CE0) 1 0 0 0 — EN
CE1 1 0 0 1 EN1 — CE2 1 0 1 0 EN2 —
CE_
OUTPUTS
(CE0) 1 0 0 0 USUS USUS
CE1 0 0 0 1 PEN1 DCM CE2 0 0 1 0 PEN2 IUSB
OFF 100mA 500mA I
OFF 100mA 500mA I
REGISTER ADDRESS = 0x01
REGISTER 0x00 READ DATA
SET
SET
MAX8606,
MAX8856
MAX8934,
MAX8677
A/N
A/N
MAX8814,
MAX8845
MAX8903
P
Applications Information
Charger Control
The MAX14578E charger-enable control outputs are ideal for autonomous external charger control. Table 4 shows example connections for various Maxim chargers.
Hi-Speed USB
Hi-Speed USB requires careful PCB layout with 45I single-ended/90I differential controlled-impedance matched traces of equal lengths.
Power-Supply Bypassing
Bypass VB and BAT with 1FF ceramic capacitors to GND as close as possible to the device.
Choosing I2C Pullup Resistors
I2C requires pullup resistors to provide a logic-high level to data and clock lines. There are trade-offs between power dissipation and speed, and a compromise must
20
be made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance even
2
when device is not in operation. I
C specifies 300ns rise times to go from low to high (30% to 70%) for fast-mode, which is defined for a clock frequency up to 400kHz (see
2
C Serial Interface (MAX14578E) section for details).
the I
To meet the rise time requirement, choose pullup resis­tors so that tR = 0.85 x R
PULLUP
x C
< 300ns. If the
BUS
transition time becomes too slow, the setup and hold times may not be met and waveforms may not be rec­ognized.
Extended ESD Protection
ESD-protection structures are incorporated on all pins to protect against electrostatic discharges up to ±2kV (Human Body Model) encountered during handling and assembly. The CD- and CD+ pins are further protected against ESD up to ±15kV (Human Body Model) and Q8kV IEC 61000-4-2 Contact Discharge without damage.
Maxim Integrated
MAX14578E/MAX14578AE
USB Battery Charger Detectors
HIGH-
VOLTAGE
DC
SOURCE
R
C
1MΩ
CHARGE-CURRENT-
LIMIT RESISTOR
C
S
100pF
R
D
1.5kΩ
DISCHARGE
RESISTANCE
STORAGE CAPACITOR
DEVICE
UNDER
TEST
HIGH-
VOLTAGE
DC
SOURCE
R
C
50MΩ TO 100MΩ
CHARGE-CURRENT-
LIMIT RESISTOR
C
S
150pF
R
D
330Ω
DISCHARGE
RESISTANCE
STORAGE CAPACITOR
Figure 12. Human Body ESD Test Model Figure 14. IEC 61000-4-2 ESD Test Model
I
(AMPS)
I
PEAK
100%
90%
36.8%
10%
(AMPS)
0
0
PEAK-TO-PEAK RINGING
I
r
(NOT DRAWN TO SCALE)
TIME
t
RL
t
DL
tR = 0.7ns TO 1ns
PEAK
100%
90%
10%
30ns
60ns
DEVICE UNDER
TEST
t
Figure 13. Human Body Current Waveform Figure 15. IEC 61000-4-2 ESD Generator Current Waveform
The VB input withstands up to ±15kV (HBM) if bypassed with a 1FF ceramic capacitor close to the pin. The ESD structures withstand high ESD both in normal operation and when the devices are powered down. After an ESD event, the MAX14578E/MAX14578AE continue to func­tion without latchup.
ESD Test Conditions
ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results.
The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. However, it does not specifically refer to integrated circuits. The MAX14578E/ MAX14578AE assist in designing equipment to meet IEC 61000-4-2 without the need for additional ESD-protection components.
The major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2, because series resistance is
IEC 61000-4-2
lower in the IEC 61000-4-2 model. Hence, the ESD with-
Human Body Model
Figure 12 shows the Human Body Model, and Figure 13 shows the current waveform it generates when dis­charged into a low-impedance state. This model con­sists of a 100pF capacitor charged to the ESD voltage of
stand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 14 shows the IEC 61000-4-2 model, and Figure 15 shows the current waveform for IEC 61000-4-2 ESD Contact Discharge test.
interest that is then discharged into the device through a 1.5kI resistor.
21
Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
12 WLP W121A1+1
16 TQFN T1633+5
PACKAGE
CODE
OUTLINE
NO.
21-0449
21-0136 90-0032
LAND
PATTERN NO.
Refer to
Application
Note 1891
22
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
0 3/11 Initial release —
1 2/12
2 9/12
Added TQFN package, corrected MAX14578E Functional Diagram/Typical Operating Circuit, and corrected default values for MAX14578AE in Table 2
Updated Package Thermal Characteristics section and VB supply current parameter for the MAX14578A
PAGES
CHANGED
1, 2, 8, 9,
13, 22
2, 3
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 23
©
2012 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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