MAXIM MAX1449 Technical data

General Description

The MAX1449 3.3V, 10-bit analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10­stage ADC architecture with wideband track-and-hold
(T/H), and digital error correction incorporating a fully dif­ferential signal path. The ADC is optimized for low­power, high-dynamic performance in imaging and digital
communications applications. The converter operates
from a single 2.7V to 3.6V supply, consuming only
186mW while delivering a 58.5dB (typ) signal-to-noise
ratio (SNR) at a 20MHz input frequency. The fully differ­ential input stage has a -3dB 400MHz bandwidth and
may be operated with single-ended inputs. In addition to
low operating power, the MAX1449 features a 5µA
power-down mode for idle periods.

An internal 2.048V precision bandgap reference is
used to set the ADC’s full-scale range. A flexible refer­ence structure allow’s the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input volt­age range.

Lower speed, pin-compatible versions of the MAX1449
are also available. Refer to the MAX1444 data sheet for
a 40Msps version, the MAX1446 data sheet for a
60Msps version, and the MAX1448 data sheet for 80Msps.

The MAX1449 has parallel, offset binary, CMOS-com­patible, three-state outputs that can be operated from

1.7V to 3.6V to allow flexible interfacing. The device is
available in a 5mm x 5mm 32-pin TQFP package and is
specified over the extended industrial (-40°C to +85°C)
temperature range.

________________________Applications

Ultrasound Imaging

CCD Imaging

Baseband and IF Digitization

Digital Set-Top Boxes

Video Digitizing Applications

Features

♦ Single 3.3V Operation
♦ Excellent Dynamic Performance

58.5dB SNR at f

IN

= 20MHz

72dBc SFDR at f

IN

= 20MHz

♦ Low Power

62mA (Normal Operation)
5µA (Shutdown Mode)

♦ Fully Differential Analog Input
♦ Wide 2Vp-p Differential Input Voltage Range
♦ 400MHz -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ CMOS-Compatible Three-State Outputs
♦ 32-Pin TQFP Package
♦ Evaluation Kit Available (MAX1448 EV Kit)

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

CLK

IN+

CONTROL

10

PIPELINE ADC

REF SYSTEM +

BIAS

OUTPUT
DRIVERS

D
E
C

REF

REFINREFOUT REFP COM REFN OE

V

DD

GND

OV

DD

OGND

D9–D0

IN-

PD

T/H

MAX1449

Functional Diagram

19-4802; Rev 2; 9/04

EVALUATION KIT

AVAILABLE

Ordering Information

Pin Configuration appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX1449EHJ -40°C to +85°C 32 TQFP

Pin-Compatible, Lower Speed

Selection Table

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART SAMPLING SPEED (Msps)

MAX1444 40

MAX1446 60

MAX1448 80

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 3.3V, OVDD= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, V

REFIN

= 2.048V, REFOUT connected to

REFIN through a 10kΩ resistor, V

IN

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs, f

CLK

= 105MHz, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical

values are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDD, OVDDto GND ...............................................-0.3V to +3.6V

OGND to GND.......................................................-0.3V to +0.3V

IN+, IN- to GND........................................................-0.3V to V

DD

REFIN, REFOUT, REFP,

REFN, and COM to GND........................-0.3V to (V

DD

+ 0.3V)

OE, PD, CLK to GND..................................-0.3V to (VDD+ 0.3V)

D9–D0 to GND.........................................-0.3V to (OV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

32-Pin TQFP (derate 18.7mW/°C above +70°C).....1495.3mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range ............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

CONDITIONS

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity INL fIN = 7.5MHz, T

A

≥ +25°C

LSB

Differential Nonlinearity DNL

f

IN

= 7.5MHz, no missing codes

guaranteed, T

A

≥ +25°C

LSB

Offset Error

Gain Error T

A

≥ +25°C, TA ≥ +25°C 0 ±2

ANALOG INPUT

Input Differential Range V

DIFF

Differential or single-ended inputs

V

Common-Mode
Voltage Range

V

COM

VDD/2

V

Input Resistance R

IN

Switched capacitor load 20 kΩ

Input Capacitance C

IN

5pF

CONVERSION RATE

Maximum Clock Frequency f

CLK

Data Latency 5.5
DYNAMIC CHARACTERISTICS (f

CLK

= 105.26MHz, 4096-point FFT)

f

IN

= 7.5MHz

fIN = 20MHz

Signal-to-Noise Ratio
(Note 1)

SNR

f

IN

= 50MHz 58

dB

fIN = 7.5MHz

fIN = 20MHz

Signal-to-Noise + Distortion (Up
to 5th Harmonic) (Note 1)

SINAD

f

IN

= 50MHz

dB

fIN = 7.5MHz 62 72

fIN = 20MHz 61 72

Spurious-Free Dynamic
Range (Note 1)

SFDR

f

IN

= 50MHz 70

dBc

SYMBOL

MIN TYP MAX UNITS

±0.75 ±2.4

±0.5 ±1.0
< ±1 ±1.7 % FS

±1.0

± 0.5

105 MHz

55.9 58.5

55.5 58.5

55.3 58.2

54.5 58.1

57.6

% FS

Cycles

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

_______________________________________________________________________________________ 3

PARAMETER

CONDITIONS

UNITS

fIN = 7.5MHz -72

fIN = 20MHz -72

Third-Harmonic Distortion
(Note 1)

HD3

f

IN

= 50MHz -70

dBc

Intermodulation Distortion (First 5
Odd-Order IMDs)
(Note 2)

IMD

f

1

= 38MHz at -6.5dB FS

f

2

= 42MHz at -6.5dB FS

-76 dBc

Third-Order Intermodulation
Distortion (Note 2)

IM3

f

1

= 38MHz at -6.5dB FS

f

2

= 42MHz at -6.5dB FS

-76 dBc

fIN = 7.5MHz -70 -62

fIN = 20MHz -70 -60

Total Harmonic Distortion
(First 5 Harmonics)
(Note 1)

THD

f

IN

= 50MHz -70

dBc

Small-Signal Bandwidth Input at -20dB FS, differential inputs

MHz

Full-Power Bandwidth FPBW Input at -0.5dB FS, differential inputs

MHz

Aperture Delay t

AD

1ns

Aperture Jitter t

AJ

2

ps

RMS

Overdrive Recovery Time For 1.5 x full-scale input 2 ns

Differential Gain ±1%

Differential Phase

Degrees

Output Noise IN+ = IN- = COM 0.2

LS B

RM S

INTERNAL REFERENCE

Reference Output Voltage

V

Reference Temperature
Coefficient

TC

REF

60

ppm/°C

Load Regulation

mV/mA

BUFFERED EXTERNAL REFERENCE (V

REFIN

= 2.048V)

REFIN Input Voltage

Positive Reference Output
Voltage

V

Negative Reference Output
Voltage

V

Common-Mode Level

V

Differential Reference Output
Voltage Range

V

REFIN

∆V

REF

= V

REFP

- V

REFN

, T

A

≥ +25°C

V

REFIN Resistance V

REFP

MΩ

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, V

REFIN

= 2.048V, REFOUT connected to

REFIN through a 10kΩ resistor, V

IN

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs, f

CLK

= 105MHz, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical

values are at T

A

= +25°C.)

SYMBOL

REFOUT

MIN TYP MAX

500

400

±0.25

2.048

±1%

1.25

2.048

2.012

0.988

V

/ 2

DD

0.98 1.024 1.07

>50

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

4 _______________________________________________________________________________________

PARAMETER

CONDITIONS

UNITS

Maximum REFP, COM Source
Current

V

REFN

5mA

Maximum REFP, COM Sink
Current

V

COM

µA

Maximum REFN Source Current

µA

Maximum REFN Sink Current I

SINK

-5 mA

UNBUFFERED EXTERNAL REFERENCE (V

REFIN

= AGND, reference voltage applied to REFP, REFN, and COM)

REFP, REFN Input Resistance

R

REFP

,

R

REFN

Measured between REFP and COM and
REFN and COM

4kΩ

REFP, REFN, COM Input
Capacitance

C

IN

15 pF

Differential Reference Input
Voltage Range

∆V

REF

∆V

REF

= V

REFP

- V

REFN

V

COM Input Voltage Range V

COM

V

DD

/ 2

V

REFP Input Voltage V

REFP

V

COM

+

V

REFN Input Voltage V

REFN

V

COM

­V

DIGITAL INPUTS (CLK, PD, OE)

CLK

0.8 x

Input High Threshold V

IH

PD, OE

0.8 x

V

CLK

0.2 x

Input Low Threshold V

IL

PD, OE

0.2 x

V

Input Hysteresis V

HYST

0.1 V

I

IH

VIH = VDD = OV

DD

±5µA

Input Leakage

I

IL

V

IL

= 0 ±5

Input Capacitance C

IN

5pF

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, V

REFIN

= 2.048V, REFOUT connected to

REFIN through a 10kΩ resistor, V

IN

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs, f

CLK

= 105MHz, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical

values are at T

A

= +25°C.)

SYMBOL

MIN TYP MAX

I

SOURCE

-250

250

1.024

∆V

±10%

±10%

REF

/ 2

∆V

/ 2

REF

V

DD

V

DD

V

DD

V

DD

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

_______________________________________________________________________________________ 5

Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale

input voltage range.

Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is

6dB better if referenced to the two-tone envelope.

Note 3: Digital outputs settle to V

IH,VIL

.

Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.

PARAMETER

CONDITIONS

UNITS

DIGITAL OUTPUTS (D9–D0)

Output Voltage Low V

OL

I

SINK

= 200µA 0.2 V

Output Voltage High V

OH

I

SOURCE

= 200µA

OV

DD

V

Three-State Leakage Current I

LEAK

OE = OV

DD

±10 µA

Three-State Output Capacitance

C

OUT

OE = OV

DD

5pF

POWER REQUIREMENTS

Analog Supply Voltage V

DD

2.7 3.3 3.6 V

Output Supply Voltage OV

DD

1.7 3.3 3.6 V

Operating, fIN = 20MHz at -0.5dB FS 58 74 mA

Analog Supply Current I

VDD

Shutdown, clock idle, PD = OE = OV

DD

415µA

Operating, CL = 15pF , fIN = 20MHz at

-0.5dB FS

10 mA

Output Supply Current I

OVDD

Shutdown, clock idle, PD = OE = OV

DD

120µA

Offset

mV/V

Power Supply Rejection PSRR

Gain

%/V

TIMING CHARACTERISTICS

CLK Rise-to-Output Data Valid t

DO

Figure 6 (Note 3) 5 8 ns

OE Fall-to-Output Enable

Figure 5 10 ns

OE Rise-to-Output Disable

Figure 5 15 ns

CLK Pulse Width High t

CH

Figure 6, clock period 9.52ns

ns

CLK Pulse Width Low t

CL

Figure 6, clock period 9.52ns

ns

Wake-Up Time t

WAKE

(Note 4) 1.5 µs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, V

REFIN

= 2.048V, REFOUT connected to

REFIN through a 10kΩ resistor, V

IN

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs, f

CLK

= 105MHz, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical

values are at T

A

= +25°C.)

SYMBOL

MIN TYP MAX

- 0.2

±0.1
±0.1

t

ENABLE

t

DISABLE

4.76

±0.47

4.76

±0.47

Typical Operating Characteristics

(VDD= 3.3V, OVDD= 2.0V, internal reference, differential input at -0.5dB FS, f

CLK

= 106.2345MHz, CL≈ 10pF, TA= +25°C, unless

otherwise noted.)

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

02010 30 40 50 60

FFT PLOT (fIN = 7.5MHz,

8192-POINT FFT, DIFFERENTIAL INPUT)

MAX1449 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

SNR = 58.6dB
SINAD = 58.4dB
THD = -72.7dBc
SFDR = 73.6dBc

2ND HARMONIC

3RD HARMONIC

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

02010 30 40 50 60

MAX1449 toc02

FFT PLOT (fIN = 19.99MHz,

8192-POINT FFT, DIFFERENTIAL INPUT)

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

SNR = 58.5dB
SINAD = 58.4dB
THD = -73.7dBc
SFDR = 75.9dBc

2ND HARMONIC

3RD HARMONIC

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

02010 30 40 50 60

MAX1449 toc03

FFT PLOT (fIN = 50.12MHz,

8192-POINT FFT, DIFFERENTIAL INPUT)

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

SNR = 57.9dB
SINAD = 56.7dB
THD = -71.3dBc
SFDR = 71.1dBc

2ND HARMONIC

3RD HARMONIC

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

02010 30 40 50 60

MAX1449 toc04

FFT PLOT (fIN = 7.5MHz,

8192-POINT FFT, SINGLE-ENDED INPUT)

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

SNR = 57.7dB
SINAD = 57.5dB
THD = -71.8dBc
SFDR = 74.4dBc

2ND HARMONIC

3RD HARMONIC

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

02010 30 40 50 60

MAX1449 toc05

FFT PLOT (fIN = 19.99MHz,

8192-POINT FFT, SINGLE-ENDED INPUT)

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

SNR = 57.7dB
SINAD = 57.2dB
THD = -67dBc
SFDR = 67.7dBc

2ND HARMONIC

3RD HARMONIC

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

02010 30 40 50 60

MAX1449 toc06

TWO-TONE INTERMODULATION

(8192-POINT IMD, DIFFERENTIAL INPUT)

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

f1 = 38MHz AT -6.5dB FS
f

2

= 42MHz AT -6.5dB FS

2ND-ORDER IMD

3RD-ORDER IMD

f

1

f

2

80

50

110100

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

56

MAX1449 toc07

ANALOG INPUT FREQUENCY (MHz)

SFDR (dBc)

62

68

74

DIFFERENTIAL

SINGLE ENDED

60

50

110100

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

52

MAX1449 toc08

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

54

56

58

DIFFERENTIAL

SINGLE ENDED

THD (dBc)

-50

-80
110100

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

-74

MAX1449 toc09

ANALOG INPUT FREQUENCY (MHz)

-68

-62

-56

DIFFERENTIAL

SINGLE ENDED

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

6 _______________________________________________________________________________________

SINAD (dB)

60

50

110100

SIGNAL-T0-NOISE + DISTORTION

vs. ANALOG INPUT FREQUENCY

52

MAX1449 toc10

ANALOG INPUT FREQUENCY (MHz)

54

56

58

DIFFERENTIAL

SINGLE-ENDED

-8
1 100010010

FULL-POWER INPUT BANDWIDTH vs.

ANALOG INPUT FREQUENCY, SINGLE ENDED

6

0

-6

4

2

MAX1449 toc11

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

-2

-4

-8
1100010010

SMALL-SIGNAL INPUT BANDWIDTH vs.

ANALOG INPUT FREQUENCY, SINGLE ENDED

6

0

-6

4

2

MAX1449 toc12

ANALOG INPUT FREQUENCY (MHz)

U(d)

-2

-4

VIN = 100mVp-p

50

60

55

70

65

75

80

-12 -6-9 -3 0

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT POWER (f

IN

= 19MHz)

MAX1449 toc13

ANALOG INPUT POWER (dB FS)

SFDR (dBc)

40

45

55

50

60

65

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT POWER (f

IN

= 19MHz)

MAX1449 toc14

ANALOG INPUT POWER (dB FS)

SNR (dB)

-12 -6-9 -3 0

-80

-70

-75

-60

-65

-55

-12 -6-9 -3 0

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT POWER (f

IN

= 19MHz)

MAX1449 toc15

ANALOG INPUT POWER (dB FS)

THD (dBc)

-50

40

45

55

50

60

65

SIGNAL-TO-NOISE + DISTORTION

vs. ANALOG INPUT POWER (f

IN

= 19MHz)

MAX1449 toc16

ANALOG INPUT POWER (dB FS)

SINAD (dB)

-12 -6-9 -3 0

64

68

76

72

80

84

-40 10-15 35 60 85

SPURIOUS-FREE DYNAMIC RANGE

vs. TEMPERATURE

MAX1449 toc17

TEMPERATURE (°C)

SFDR (dBc)

fIN = 26.1696MHz

50

54

62

58

66

70

-40 10-15 35 60 85

SIGNAL-TO-NOISE vs. TEMPERATURE

MAX1449 toc18

TEMPERATURE (°C)

SNR (dB)

fIN = 26.1696MHz

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, internal reference, differential input at -0.5dB FS, f

CLK

= 106.2345MHz, CL≈ 10pF, TA= +25°C, unless

otherwise noted.)

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

_______________________________________________________________________________________ 7

-80

-76

-68

-72

-64

-60

-40 10-15 35 60 85

TOTAL HARMONIC DISTORTION

vs. TEMPERATURE

MAX1449 toc19

TEMPERATURE (°C)

THD (dBc)

fIN = 26.1696MHz

50

54

62

58

66

70

-40 10-15 35 60 85

SIGNAL-TO-NOISE + DISTORTION

vs. TEMPERATURE

MAX1449 toc20

TEMPERATURE (°C)

SINAD (dB)

fIN = 26.1696MHz

-0.4

-0.2

-0.3

0.1

0

-0.1

0.4

0.3

0.2

0.5

0 400200 600 800 1000 1200

INTEGRAL NONLINEARITY vs.

DIGITAL OUTPUT CODE (BEST STRAIGHT LINE)

MAX1449 toc21

DIGITAL OUTPUT CODE

INL (LSB)

-0.4

-0.2

-0.3

0.1

0

-0.1

0.4

0.3

0.2

0.5

0 400200 600 800 1000 1200

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1449 toc22

DIGITAL OUTPUT CODE

DNL (LSB)

0

0.02

0.06

0.04

0.08

0.10

-40 10-15 35 60 85

GAIN ERROR vs. TEMPERATURE,

EXTERNAL REFERENCE, V

REFIN

= +2.048V

MAX1449 toc23

TEMPERATURE (°C)

GAIN ERROR (LSB)

-2

0

-1

2

1

3

4

-40 10-15 35 6085

OFFSET ERROR vs. TEMPERATURE,

EXTERNAL REFERENCE, V

REFIN

= +2.048V

MAX1449 toc24

TEMPERATURE (°C)

OFFSET ERROR (LSB)

40

50

45

60

55

65

70

-40 10-15 35 6085

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

MAX1449 toc26

TEMPERATURE (°C)

I

VDD

(mA)

0

3

9

6

12

15

-40 10-15 35 60 85

DIGITAL SUPPLY CURRENT

vs. TEMPERATURE

MAX1449 toc27

TEMPERATURE (°C)

I

OVDD

(mA)

51

55

53

59

57

61

63

2.70 3.00 3.152.85 3.30 3.45 3.60

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1449 toc25

VDD (V)

I

VDD

(mA)

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, internal reference, differential input at -0.5dB FS, f

CLK

= 106.2345MHz, CL≈ 10pF, TA= +25°C, unless

otherwise noted.)

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

8 _______________________________________________________________________________________

12

10

8

6

4

-40 10-15 35 6085

DIGITAL SUPPLY CURRENT

vs. TEMPERATURE

MAX1449 toc28

TEMPERATURE (°C)

I

OVDD

(mA)

2.00

2.20

2.60

2.40

2.80

3.00

2.70 3.002.85 3.15 3.30 3.45 3.60

ANALOG POWER-DOWN CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1449 toc29

VDD (V)

I

VDD

(µA)

12

9

6

3

0

2.0 2.62.3 3.0 3.3 3.6

DIGITAL POWER-DOWN CURRENT

vs. DIGITAL SUPPLY VOLTAGE

MAX1449 toc30

OV

DD

(V)

I

OVDD

(µA)

50

60

55

70

65

75

80

100 108104 112 116 120

SNR/SINAD, THD/SFDR

vs. CLOCK FREQUENCY

MAX1449 toc31

CLOCK FREQUENCY (MHz)

SNR/SINAD, THD/SFDR (dB, dBc)

fIN = 50.123MHz

SFDR

SNR

SINAD

THD

2.100

2.075

2.050

2.025

2.000

2.70 3.152.85 3.00 3.30 3.45 3.60

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

MAX1449 toc32

VDD (V)

V

REFOUT

(V)

2.00

2.02

2.06

2.04

2.08

2.10

-40 10-15 35 60 85

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1449 toc33

TEMPERATURE (°C)

V

REFOUT

(V)

0

20,000

10,000

40,000

30,000

60,000

50,000

70,000

N-2 NN-1 N+1 N+2

OUTPUT NOISE HISTOGRAM (DC INPUT)

MAX1449 toc34

DIGITAL OUTPUT CODE

COUNTS

0

607

64676

252

0

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, internal reference, differential input at -0.5dB FS, f

CLK

= 106.2345MHz, CL≈ 10pF, TA= +25°C, unless

otherwise noted.)

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

_______________________________________________________________________________________ 9

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

10 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 REFN

Lower Reference. Conversion range is ±(V

REFP

- V

REFN

).

Bypass to GND with a > 0.1µF capacitor.

2 COM Common-Mode Voltage Output. Bypass to GND with a > 0.1µF capacitor.

3, 9, 10 V

DD

Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF.

4, 5, 8, 11,

14, 30

GND Analog Ground

6 IN+ Positive Analog Input. For single-ended operation connect signal source to IN+.

7 IN- Negative Analog Input. For single-ended operation connect IN- to COM.

12 CLK Conversion Clock Input

13 PD

Power Down Input.
High: Power-down mode
Low: Normal operation

15 OE

Output Enable Input.
High: Digital outputs disabled
Low: Digital outputs enabled

16–20 D9–D5 Three-State Digital Outputs D9–D5. D9 is the MSB.

21 OV

DD

Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with

0.1µF.

22 T.P. Test Point. Do not connect.

23 OGND Output Driver Ground

24–28 D4–D0 Three-State Digital Outputs D4–D0. D0 is the LSB.

29

Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor­divider.

31 REFIN Reference Input. V

REFIN

= 2 x (V

REFP

- V

REFN

). Bypass to GND with a > 0.1µF capacitor.

32 REFP Upper Reference. Conversion range is ±(V

REFP

- V

REFN

). Bypass to GND with a > 0.1µF capacitor.

REFOUT

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

______________________________________________________________________________________ 11

Detailed Description

The MAX1449 uses a 10-stage, fully differential,
pipelined architecture (Figure 1), that allows for high­speed conversion while minimizing power consump­tion. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.

A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digital­to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been
processed by all 10 stages. Each stage provides a 1­bit resolution. Digital error-correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes.

Input Track-and-Hold (T/H) Circuit

Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors C2a
and C2b through switches S4a and S4b. Switches S2a
and S2b set the common mode for the amplifier input,

and open simultaneously with S1, sampling the input
waveform. Switches S4a and S4b are then opened
before switches S3a and S3b connect capacitors C1a
and C1b to the output of the amplifier and switch S4c is
closed. The resulting differential voltage is held on
capacitors C2a and C2b. The amplifier is used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. This value is then pre­sented to the first stage quantizer and isolates the
pipeline from the fast-changing input. The wide input
bandwidth T/H amplifier allows the MAX1449 to track
and sample/hold analog inputs of high frequencies
beyond Nyquist. The analog inputs IN+ and IN- can be
driven either differentially or single-ended. It is recom­mended to match the impedance of IN+ and IN- and
set the common-mode voltage to mid-supply (VDD/2)
for optimum performance.

Analog Input and Reference Configuration

The full-scale range of the MAX1449 is determined by the
internally generated voltage difference between REFP
(VDD/2 + V

REFIN

/4) and REFN (VDD/2 - V

REFIN

/4). The
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered low-impedance outputs.

T/H

V

OUT

x2

Σ

FLASH

ADC

DAC

1.5 BITS

MDAC

10

V

IN

V

IN

STAGE 1 STAGE 2

D9–D0

V

IN

= INPUT VOLTAGE BETWEEN

IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED)

DIGITAL CORRECTION LOGIC

STAGE 10

Figure 1. Pipelined Architecture—Stage Blocks

S3b

S3a

COM

S5bS2b

S5a

IN+

IN-

S1

OUT

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

TRACK TRACK

CLK

INTERNAL
NONOVERLAPPING
CLOCK SIGNALS

HOLD HOLD

S2a

Figure 2. Internal T/H Circuit

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

12 ______________________________________________________________________________________

The MAX1449 provides three modes of reference oper­ation:

•Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, the internal reference out­put REFOUT can be tied to the REFIN pin through a
resistor (e.g., 10kΩ) or resistor-divider, if an application
requires a reduced full-scale range. For stability pur­poses it is recommended to bypass REFIN with a
>10nF capacitor to GND.

In buffered external reference mode, the reference volt­age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a >10kΩ resistor.

In unbuffered external reference mode, REFIN is con­nected to GND thereby deactivating the on-chip buffers
of REFP, COM, and REFN. With their buffers shut down,
these pins become high impedance and can be driven
by external reference sources.

Clock Input (CLK)

The MAX1449’s CLK input accepts CMOS-compatible
clock signals. Since the inter-stage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR per­formance of the ADC as follows:

where f

IN

represents the analog input frequency and

tAJis the time of the aperture jitter.

Clock jitter is especially critical for undersampling
applications. The clock input should always be consid­ered as an analog input and routed away from any ana­log input or other digital signal lines.

The MAX1449 clock input operates with a voltage
threshold set to V

DD

/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the Electrical
Characteristics. (See Figures 3 (3a, 3b) and 4 (4a, 4b)
for the relationship between spurious-free dynamic
range (SFDR), signal-to-noise ratio (SNR), total harmon­ic distortion (THD), or signal-to-noise plus distortion
(SINAD) vs. duty cycle.)

Output Enable (

OOEE

), Power Down (PD),

and Output Data (D0–D9)

All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS logic-compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD high, the digital outputs
enter a high-impedance state. If OE is held low with PD
high, the outputs are latched at the last value prior to
the power down.

The capacitive load on the digital outputs D0 through D9
should be kept as low as possible (<15pF), to avoid
large digital currents that could feed back into the ana­log portion of the MAX1449, thereby degrading its
dynamic performance. The use of buffers on the digital
outputs of the ADC can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1449, small series
resistors (e.g., 100Ω) may be added to the digital output
paths, close to the ADC. Figure 5 displays the timing
relationship between output enable and data output valid
as well as power-down/wake-up and data output valid.

SNR

ft

IN AJ

=×

×× ×











20

1

2

log

π

Table 1. MAX1449 Output Code for Differential Inputs

DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY

V

REF

× 511/512 +Full Scale -1LSB 11 1111 1111

V

REF

× 510/512 +Full Scale -2LSB 11 1111 1110

V

REF

× 1/512 +1LSB 10 0000 0001

0 Bipolar Zero 10 0000 0000

- V

REF

× 1/512 -1LSB 01 1111 1111

- V

REF

× 511/512 Negative Full Scale + 1LSB 00 0000 0001

- V

REF

× 512/512 Negative Full Scale 00 0000 0000

*V

REF

= V

REFP

= V

REFN

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

______________________________________________________________________________________ 13

50

58

74

66

82

90

35 4942 56 63 70

CLOCK DUTY CYCLE (%)

SFDR (dBc)

fIN = 25.123MHz AT -0.5dB FS

Figure 3a. Spurious Free Dynamic Range vs. Clock Duty Cycle
(Differential Input)

54

57

56

55

60

58

59

61

62

35 4942 56 63 70

CLOCK DUTY CYCLE (%)

SNR (dB)

fIN = 25.123MHz AT -0.5dB FS

Figure 3b. Signal-to-Noise Ratio vs. Clock Duty Cycle
(Differential Input)

-85

-75

-80

-65

-70

-55

-60

-50

35 4942 56 63 70

CLOCK DUTY CYCLE (%)

THD (dBc)

fIN = 25.123MHz AT -0.5dB FS

Figure 4a. Total Harmonic Distortion vs. Clock Duty Cycle
(Differential Input)

52

56

54

60

58

62

64

35 4942 56 63 70

CLOCK DUTY CYCLE (%)

SINAD (dB)

fIN = 25.123MHz AT -0.5dB FS

Figure 4b. Signal-to-Noise Plus Distortion vs. Clock Duty Cycle
(Differential Input)

OUTPUT

DATA D9–D0

OE

t

DISABLE

t

ENABLE

HIGH-ZHIGH-Z

VALID DATA

Figure 5. Output Enable Timing

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

14 ______________________________________________________________________________________

System Timing Requirements

Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1449
samples at the falling edge of the input clock. Output
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Figure 6 also determines the relationship between the
input clock parameters and the valid output data.

Applications Information

Figure 7 depicts a typical application circuit containing a
single-ended to differential converter. The internal refer­ence provides a VDD/2 output voltage for level shifting
purposes. The input is buffered and then split to a volt­age follower and inverter. A low-pass filter, to suppress
some of the wideband noise associated with high-speed
op amps, follows the op amps. The user may select the
R

ISO

and CINvalues to optimize the filter performance, to
suit a particular application. For the application in Figure
7, a R

ISO

of 50Ω is placed before the capacitive load to

prevent ringing and oscillation. The 22pF CINcapacitor
acts as a small bypassing capacitor.

Using Transformer Coupling

An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1449 for
optimum performance. Connecting the center tap of the
transformer to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step­up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over­all distortion.

In general, the MAX1449 provides better SFDR and
THD with fully differential input signals than single­ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (IN+, IN-) are balanced, and each
of the inputs only requires half the signal swing com­pared to single-ended mode.

Single-Ended AC-Coupled Input Signal

Figure 9 shows an AC-coupled, single-ended applica­tion. The MAX4108 op amp provides high speed, high
bandwidth, low-noise, and low-distortion to maintain the
integrity of the input signal.

N - 6

N

N - 5

N + 1

N - 4

N + 2

N - 3

N + 3

N - 2

N + 4

N - 1

N + 5

N

N + 6

N + 1

5.5 CLOCK-CYCLE LATENCY

ANALOG INPUT

CLOCK INPUT

DATA OUTPUT

t

D0

t

CH

t

CL

Figure 6. System and Output Timing Diagram

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

______________________________________________________________________________________ 15

INPUT

300Ω

-5V

5V

0.1µF

0.1µF

0.1µF

C

IN

22pF

C

IN

22pF

R

ISO

50Ω

R

ISO

50Ω

-5V

600Ω

300Ω

300Ω

IN+

IN-

LOWPASS FILTER

COM

600Ω

5V

-5V

0.1µF

600Ω

300Ω

600Ω

300Ω

0.1µF

0.1µF

0.1µF

5V

0.1µF

300Ω

MAX4108

MAX1449

MAX4108

MAX4108

LOWPASS FILTER

Figure 7. Typical Application Circuit Using the Internal Reference

MAX1449

T1

N.C.

V

IN

4

3

2

5

61

22pF

22pF

0.1µF

0.1µF

2.2µF

25Ω

25Ω

MINI-CIRCUITS

ADT1-1WT

IN-

IN+

COM

Figure 8. Using a Transformer for AC-Coupling

MAX1449

0.1µF

1kΩ

1kΩ

100Ω

100Ω

C

IN

COM

C

IN

IN+

IN-

0.1µF

R

ISO

R

ISO

REFP

REFN

R

ISO

= 50Ω

C

IN

= 22pF

V

IN

MAX4108

Figure 9. Single-Ended AC-Coupled Input

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

16 ______________________________________________________________________________________

Buffered External Reference Drives

Multiple ADCs

Multiple-converter systems based on the MAX1449 are
well suited for use with a common reference voltage.
The REFIN pin of those converters can be connected
directly to an external reference source. A precision
bandgap reference like the MAX6062 generates an
external DC level of 2.048V (Figure 10), and exhibits a
noise voltage density of 150nV/√Hz. Its output passes
through a 1-pole lowpass filter (with 10Hz cutoff fre-

quency) to the MAX4250, which buffers the reference
before its output is applied to a second 10Hz lowpass
filter. The MAX4250 provides a low offset voltage (for
high-gain accuracy) and a low noise level. The passive
10Hz filter following the buffer attenuates noise pro­duced in the voltage reference and buffer stages. This
filtered noise density, which decreases for higher fre­quencies, meets the noise levels specified for precision
ADC operation.

REFOUT

29

N.C.

REFIN

31

REFP

32

REFN

1

COM

2

0.1µF

0.1µF

0.1µF

0.1µF

2.048V

100µF2

5

3

2

3

1

4

1

MAX1449

N = 1

MAX4250

REFOUT

29

N.C.

REFIN

31

REFP

32

REFN

1

COM

2

0.1µF

0.1µF

0.1µF

0.1µF

MAX1449

N = 1000

0.1µF

162Ω

16.2kΩ

3.3V

1µF

10Hz LOWPASS

FILTER 10Hz LOWPASS

FILTER

NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.

2.2µF
10V

0.1µF

0.1µF

3.3V

MAX6062

Figure 10. Buffered External Reference Drives Up to 1000 ADCs

Unbuffered External Reference Drives

Multiple ADCs

Connecting each REFIN to analog ground disables the
internal reference of each device, allowing the internal
reference ladders to be driven directly by a set of external
reference sources. Followed by a 10Hz lowpass filter and
precision voltage-divider (Figure 11), the MAX6066 gen­erates a DC level of 2.500V. The buffered outputs of this
divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy
that depends on the tolerance of the divider resistors. The
three voltages are buffered by the MAX4252, which pro­vides low noise and low DC offset. The individual voltage
followers are connected to 10Hz lowpass filters, which fil-

ter both the reference voltage and amplifier noise to a
level of 3nV/√Hz. The 2.0V and 1.0V reference voltages
set the differential full-scale range of the associated
ADCs at 2V

P-P

. The 2.0V and 1.0V buffers drive the
ADC’s internal ladder resistances between them. Note
that the common power supply for all active components
removes any concern regarding power-supply sequenc­ing when powering up or down. With the outputs of the
MAX4252 matching better than 0.1%, the buffers and
subsequent lowpass filters can be replicated to support
as many as 32 ADCs. For applications that require more
than 32 matched ADCs, a voltage reference and divider
string common to all converters is highly recommended.

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

______________________________________________________________________________________ 17

REFOUT

29

N.C.

REFIN

31

REFP

32

REFN

1

COM

2

0.1µF

0.1µF

0.1µF

330µF

6V

330µF

6V

330µF

6V

10µF
6V

11

4

3

2

3

1

2

1

MAX1449

N = 1

MAX6066

1/4 MAX4252

REFOUT

29

N.C.

REFIN

31

REFP

32

REFN

1

COM

2

0.1µF

0.1µF

0.1µF

MAX1449

N = 32

47Ω

2.0V AT 8mA

1.47kΩ

21.5kΩ

3.3V

1µF

21.5kΩ

21.5kΩ

21.5kΩ

21.5kΩ

NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.

2.2µF
10V

0.1µF

0.1µF

3.3V

2.0V

10µF
6V

11

4

5

6

7

1/4 MAX4252

47Ω

1.5V AT 0mA

1.47kΩ

3.3V

10µF
6V

11

4

10

9

8

1/4 MAX4252

47Ω

1.0V AT -8mA

1.47kΩ

3.3V

3.3V

MAX4254 POWER-SUPPLY BYPASSING.
PLACE CAPACITOR AS CLOSE AS
POSSIBLE TO THE OP AMP.

0.1µF

1.5V

1.0V

Figure 11. Unbuffered External Reference Drives Up to 32 ADCs

MAX1449

Grounding, Bypassing,

and Board Layout

The MAX1449 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multi-layer
boards with separated ground and power planes pro­duce the highest level of signal integrity. Consider
the use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC's
package. The two ground planes should be joined at a
single point, such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi­mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
(1Ω to 5Ω), a ferrite bead or a direct short. Alternatively,
all ground pins could share the same ground plane, if
the ground plane is sufficiently isolated from any noisy
digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin­earity parameters for the MAX1449 are measured using
the best straight-line fit method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.

Dynamic Parameter Definitions

Aperture Jitter

Figure 12 depicts the aperture jitter (t

AJ

), which is the

sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (t

AD

) is the time defined between the
falling-edge of the sampling clock and the instant when
an actual sample is taken (Figure 12).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital sam­ples, the theoretical maximum SNR is the ratio of the full­scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana­log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):

SNR

(MAX)

= 6.02 x N + 1.76

In reality, there are other noise sources besides quanti­zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har­monics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig­nal to all spectral components minus the fundamental
and the DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:

where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.

THD

VVVV

V

=×

+++















20

2

2

3

2

4

2

5

2

1

log

()

ENOB

SINAD

.

.

=

−

()

176

602

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

18 ______________________________________________________________________________________

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

______________________________________________________________________________________ 19

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next largest spurious
component, excluding DC offset.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter­modulation products. The individual input tone levels
are at -6.5dB full scale and their envelope is at -0.5dB
full scale.

HOLD

ANALOG

INPUT

SAMPLED

DATA (T/H)

T/H

t

AD

t

AJ

TRACK TRACK

CLK

Figure 12. T/H Aperture Timing

Pin Configuration

Chip Information

TRANSISTOR COUNT: 5684

PROCESS: CMOS

MAX1449

TQFP

TOP VIEW

32 28

293031

25

26

27

REFIN

GND

REFOUT

D0

REFP

D1

D2

D3

10

13

15

14

1611 12

9

V

DD

GND

V

DD

PD

CLK

OE

GND

D9

17

18

19

20

21

22

23

OGND

24 D4

T.P.

OV

DD

D5

D6

D7

D8

2

3

4

5

6

7

8GND

IN-

IN+

GND

GND

V

DD

COM

1REFN

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference

20 ______________________________________________________________________________________

32L TQFP, 5x5x01.0.EPS

B

1

2

21-0110

PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

21 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

B

2

2

21-0110

PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)