MAXIM MAX1436B Technical data

General Description

The MAX1436B octal, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. This ADC is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. The MAX1436B operates from a 1.8V single supply and consumes only 743mW (93mW per channel) while delivering a 69.9dB (typ) signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1436B features a lowpower standby mode for idle periods.

An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise.

A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip PLL generates the high-speed serial low-voltage differential signal (LVDS) clock.

The MAX1436B has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two’s complement or binary format.

The MAX1436B offers a maximum sample rate of 40Msps. See the

Pin-Compatible Versions

table below for higher-speed versions. This device is available in a small, 14mm x 14mm x 1mm, 100-pin TQFP package with exposed pad and is specified for the extended industrial (-40°C to +85°C) temperature range.

Applications

Ultrasound and Medical Imaging

Instrumentation

Multichannel Communications

Features

o Excellent Dynamic Performance

69.9dB SNR at 5.3MHz 96dBc SFDR at 5.3MHz 95dB Channel Isolation

o Ultra-Low Power

93mW per Channel (Normal Operation) Fast 200μs Wake-Up Time from Standby

o Serial LVDS Outputs

o Pin-Selectable LVDS/SLVS (Scalable Low-Voltage

Signal) Mode

o LVDS Outputs Support Up to 30 Inches FR-4

Backplane Connections

o Test Mode for Digital Signal Integrity

o Fully Differential Analog Inputs

o Wide Differential Input Voltage Range (1.4V

P-P

)

o On-Chip 1.24V Precision Bandgap Reference

o Clock Duty-Cycle Equalizer

o Compact, 100-Pin TQFP Package with Exposed

Pad

o Evaluation Kit Available (Order MAX1436BEVKIT)

MAX1436B

Octal, 12-Bit, 40Msps, 1.8V ADC

with Serial LVDS Outputs

________________________________________________________________

Maxim Integrated Products

1

Ordering Information

19-0523; Rev 1; 2/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at the end of data sheet.

EVALUATION KIT

AVAILABLE

Pin-Compatible Versions

+

Denotes a lead(Pb)-free/RoHS-compliant package.

D = Dry pack.

*

EP = Exposed pad.

PA R T T EM P RA N G EPIN - PA C K A G E

M AX 1436BE C Q+ D - 40°C to + 85° C

100 TQFP - E P * ( 14m m x 14m m x 1m m )

PART

MAX1434 50 10 Power-down

MAX1436 40 12 Power-down

MAX1436B 40 12 Standby

MAX1437 50 12 Power-down

MAX1438 65 12 Power-down

SAMPLING

RATE (Msps)

RESOLUTION

(Bits)

POWER-

SAVE MODE

MAX1436B

Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(Voltages referenced to GND)

AVDD.....................................................................-0.3V to +2.0V

CVDD.....................................................................-0.3V to +3.6V

OVDD ....................................................................-0.3V to +2.0V

IN_P, IN_N ..............................................-0.3V to (V

AV

DD

+ 0.3V)

CLK ........................................................-0.3V to (V

CV

DD

+ 0.3V)

OUT_P, OUT_N, FRAME_, CLKOUT_ ......-0.3V to (V

OV

DD

+ 0.3V)

DT, SLVS/LVDS, LVDSTEST, PLL_, T/B, STBY,

REFIO, REFADJ, CMOUT...................-0.3V to (V

AV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

TQFP (derate 47.6mW/°C above +70°C)................3809.5mW

Operating Temperature Range ...........................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

ELECTRICAL CHARACTERISTICS

(V

AV

DD

= 1.8V, V

OV

DD

= 1.8V, V

CV

DD

= 3.3V, V

GND

= 0V, external V

REFIO

= 1.24V, C

REFIO

= 0.1µF, C

REFP

= 10µF, C

REFN

= 10µF, f

CLK

= 40MHz (50% duty cycle), VDT= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 2, 3)

PACKAGE THERMAL CHARACTERISTICS (Note 1)

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial

.

TQFP

Junction-to-Ambient Thermal Resistance (θ

JA

) ...........21°C/W

Junction-to-Case Thermal Resistance (θ

JC

) ..................2°C/W

DC ACCURACY (Note 4)

Resolution N 12 Bits

Integral Nonlinearity INL ±0.4 ±3 LSB

Differential Nonlinearity DNL No missing codes over temperature ±0.25 ±1 LSB

Offset Error ±0.5 %FS

Gain Error ±2.4 %FS

ANALOG INPUTS (IN_P, IN_N)

Input Differential Range V

Common-Mode Voltage Range V

Common-Mode Voltage Range Tolerance

Differential Input Impedance R

Differential Input Capacitance C

CONVERSION RATE

Maximum Conversion Rate f

Minimum Conversion Rate f

Data Latency 6.5 Cycles

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ID

CMO

IN

SMAX

SMIN

Differential input 1.4 V

(Note 5) ±50 mV

Switched capacitor load 2 kΩ

40 MHz

0.76 V

12.5 pF

4.0 MHz

P-P

MAX1436B

Octal, 12-Bit, 40Msps, 1.8V ADC

with Serial LVDS Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(V

AV

DD

= 1.8V, V

OV

DD

= 1.8V, V

CV

DD

= 3.3V, V

GND

= 0V, external V

REFIO

= 1.24V, C

REFIO

= 0.1µF, C

REFP

= 10µF, C

REFN

= 10µF, f

CLK

= 40MHz (50% duty cycle), VDT= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) (Note 4)

Signal-to-Noise Ratio SNR

Signal-to-Noise and Distortion (First 4 Harmonics)

Effective Number of Bits ENOB

Spurious-Free Dynamic Range SFDR

Total Harmonic Distortion THD

Intermodulation Distortion IMD

Third-Order Intermodulation IM3

Aperture Jitter t

Aperture Delay t

Small-Signal Bandwidth SSBW Input at -20dBFS 100 MHz

Full-Power Bandwidth LSBW Input at -0.5dBFS 100 MHz

Output Noise IN_P = IN_N 0.44 LSB

Over-Range Recovery Time t

INTERNAL REFERENCE

REFADJ Internal Reference-Mode Enable Voltage

REFADJ Low-Leakage Current 1.5 mA

REFIO Output Voltage V

Reference Temperature Coefficient

EXTERNAL REFERENCE

REFADJ External ReferenceMode Enable Voltage

REFADJ High-Leakage Current 200 µA

REFIO Input Voltage 1.24 V

REFIO Input Voltage Tolerance ±5 %

REFIO Input Current I

SINAD

AJ

AD

OR

REFIO

TC

REFIO

fIN = 5.3MHz at -0.5dBFS 69.9

= 19.3MHz at -0.5dBFS 66.5 69.6

f

IN

fIN = 5.3MHz at -0.5dBFS 69.9

f

= 19.3MHz at -0.5dBFS 66.5 69.6

IN

fIN = 5.3MHz at -0.5dBFS 11.3

f

= 19.3MHz at -0.5dBFS 11.3

IN

fIN = 5.3MHz at -0.5dBFS 96

f

= 19.3MHz at -0.5dBFS 79 90

IN

fIN = 5.3MHz at -0.5dBFS -96

f

= 19.3MHz at -0.5dBFS -92 -79

IN

f

= 5.3MHz at -6.5dBFS

1

= 6.3MHz at -6.5dBFS

f

2

f

= 5.3MHz at -6.5dBFS

1

= 6.3MHz at -6.5dBFS

f

2

Figure 11 < 0.4 ps

Figure 11 1 ns

RS = 25Ω, CS = 50pF 1

(Note 6) 0.1 V

(Note 6)

1.18 1.24 1.30 V

V

AVDD

0.1

89.8 dBc

96.6 dBc

120 ppm/°C

-

< 1 µA

dB

dBc

RMS

Clock

cycle

V

MAX1436B

Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

AV

DD

= 1.8V, V

OV

DD

= 1.8V, V

CV

DD

= 3.3V, V

GND

= 0V, external V

REFIO

= 1.24V, C

REFIO

= 0.1µF, C

REFP

= 10µF, C

REFN

= 10µF, f

CLK

= 40MHz (50% duty cycle), VDT= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

COMMON-MODE OUTPUT (CMOUT)

CMOUT Output Voltage V

CLOCK INPUT (CLK)

Input High Voltage V

CMOUT

CLKH

0.8 x

V

AVDD

0.76 V

Input Low Voltage V

Clock Duty Cycle 50 %

Clock Duty-Cycle Tolerance ±30 %

Input Leakage Current DI

Input Capacitance DC

DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, STBY, T/B)

Input Logic-High Voltage V

Input Logic-Low Voltage V

Input Leakage Current DI

Input Capacitance DC

LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0

Differential Output Voltage V

Output Common-Mode Voltage V

Rise Time (20% to 80%) t

Fall Time (80% to 20%) t

SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1

Differential Output Voltage V

Output Common-Mode Voltage V

Rise Time (20% to 80%) t

Fall Time (80% to 20%) t

STANDBY MODE (STBY)

STBY Fall to Output Enable t

STBY Rise to Output Disable t

CLKL

Input at GND 5

IN

Input at AVDD 80

IN

IH

IL

Input at GND 5

IN

Input at AVDD 80

IN

OHDIFFRTERM

OCMRTERM

R

RL

FL

OHDIFFRTERM

OCMRTERM

RS

FS

ENABLE

DISABLE

TERM

R

TERM

R

TERM

R

TERM

V

5pF

0.8 x

V

AVDD

V

5pF

= 100Ω 250 450 mV = 100Ω 1.125 1.375 V = 100Ω, C = 100Ω, C

= 5pF 350 ps

LOAD

= 5pF 350 ps

LOAD

= 100Ω 205 mV = 100Ω 220 mV = 100Ω, C = 100Ω, C

= 5pF 320 ps

LOAD

= 5pF 320 ps

LOAD

200 µs

60 ns

0.2 x

AVDD

0.2 x

AVDD

V

µA

V

µA

MAX1436B

Octal, 12-Bit, 40Msps, 1.8V ADC

with Serial LVDS Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(V

AV

DD

= 1.8V, V

OV

DD

= 1.8V, V

CV

DD

= 3.3V, V

GND

= 0V, external V

REFIO

= 1.24V, C

REFIO

= 0.1µF, C

REFP

= 10µF, C

REFN

= 10µF, f

CLK

= 40MHz (50% duty cycle), VDT= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 2, 3)

Note 2: Specifications at TA≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design

and characterization and not subject to production testing.

Note 3: All capacitances are between the indicated pin and GND, unless otherwise noted. Note 4: See definition in the

Parameter Definitions

section at the end of this data sheet.

Note 5: See the

Common-Mode Output (CMOUT)

section.

Note 6: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the inter-

nal bandgap reference and enable external reference mode.

Note 7: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level. Note 8: Guaranteed by design and characterization. Not subject to production testing.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER REQUIREMENTS

AVDD Supply Voltage Range V

OVDD Supply Voltage Range V

CVDD Supply Voltage Range V

AVDD Supply Current I

OVDD Supply Current I

CVDD Supply Current I

Power Dissipation P

TIMING CHARACTERISTICS (Note 8)

Data Valid to CLKOUT Rise/Fall t

CLKOUT Output-Width High t

CLKOUT Output-Width Low t

FRAME Rise to CLKOUT Rise t

Sample CLK Rise to FRAME Rise t

Crosstalk (Note 4) -95 dB

Gain Matching C

Phase Matching C

AVDD

OVDD

CVDD

AVDD

OVDD

CVDD

DISSfIN

OD

CH

CL

CF

SF

GMfIN

PMfIN

1.7 1.8 1.9 V

1.7 1.8 3.6 V

STBY = 0 337 380

fIN = 19.3MHz at -0.5dBFS

STBY = 0, D T = 1 337

STBY = 1, standb y, no cl ock i np ut

37 mA

STBY = 0 76 100

fIN = 19.3MHz at -0.5dBFS

CVDD is used only to bias ESD-protection diodes on CLK input, Figure 2

STBY = 0, D T = 199

STBY = 1, standb y, no cl ock i np ut

16 µA

0mA

= 19.3MHz at -0.5dBFS 743 864 mW

Figure 5 (Notes 7, 8)

( t

Figure 5 t

Figure 4 (Note 8)

( t

S AM P LE

- 0.15

S AM P LE

- 0.15

S AM P LE

+ 1.1

/24)

S AM P LE

/24)

/2)

( t

S AM P LE

/24)

+ 0.15

/12 ns

( t

S AM P LE

/24)

+ 0.15

( t

S AM P LE

/2)

+ 2.6

= 5.3MHz (Note 4) ±0.1 dB

= 5.3MHz (Note 4) ±0.25 D eg r ees

mA

ns

MAX1436B

Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

6 _______________________________________________________________________________________

)

Typical Operating Characteristics

(V

AV

DD

= 1.8V, V

OV

DD

= 1.8V, V

CV

DD

= 3.3V, V

GND

= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f

CLK

=

40MHz (50% duty cycle), V

DT

= 0V, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

FFT PLOT

(16,384-POINT DATA RECORD)

MAX1436B toc01

FREQUENCY (MHz)

AMPLITUDE (dBFS)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-90

-110 51015020

f

CLK

= 39.8871375MHz

f

IN

= 5.304814MHz

A

IN

= -0.5dBFS SNR = 69.917dB SINAD = 69.907dB THD = -96.178dBc SFDR = 95.807dBc

HD2

HD3

FFT PLOT

(16,384-POINT DATA RECORD)

MAX1436B toc02

FREQUENCY (MHz)

AMPLITUDE (dBFS)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-90

-110

f

CLK

= 39.8871374MHz

f

IN

= 19.2984215MHz

A

IN

= -0.5dBFS SNR = 69.641dB SINAD = 69.618dB THD = -92.410dBc SFDR = 90.384dBc

51015020

HD2

HD3

CROSSTALK

(16,384-POINT DATA RECORD)

MAX1436B toc03

FREQUENCY (MHz)

AMPLITUDE (dBFS)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-110

-90

51015020

MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 2 f

IN(IN1)

= 5.304814MHz

f

IN(IN2)

= 19.2984215MHz

CROSSTALK = 97.2dB

f

IN(IN2)

TWO-TONE INTERMODULATION DISTORTION

(16,384-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

f

= 5.298993MHz

IN(IN1)

= 6.298573MHz

f

IN(IN2)

= -6.5dBFS

A

IN1

= -6.5dBFS

A

IN2

IMD = 89.8dBc IM3 = 96.6dBc

51015020

FREQUENCY (MHz

MAX1436B toc04

GAIN (dB)

vs. ANALOG INPUT FREQUENCY

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10 1 100 1000

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

72

71

70

69

68

67

SINAD (dB)

66

65

64

63

62

0120

ANALOG INPUT FREQUENCY (MHz)

1008020 40 60

MAX1436B toc07

-55

-60

-65

-70

-75

THD (dBc)

-80

-85

-90

-95

-100 0120

BANDWIDTH

SMALL-SIGNAL BANDWIDTH

FULL-POWER BANDWIDTH

-0.5dBFS

10

ANALOG INPUT FREQUENCY (MHz

-20.5dBFS

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

1008020 40 60

ANALOG INPUT FREQUENCY (MHz)

MAX1436B toc05

MAX1436B toc08

72

71

70

69

68

67

SNR (dB)

66

65

64

63

62

100

95

90

85

80

75

SFDR (dBc)

70

65

60

55

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

0 120

ANALOG INPUT FREQUENCY (MHz

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

0 120

ANALOG INPUT FREQUENCY (MHz)

MAX1436B toc06

1008020 40 60

MAX1436B toc09

1008020 40 60

MAX1436B

Octal, 12-Bit, 40Msps, 1.8V ADC

with Serial LVDS Outputs

_______________________________________________________________________________________

7

Typical Operating Characteristics (continued)

(V

AV

DD

= 1.8V, V

OV

DD

= 1.8V, V

CV

DD

= 3.3V, V

GND

= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f

CLK

=

40MHz (50% duty cycle), V

DT

= 0V, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT POWER

ANALOG INPUT POWER (dBFS)

SNR (dB)

-5-10-25 -20 -15

37

42

52

57

47

62

67

72

32

-30 0

MAX1436B toc10

fIN = 5.304814MHz

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT POWER

ANALOG INPUT POWER (dBFS)

SINAD (dB)

-5-10-25 -20 -15

37

42

52

57

47

62

MAX1436B toc11

67

72

32

-30 0

fIN = 5.304814MHz

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT POWER

ANALOG INPUT POWER (dBFS)

THD (dBc)

-5-10-25 -20 -15

-80

-85

-75

-65

-60

-70

-55

-50

-45

-95

-90

-30 0

MAX1436B toc12

fIN = 5.304814MHz

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT POWER

ANALOG INPUT POWER (dBFS)

SFDR (dBc)

-5-10-25 -20 -15

60

55

65

75

80

70

85

90

95

45

50

-30 0

MAX1436B toc13

fIN = 5.304814MHz

SIGNAL-TO-NOISE RATIO

vs. SAMPLING RATE

CLOCK FREQUENCY (MHz)

SNR (dB)

353015 20 25

65

64

66

68

69

67

70

71

72

62

63

10 40

MAX1436B toc14

fIN = 5.304814MHz

SIGNAL-TO-NOISE PLUS DISTORTION

vs. SAMPLING RATE

CLOCK FREQUENCY (MHz)

SINAD (dB)

353015 20 25

65

64

66

68

69

67

70

71

72

62

63

10 40

MAX1436B toc15

fIN = 5.304814MHz

TOTAL HARMONIC DISTORTION

vs. SAMPLING RATE

CLOCK FREQUENCY (MHz)

THD (dBc)

3515 20 25 30

-95

-90

-100

-85

-80

-75

-105 10 40

MAX1436B toc16

fIN = 5.304814MHz

SPURIOUS-FREE DYNAMIC RANGE

vs. SAMPLING RATE

CLOCK FREQUENCY (MHz)

SFDR (dBc)

3515 20 25 30

85

90

80

95

100

105

75

10 40

MAX1436B toc17

fIN = 5.304814MHz

SIGNAL-TO-NOISE RATIO

vs. DUTY CYCLE

DUTY CYCLE (%)

SNR (dB)

60 655540 4535 50

69

66

72

67

68

70

71

73

65

30 70

MAX1436B toc18

fIN = 5.304814MHz

MAX1436B

Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(V

AV

DD

= 1.8V, V

OV

DD

= 1.8V, V

CV

DD

= 3.3V, V

GND

= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f

CLK

=

40MHz (50% duty cycle), V

DT

= 0V, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE PLUS DISTORTION

vs. DUTY CYCLE

73

fIN = 5.304814MHz

72

71

70

69

SINAD (dB)

68

67

66

65

30 70

DUTY CYCLE (%)

60 655540 4535 50

TOTAL HARMONIC DISTORTION

vs. DUTY CYCLE

-75 fIN = 5.304814MHz

-80

MAX1436B toc19

-85

-90

THD (dBc)

-95

-100

-105 30 70

DUTY CYCLE (%)

60 655540 4535 50

MAX1436B toc20

SPURIOUS-FREE DYNAMIC RANGE

vs. DUTY CYCLE

100

fIN = 5.304814MHz

95

90

85

SFDR (dBc)

80

75

70

30 70

DUTY CYCLE (%)

MAX1436B toc21

60 655540 4535 50

SIGNAL-TO-NOISE RATIO

vs. TEMPERATURE

73

f

= 40MHz

CLK

= 19.8MHz

f

IN

72

4096-POINT DATA RECORD

71

70

69

SNR (dB)

68

67

66

65

-40 85

-15 10 6035

TEMPERATURE (°C)

SPURIOUS-FREE DYNAMIC RANGE

vs. TEMPERATURE

95

f

= 40MHz

CLK

94

= 19.8MHz

f

IN

4096-POINT DATA RECORD

93

92

91

90

89

SFDR (dBc)

88

87

86

85

-15 10 6035

-40 85

TEMPERATURE (°C)

MAX1436B toc22

MAX1436B toc25

SIGNAL-TO-NOISE PLUS DISTORTION

vs. TEMPERATURE

73

f

= 40MHz

CLK

= 19.8MHz

f

IN

72

4096-POINT DATA RECORD

71

70

69

SINAD (dB)

68

67

66

65

-40 85

-15 10 6035

TEMPERATURE (°C)

SUPPLY CURRENT

vs. SAMPLING RATE (AVDD)

010155 2025303540

CLOCK FREQUENCY (MHz)

(mA)

AVDD

I

360

350

340

330

320

310

300

290

280

MAX1436B toc23

MAX1436B toc26

TOTAL HARMONIC DISTORTION

vs. TEMPERATURE

-90

-91

-92

-93

-94

-95

THD (dBc)

-96

-97

-98 f

= 40MHz

CLK

= 19.8MHz

f

IN

-99 4096-POINT DATA RECORD

-100

-15 10 6035

-40 85

TEMPERATURE (°C)

ANALOG SUPPLY CURRENT

vs. SAMPLING RATE (0VDD)

85

80

75

(mA)

70

OVDD

I

65

60

55

010155 2025303540

CLOCK FREQUENCY (MHz)

MAX1436B toc24

MAX1436B toc27