General Description
The MAX1123 is a monolithic 10-bit, 210Msps analogto-digital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 210Msps while consuming only 460mW.
At 210Msps and an input frequency of 100MHz, the
MAX1123 achieves a spurious-free dynamic range
(SFDR) of 74.5dBc. Its excellent signal-to-noise ratio
(SNR) of 57.4dB at 10MHz remains flat (within 1.5dB)
for input tones up to 500MHz. This makes the MAX1123
ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems.
The MAX1123 requires a single 1.8V supply. The analog input is designed for either differential or singleended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock frequencies as high as 420MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible, and the data format can be selected to be
either two’s complement or offset binary.
The MAX1123 is available in a 68-pin QFN with
exposed pad (EP) and is specified over the industrial
(-40°C to +85°C) temperature range.
For pin-compatible, lower and higher speed versions of
the MAX1123, refer to the MAX1122 (170Msps) and the
MAX1124 (250Msps) data sheets. For a higher speed,
pin-compatible 8-bit version of the MAX1123, refer to
the MAX1121 data sheet.
Applications
Wireless and Wired Broadband Communication
Cable-Head End Systems
Digital Predistortion Receivers
Communications Test Equipment
Radar and Satellite Subsystems Antenna Array
Processing
Features
o 210Msps Conversion Rate
o SNR = 57.4dB/56dB at f
IN
= 100MHz/500MHz
o SFDR = 74.5dBc/62.6dBc at f
IN
= 100MHz/500MHz
o NPR = 53.6dB at f
NOTCH
= 28.8MHz
o Single 1.8V Supply
o 460mW Power Dissipation at 210Msps
o On-Chip Track-and-Hold and Internal Reference
o On-Chip Selectable Divide-by-2 Clock Input
o LVDS Digital Outputs with Data Clock Output
o Evaluation Kit Available (Order MAX1124EVKIT)
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
________________________________________________________________
Maxim Integrated Products
1
Pin Configuration
Ordering Information
19-3028; Rev 2; 8/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX1123EGK -40°C to +85°C 68 QFN-EP*
*
EP = Exposed pad.
TOP VIEW
CC
CC
AVCCOGND
OVCCORP
ORN
D9P
D9N
D8P
D8N
D7P
D7N
5253
51 D6P
50
49
48 D5N
47
46
45
44
43
42
41
40
39
38
37 D2N
36
35
AV
CC
AGND
REFIO
REFADJ
AGND
AV
CC
AGND
INP
INN
AGND
AV
CC
AV
CC
AV
CC
AV
CC
AGND
AGND
CLKDIV 17
T/B
68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AV
64
656667
EP
5859606162 5455565763
MAX1123
AGND
AGND
AGND
AV
D6N
D5P
D4P
D4N
OGND
OV
CC
DCLKP
DCLKN
OV
CC
D3P
D3N
D2P
D1P
D1N
AGND
AGND
2322212019 2726252418 2928 323130
CC
AV
CLKP
CLKN
AGND
AGND
3433
CC
CC
CC
N.C.
OGND
N.C.
OV
OV
AV
N.C.
N.C.
D0N
D0P
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCCto AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs to AGND ...........................-0.3V to (AV
CC
+ 0.3V)
Digital Inputs to AGND.............................-0.3V to (AV
CC
+ 0.3V)
REF, REFADJ to AGND............................-0.3V to (AV
CC
+ 0.3V)
Digital Outputs to OGND.........................-0.3V to (OV
CC
+ 0.3V)
ESD on All Pins (Human Body Model).............................±2000V
Continuous Power Dissipation (T
A
= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C) .........3333mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Maximum Current into Any Pin............................................50mA
ELECTRICAL CHARACTERISTICS
(AVCC= OVCC= 1.8V, V
AGND
= V
OGND
= 0, f
SAMPLE
= 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100Ω ±1%, CL= 5pF, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥ +25°C
guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity INL (Note 1) -2 ±0.4 +2 LSB
Differential Nonlinearity DNL No missing codes (Note 1) -1.0 ±0.3 +1.5 LSB
Transfer Curve Offset V
Offset Temperature Drift ±20 µV/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range V
Full-Scale Range Temperature
Drift
Common-Mode Input Range V
Input Capacitance C
Differential Input Resistance R
Full-Power Analog Bandwidth FPBW Figure 8 600 MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage V
Reference Temperature Drift 90 ppm/°C
REFADJ Input High Voltage V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate f
Minimum Sampling Rate f
OS
FS
CM
IN
IN
REFIO
REFADJ
SAMPLE
SAMPLE
(Note 1)
(Note 1) 1100 1250 1375 mV
Used to disable the internal reference
TA ≥ +25°C -25 +25
(Note 2) -37 +37
3.00 4.3 6.25 kΩ
1.18 1.24 1.30 V
AV
CC
0.3
210 MHz
130 ppm/°C
1.38
±0.18
3pF
-
20 MHz
LSB
P-P
V
V
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVCC= OVCC= 1.8V, V
AGND
= V
OGND
= 0, f
SAMPLE
= 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100Ω ±1%, CL= 5pF, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥ +25°C
guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Clock Duty Cycle Set by clock management circuit 40 to 60 %
Aperture Delay t
Aperture Jitter t
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude (Note 2) 200 500 mV
Clock Input Common-Mode
Voltage Range
Clock Differential Input
Resistance
Clock Differential Input
Capacitance
DYNAMIC CHARACTERISTICS (at -0.5dBFS)
Signal-to-Noise Ratio SNR
Signal-to-Noise
and Distortion
Spurious-Free
Dynamic Range
Worst Harmonics
(HD2 or HD3)
Two-Tone Intermodulation
Distortion
LVDS DIGITAL OUTPUTS (D0P/N–D9P/N, ORP/N)
Differential Output Voltage |VOD| 250 450 mV
AD
AJ
R
CLK
C
CLK
SINAD
SFDR
IMD
100
IMD
500
fIN = 10MHz, TA ≥ +25°C 56 57.5
fIN = 100MHz, TA ≥ +25°C 55.5 57.1
fIN = 180MHz 57
= 500MHz 56
f
IN
fIN = 10MHz, TA ≥ +25°C 55.5 57.4
fIN = 100MHz, TA ≥ +25°C5557
fIN = 180MHz 56.5
f
= 500MHz 55
IN
fIN = 10MHz, TA ≥ +25°C6377
fIN = 100MHz, TA ≥ +25°C6172
fIN = 180MHz 66.3
= 500MHz 62.5
f
IN
fIN = 10MHz -77
fIN = 100MHz -72
fIN = 180MHz -66.3
= 500MHz -62.5
f
IN
f
= 99MHz at -7dBFS,
IN1
= 101MHz at -7dBFS
f
IN2
f
= 498.5MHz at -7dBFS,
IN1
= 502.5MHz at -7dBFS
f
IN2
350 ps
0.21 ps
1.15
±0.2
11 ±
25%
5pF
-75
-58
RMS
P-P
V
kΩ
dB
dB
dBc
dBc
dBc
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVCC= OVCC= 1.8V, V
AGND
= V
OGND
= 0, f
SAMPLE
= 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100Ω ±1%, CL= 5pF, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥ +25°C
guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range is defined as 1023 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; T
A
= T
MIN
to T
MAX
.
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
Output Offset Voltage OV
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input Voltage Low V
Digital Input Voltage High V
TIMING CHARACTERISTICS
CLK to Data Propagation Delay t
CLK to DCLK Propagation Delay t
Data Valid to DCLK Rising Edge
LVDS Output Rise-Time t
LVDS Output Fall-Time t
Output Data Pipeline Delay t
POWER REQUIREMENTS
Analog Supply Voltage Range AV
Digital Supply Voltage Range OV
Analog Supply Current
Digital Supply Current I
Total Power Dissipation P
Power-Supply Rejection Ratio
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OS
IL
IH
PDL
CPDL
t
-
CPDL
t
PDL
RISE
FALL
LATENCY
CC
CC
I
AVCCfIN
OVCCfIN
DISS
PSRR
Figure 4 1.5 ns
Figure 4 3.01 ns
Figure 4 (Note 2) 1.23 1.51 1.84 ns
20% to 80%, CL = 5pF 460 ps
20% to 80%, CL = 5pF 460 ps
= 100MHz 210 280 mA
= 100MHz 45 75 mA
fIN = 100MHz 460 640 mW
Offset 1.6 mV/V
Gain 1.9 %FS/V
1.125 1.310 V
0.8 x
AV
CC
1.7 1.8 1.9 V
1.7 1.8 1.9 V
8
0.2 x
AV
CC
V
V
Clock
cycles
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________
5
)
Typical Operating Characteristics
(AVCC= OVCC= 1.8V, V
AGND
= V
OGND
= 0, f
SAMPLE
= 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R
L
= 100Ω, TA= +25°C.)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
0
-10
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
HD2
HD3
0 40608020 100 120
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
0
f
= 210.0057MHz
SAMPLE
-10
= 500.0196MHz
f
IN
= -0.4975dBFS
A
IN
-20
SNR = 55.9dB
-30
SFDR = 62.5dBc
HD2 = -69.5dBc
-40
HD3 = -62.5dBc
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
0 40608020 100 120
HD3
ANALOG INPUT FREQUENCY (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
= 210.0057MHz, AIN = -0.5dBFS)
(f
SAMPLE
-50
f
= 210.0057MHz
SAMPLE
= 11.5103MHz
f
IN
= -0.542dBFS
A
IN
SNR = 57.5dB
SFDR = 79.5dBc
HD2 = -82dBc
HD3 = -86.3dBc
HD2
MAX1123 toc01
MAX1123 toc04
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
0
-10
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
0 40608020 100 120
ANALOG INPUT FREQUENCY (MHz)
HD3
f
SAMPLE
= 60.1152MHz
f
IN
= -0.4885dBFS
A
IN
SNR = 57.4dB
SFDR = 76.2dBc
HD2 = -83.9dBc
HD3 = -76.2dBc
SNR vs. ANALOG INPUT FREQUENCY
= 210.0057MHz, AIN = -0.5dBFS)
(f
SAMPLE
59
58
57
56
55
54
SNR (dB)
53
52
51
50
0 500
f
(MHz)
IN
SNR vs. ANALOG INPUT AMPLITUDE
= 210.0057MHz, fIN = 60.0126MHz
(f
SAMPLE
62
= 210.0057MHz
HD2
400300200100
MAX1123 toc02
AMPLITUDE (dB)
MAX1123 toc05
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0 40608020 100 120
ANALOG INPUT FREQUENCY (MHz)
f
= 210.0057MHz
SAMPLE
= 183.5242MHz
f
IN
= -0.5245dBFS
A
IN
SNR = 57dB
SFDR = 66.6dBc
HD2 = -82.9dBc
HD3 = -66.9dBc
HD2
SFDR vs. ANALOG INPUT FREQUENCY
= 210.0057MHz, AIN = -0.5dBFS)
(f
SAMPLE
85
80
75
70
65
60
55
SFDR (dBc)
50
45
40
35
30
0 500
f
(MHz)
IN
SFDR vs. ANALOG INPUT AMPLITUDE
= 210.0057MHz, fIN = 60.0126MHz)
(f
SAMPLE
80
HD3
400300200100
MAX1123 toc03
MAX1123 toc06
-60
-70
HD3
-80
HD2/HD3 (dBc)
-90
-100
0 500
HD2
f
(MHz)
IN
57
MAX1123 toc07
52
47
SNR (dB)
42
37
32
27
400300200100
-28 -16 -12-24 -20 -8 -4 0
ANALOG INPUT AMPLITUDE (dBFS)
MAX1123 toc08
75
70
65
SFDR (dBc)
60
55
50
-28 -16 -12-24 -20 -8 -4 0
ANALOG INPUT AMPLITUDE (dBFS)
MAX1123 toc09
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVCC= OVCC= 1.8V, V
AGND
= V
OGND
= 0, f
SAMPLE
= 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R
L
= 100Ω, TA= +25°C.)
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
= 210.0057MHz, fIN = 60.0126MHz)
(f
SAMPLE
-50
-55
-60
-65
-70
HD2/HD3 (dBc)
-75
-80
-85
-90
-28 -16 -12-24 -20 -8 -4 0
HD2
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 vs. f
(fIN = 60.0126MHz, AIN = -0.5dBFS)
-60
-68
-76
-84
HD2/HD3 (dBc)
-92
-100
10 2101501107030 190
f
SAMPLE
HD3
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.5
0.4
0.3
0.2
0.1
0
DNL (LSB)
-0.1
-0.2
-0.3
-0.4
-0.5
256 3841280 512 640 768 896 1024
DIGITAL OUTPUT CODE
HD3
SAMPLE
HD2
(MHz)
1701309050
MAX1123 toc10
MAX1123 toc13
MAX1123 toc16
SNR vs. f
SAMPLE
(fIN = 60.0126MHz, AIN = -0.5dBFS)
60
59
58
57
56
55
SNR (dB)
54
53
52
51
50
10 210
f
(MHz)
SAMPLE
TWO-TONE IMD PLOT (8192-POINT
DATA RECORD, COHERENT SAMPLING)
0
f
= 210.0057MHz
SAMPLE
-10
= 99.0298MHz
f
IN1
= 101.0293MHz
f
IN2
-20
= A
= -7dBFS
A
IN1
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
IN2
IMD = -75dBc
2f
- f
IN1
0 40608020 100 120
ANALOG INPUT FREQUENCY (MHz)
GAIN BANDWIDTH PLOT
= 210.0057MHz, AIN = -0.5dBFS)
(f
SAMPLE
2
0
-2
-4
-6
GAIN (dB)
-8
-10
-12
10 100 1000
ANALOG INPUT FREQUENCY (MHz)
SFDR vs. f
SAMPLE
(fIN = 60.0126MHz, AIN = -0.5dBFS)
90
MAX1123 toc11
80
70
SFDR (dBc)
60
50
40
170130 150 1909050 70 11030
10 2101501107030 190
f
(MHz)
SAMPLE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.5
0.4
MAX1123 toc14
0.3
0.2
f
IN1
f
IN2
2f
-
IN2
f
IN2
IN1
0.1
0
INL (LSB)
-0.1
-0.2
-0.3
-0.4
-0.5
256 3841280 512 640 768 896 1024
DIGITAL OUTPUT CODE
SNR vs. TEMPERATURE (fIN = 64.9974MHz,
= 210.0428MHz, AIN = -0.5dBFS)
f
SAMPLE
60
59
MAX1123 toc17
58
57
56
55
SNR (dB)
54
53
52
51
50
-40 85
TEMPERATURE (°C)
MAX1123 toc12
1701309050
MAX1123 toc15
MAX1123 toc18
603510-15
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(AVCC= OVCC= 1.8V, V
AGND
= V
OGND
= 0, f
SAMPLE
= 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R
L
= 100Ω, TA= +25°C.)
SINAD vs. TEMPERATURE (fIN = 64.9974MHz,
= 210.0428MHz, AIN = -0.5dBFS)
f
SAMPLE
60
59
58
57
56
55
54
SINAD (dBc)
53
52
51
50
-40 85
TEMPERATURE (°C)
FS VOLTAGE vs. FS ADJUST RESISTOR
1.34
1.32
1.30
1.28
1.26
(V)
FS
1.24
V
1.22
1.20
1.18
1.16
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND AGND
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND REFIO
0 1000
FS ADJUST RESISTOR (Ω)
603510-15
FIGURE 6
900800600 700200 300 400 500100
MAX1123 toc19
MAX1123 toc22
SFDR vs. TEMPERATURE (fIN = 64.9974MHz,
= 210.0428MHz, AIN = -0.5dBFS)
f
SAMPLE
80
75
70
65
SFDR (dBc)
60
55
50
-40 85
TEMPERATURE (°C)
603510-15
SNR vs. VOLTAGE SUPPLY
= 60.0126MHz, AIN = -0.5dBFS)
(f
IN
60
AVCC = OV
59
58
57
56
(dB)
55
SNR
54
53
52
51
50
1.5 2.1
CC
2.01.91.81.71.6
VOLTAGE SUPPLY (V)
MAX1123 toc20
MAX1123 toc23
POWER DISSIPATION vs. f
(fIN = 60.0126MHz, AIN = -0.5dBFS)
495
485
475
465
(mW)
DISS
455
P
445
435
425
10 2101501107030 190
f
(MHz)
SAMPLE
INTERNAL REFERENCE vs. SUPPLY VOLTAGE
= 210.0057MHz)
(f
SAMPLE
MEASURED AT THE REFIO PIN
REFADJ = AV
1.5 2.1
= OV
CC
CC
SUPPLY VOLTAGE (V)
(V)
REFIO
V
1.2325
1.2320
1.2315
1.2310
1.2305
1.2300
SAMPLE
1701309050
2.01.91.81.71.6
MAX1123 toc21
MAX1123 toc24
(DC INPUT, 256k-POINT DATA RECORD)
NOISE HISTOGRAM
5.0E+05
4.0E+05
3.0E+05
2.0E+04
CODE COUNTS
1.0E+04
0.0E+00
467263
13207
511
DIGITAL OUTPUT NOISE
174671
512 513
f
SAMPLE
219
514 515
= 210MHz
MAX1123 toc25
PROPAGATION DELAY (ns)
PROPAGATION DELAY TIMES
vs. TEMPERATURE
6
5
4
3
2
1
0
-40 85
t
CPDL
t
PDL
TEMPERATURE (°C)
603510-15
MAX1123 toc26
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
8 _______________________________________________________________________________________
Pin Description
,
Typical Operating Characteristics (continued)
(AVCC= OVCC= 1.8V, V
AGND
= V
OGND
= 0, f
SAMPLE
= 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R
L
= 100Ω, TA= +25°C.)
SINAD vs. CLOCK DUTY CYCLE (fIN = 1.4106MHz
f
SAMPLE
60
59
58
57
56
55
SINAD (dB)
54
53
52
51
50
30 48 5436 42 60 66 72
PIN NAME FUNCTION
1, 6, 11–14, 20, 25,
62, 63, 65
2, 5, 7, 10, 15, 16,
18, 19, 21, 24, 64,
66, 67, EP
= 210.0428MHz, AIN = -0.5dBFS)
CLOCK DUTY CYCLE (%)
NOISE POWER RATIO PLOT
-40
MAX1123 toc27
-50
-60
-70
-80
-90
POWER SPECTRAL DENSITY (dB)
f
= 210MHz
SAMPLE
= 28.8MHz
f
NOTCH
-100
NPR = 53.6dB
5 101520253035
ANALOG INPUT FREQUENCY (MHz)
AV
CC
AGND Analog Converter Ground. Connect the converter’s exposed pad (EP) to AGND.
Analog Supply Voltage. Bypass each pin with a 0.1µF capacitor for best decoupling results.
MAX1123 toc28
Reference Input/Output. With REFADJ pulled high through a 1kΩ resistor, this I/O port allows
3 REFIO
an external reference source to be connected to the MAX1123. With REFADJ pulled low
through the same 1kΩ resistor, the internal 1.23V bandgap reference is active.
Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor
or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and
4 REFADJ
REFIO (increases FS range). If REFADJ is connected to AV
internal reference can be overdriven with an external source connected to REFIO. If REFADJ
through a 1kΩ resistor, the
CC
is connected to AGND through a 1kΩ resistor, the internal reference is used to determine the
full-scale range of the data converter.
8 INP Positive Analog Input Terminal
9 INN Negative Analog Input Terminal
17 CLKDIV
Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at the input clock rate.
22 CLKP
23 CLKN
True Clock Input. This input requires an LVDS-compatible input level to maintain the
converter’s excellent performance.
Complementary Clock Input. This input requires an LVDS-compatible input level to maintain
the converter’s excellent performance.
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN NAME FUNCTION
26, 45, 61 OGND Digital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41, 44, 60 OV
29–32 N.C. No Connection. Do not connect to these pins.
33 D0N Complementary Output Bit 0 (LSB)
34 D0P True Output Bit 0 (LSB)
35 D1N Complementary Output Bit 1
36 D1P True Output Bit 1
37 D2N Complementary Output Bit 2
38 D2P True Output Bit 2
39 D3N Complementary Output Bit 3
40 D3P True Output Bit 3
42 DCLKN
43 DCLKP
46 D4N Complementary Output Bit 4
47 D4P True Output Bit 4
48 D5N Complementary Output Bit 5
49 D5P True Output Bit 5
50 D6N Complementary Output Bit 6
51 D6P True Output Bit 6
52 D7N Complementary Output Bit 7
53 D7P True Output Bit 7
54 D8N Complementary Output Bit 8
55 D8P True Output Bit 8
56 D9N Complementary Output Bit 9 (MSB)
57 D9P True Output Bit 9 (MSB)
58 ORN
59 ORP
CC
Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results.
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock. There is a 2.1ns delay
between CLKP and DCLKP.
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock. There is a 2.1ns delay between CLKN
and DCLKN.
Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP
flags this condition by transitioning high.
68 T/B
Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input
controls the digital output format of the MAX1123. T/B has an internal pulldown resistor.
T/B = 0: Two’s complement output format
T/B = 1: Binary output format
MAX1123
Detailed Description—Theory
of Operation
The MAX1123 uses a fully differential, pipelined architecture that allows for high-speed conversion, optimized accuracy and linearity, while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a commonmode voltage of 1.4V, and accept a differential analog
input voltage swing of ±0.3125V each, resulting in a typical differential full-scale signal swing of 1.25V
P-P
.
INP and INN are buffered prior to entering each trackand-hold (T/H) stage and are sampled when the differential sampling clock signal transitions high. A 2-bit ADC
following the first T/H stage then digitizes the signal, and
controls a 2-bit digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 10-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital correction logic to generate the final output code. The result
is a 10-bit parallel digital output word in user-selectable
two’s complement or binary output formats with LVDScompatible output levels. See Figure 1 for a more
detailed view of the MAX1123 architecture.
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
10 ______________________________________________________________________________________
Figure 1. MAX1123 Block Diagram
Figure 2. Simplified Analog Input Architecture
Figure 3. Simplified Reference Architecture
CLKDIV
CLKP
CLKN
INP
INN
COMMON-MODE
INP
2.2kΩ
TO COMMON-MODE INPUT
CLOCKDIVIDER
CONTROL
INPUT
BUFFER
2.2kΩ2.2kΩ
BUFFER
2.2kΩ
TO COMMON-MODE INPUT
CLOCK
MANAGEMENT
REFERENCE
REFIO
AV
CC
INN
AGND
T/H
REFADJ
10-BIT PIPELINE
QUANTIZER CORE
MAX1123
1V
LVDS
DATA PORT
ADC FULL-SCALE = REFT - REFB
10
REFT
REFB
REFERENCE
BUFFER
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
DCLKP
DCLKN
D0P/N–D9P/N
ORP
ORN
REFERENCE-
SCALING
AMPLIFIER
G
REFIO
0.1μF
REFADJ
1kΩ
AV
CC
AVCC/2
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1123. Differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced
AC performance as the signals are progressing through
the analog stages. The MAX1123 analog inputs are selfbiased at a common-mode voltage of 1.4V and allow a
differential input voltage swing of 1.25V
P-P
. Both inputs
are self-biased through 2.2kΩ resistors, resulting in a
typical differential input resistance of 4.4kΩ. It is recommended to drive the analog inputs of the MAX1123 in
AC-coupled configuration to achieve best dynamic performance. See the
AC-Coupled Analog Inputs
section for
a detailed discussion of this configuration.
On-Chip Reference Circuit
The MAX1123 features an internal 1.23V bandgap reference circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the fullscale range of the MAX1123. Bypass REFIO with a
0.1µF capacitor to AGND. To compensate for gain
errors or increase the ADC’s full-scale range, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100kΩ trim
potentiometer) between REFADJ and AGND or
REFADJ and REFIO. See the
Applications Information
section for a detailed description of this process.
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
______________________________________________________________________________________ 11
Figure 4. System and Output Timing Diagram
Figure 5. Simplified LVDS Output Architecture
SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT
INN
INP
t
AD
CLKN
N N + 1 N + 8 N + 9
CLKP
DCLKP
DCLKN
D0P/N–D9P/N
ORP/N
t
- t
CPDL
PDL
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
~ 0.4 x t
t
CPDL
t
LATENCY
N - 7N - 8 N N + 1
t
PDL
N - 8 N - 7 N N + 1
SAMPLE
with t
SAMPLE
= 1/f
SAMPLE
N - 1
t
CH
t
- t
CPDL
PDL
V
OP
2.2kΩ 2.2kΩ
t
CL
OV
CC
V
ON
OGND
MAX1123
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1123
with an LVDS-compatible clock to achieve the best
dynamic performance. The clock signal source must be
a high-quality, low phase noise to avoid any degradation in the noise performance of the ADC. The clock
inputs (CLKP, CLKN) are internally biased to 1.2V,
accept a differential signal swing of 0.2V
P-P
to 1.0V
P-P
and are usually driven in AC-coupled configuration.
See the
Differential, AC-Coupled Clock Input
in the
Applications Information
section for more circuit details
on how to drive CLKP and CLKN appropriately.
Although not recommended, the clock inputs also
accept a single-ended input signal.
The MAX1123 also features an internal clock management circuit (duty-cycle equalizer) that ensures that the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty cycle clock signal,
which desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock frequency of >20MHz to work appropriately and according to data sheet specifications.
Clock Outputs (DCLKP, DCLKN)
The MAX1123 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
2.1ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 4 for timing details.
Divide-by-2 Clock Control (CLKDIV)
The MAX1123 offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at onehalf the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that only operate with update rates one-half of the converter’s sampling rate. Connecting CLKDIV to OV
CC
allows data to be updated at the speed of the ADC input
clock.
System Timing Requirements
Figure 4 depicts the relationship between the clock
input and output, analog input, sampling event, and
data output. The MAX1123 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of the DCLKP (DCLKN)
clock, but has an internal latency of eight clock cycles.
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
12 ______________________________________________________________________________________
Table 1. MAX1123 Digital Output Coding
INP ANALOG
VOLTAGE LEVEL
INN ANALOG
VOLTAGE LEVEL
OUT-OF-RANGE
ORP (ORN)
BINARY
DIGITAL OUTPUT CODE
(D9–D0)
TWO’S COMPLEMENT
DIGITAL OUTPUT CODE
(D9–D0)
> VCM + 0.3125V < VCM - 0.3125V 1 (0)
VCM + 0.3125V VCM - 0.3125V 0 (1)
V
CM
V
- 0.3125V VCM + 0.3125V 0 (1)
CM
< VCM - 0.3125V > V
V
CM
+ 0.3125V 1 (0)
CM
0 (1)
11 1111 1111
(exceeds positive full scale,
OR set)
11 1111 1111
(represents positive full
scale)
10 0000 0000 or
01 1111 1111
(represents midscale)
00 0000 0000
(represents negative full
scale)
00 0000 0000
(exceeds negative full scale,
OR set)
01 1111 1111
(exceeds positive full scale,
OR set)
01 1111 1111
(represents positive full
scale)
00 0000 0000 or
11 1111 1111
(represents midscale)
10 0000 0000
(represents negative full
scale)
10 0000 0000
(exceeds negative full scale,
OR set)
Digital Outputs (D0P/N–D9P/N, DCLKP/N,
ORP/N) and Control Input
T
/B
The digital outputs D0P/N–D9P/N, DCLKP/N, and
ORP/N are LVDS compatible, and data on
D0P/N–D9P/N is presented in either binary or two’s
complement format (Table 1). The T/B control line is an
LVCMOS-compatible input, which allows the user to
select the desired output format. Pulling T/B low outputs data in two’s complement and pulling it high presents data in offset binary format on the 10-bit parallel
bus. T/B has an internal pulldown resistor and may be
left unconnected in applications using only two’s complement output format. All LVDS outputs provide a typical voltage swing of 0.4V around a common-mode
voltage of approximately 1.2V, and must be terminated
at the far end of each transmission line pair (true and
complementary) with 100Ω. The LVDS outputs are powered from a separate power supply, which can be
operated between 1.7V and 1.9V.
The MAX1123 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out of range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although differential LVDS reduces single-ended
transients to the supply and ground planes, capacitive
loading on the digital outputs should still be kept as low
as possible. Using LVDS buffers on the digital outputs
of the ADC when driving off-board may improve overall
performance and reduce system timing constraints.
Applications Information
Full-Scale Range Adjustments Using the
Internal Bandgap Reference
The MAX1123 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, an external resistor value ranging from 13kΩ to 1MΩ may be
added between REFADJ and AGND. A similar
approach can be taken to increase the ADCs full-scale
range. Adding a variable resistor, potentiometer, or
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
V
0.1μF
CLK
BUFFER
REFERENCE-
AMPLIFIER
G
AV
CCAVCC
SCALING
REFIO
REFADJ
0.1μF
13kΩ TO 1MΩ
13kΩ TO 1MΩ
/2
ADC FULL-SCALE = REFT - REFB
REFT
REFB
REFERENCE
BUFFER
1V
CONTROL LINE TO
DISABLE REFERENCE
SINGLE-ENDED
INPUT TERMINAL
0.1μF
50Ω
2
3
510Ω510Ω
8
MC100LVEL16
45
0.01μF
VGND
7
6
150Ω
150Ω
0.1μF
0.1μF
INP
INN
AV
CCOVCC
CLKPCLKN
MAX1123
AGND OGND
D0P/N–D9P/N
10
MAX1123
predetermined resistor value between REFADJ and
REFIO increases the full-scale range of the data converter. Figure 6 shows the two possible configurations
and their impact on the overall full-scale range adjustment of the MAX1123. Do not use resistor values of less
than 13kΩ to avoid instability of the internal gain regulation loop for the bandgap reference.
Differential, AC-Coupled, PECL-Compatible
Clock Input
The preferred method of clocking the MAX1123 is differentially with LVDS- or PECL-compatible input levels. To
accomplish this, a 50Ω reverse-terminated clock signal
source with low phase noise is AC-coupled into a fast
differential receiver such as the MC100LVEL16
(Figure 7). The receiver produces the necessary PECL
output levels to drive the clock inputs of the data converter.
Differential, AC-Coupled Analog Input
An RF transformer provides an excellent solution to
convert a single-ended source signal to a fully differential signal, required by the MAX1123 for optimum
dynamic performance. In general, the MAX1123 provides the best SFDR and THD with fully differential
input signals and it is not recommended to drive the
ADC inputs in single-ended configuration. In differential
input mode, even-order harmonics are usually lower
since INP and INN are balanced, and each of the ADC
inputs only requires half the signal swing compared to
a single-ended configuration.
Figure 8 depicts a secondary-side termination of the 1:1
transformer into two separate 25Ω loads. Terminating the
transformer in this fashion reduces the potential effects of
transformer parasitics. The source impedance combined
with the shunt capacitance provided by a PCB and the
ADC’s parasitic capacitance reduce the combined bandwidth to approximately 550MHz.
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX1123 can be
used in single-ended mode (Figure 9). Analog signals
can be AC-coupled to the positive input INP through a
0.1µF capacitor and terminated with a 50Ω resistor to
AGND. The negative input should be 25Ω reverse-terminated and AC grounded with a 0.1µF capacitor.
Grounding, Bypassing, and Board
Layout Considerations
The MAX1123 requires board layout design techniques
suitable for high-speed data converters. This ADC provides separate analog and digital power supplies. The
analog and digital supply voltage pins accept input
voltage ranges of 1.7V to 1.9V. Although both supply
types can be combined and supplied from one source,
it is recommended to use separate sources to cut down
on performance degradation caused by digital switching currents, which can couple into the analog supply
network. Isolate analog and digital supplies (AV
CC
and
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
14 ______________________________________________________________________________________
Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination
Figure 9. Single-Ended AC-Coupled Analog Input
Configuration
SINGLE-ENDED
INPUT TERMINAL
0.1μF
ADT1–1WT
25Ω
25Ω
0.1μF
15Ω
15Ω
INP
INN
SINGLE-ENDED
INPUT TERMINAL
CC
0.1μF
0.1μF
25Ω
INP
INN
OV
CC
D0P/N–D9P/N
10
AV
CC
MAX1123
AGND OGND
OV
CC
AV
MAX1123
AGND OGND
50Ω
D0P/N–D9P/N
10
OVCC) where they enter the PCB with separate networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor in
parallel with 10µF and 1µF ceramic capacitors.
Additionally, the ADC requires each supply pin to be
bypassed with separate 0.1µF ceramic capacitors
(Figure 10). Locate these capacitors directly at the ADC
supply pins or as close as possible to the MAX1123.
Choose surface-mount capacitors, which are preferably
located on the same side as the converter, to save
space and minimize the inductance.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long distances before they are recombined at a common
source ground, resulting in large and undesirable
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sections of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
The MAX1123 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater
design flexibility, increased thermal efficiency, and optimized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PCB side of
the package. This allows a solid attachment of the
package to the PCB with standard infrared (IR) flow soldering techniques.
Note that thermal efficiency is not the key factor, since
the MAX1123 features low-power operation. The
exposed pad is the key element to ensure a solid
ground connection between the DAC and the PCB’s
analog ground layer.
Considerable care must be taken, when routing the
digital output traces for a high-speed, high-resolution
data converter. It is essential to keep trace lengths at a
minimum and place minimal capacitive loading—less
than 5pF—on any digital trace to prevent coupling to
sensitive analog sections of the ADC. It is recommended to run the LVDS output traces as differential lines
with 100Ω characteristic impedance from the ADC to
the LVDS load device.
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
______________________________________________________________________________________ 15
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1123
BYPASSING—ADC LEVEL
AV
NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL)
SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1μF CAPACITOR CLOSE TO THE ADC.
OV
CC
0.1μF 0.1μF
OGNDAGND
MAX1123
AGND OGND
CC
D0P/N–D9P/N
10
BYPASSING—BOARD LEVEL
AV
CC
1μF10μF47μF
OV
CC
1μF10μF47μF
ANALOG POWERSUPPLY SOURCE
DIGITAL/OUTPUTDRIVER POWERSUPPLY SOURCE
MAX1123
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX1123 are measured using the histogram method with an input frequency of 10MHz.
Differential Nonlinearly (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1123’s DNL specification is measured with the histogram method based on a 10MHz input tone.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR
dB[max]
= 6.02dBx N + 1.76
dB
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calculation and should be considered when determining the
SNR in ADC.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In case of the MAX1123, SINAD
is computed from a curve fit.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -7dB full scale.
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
16 ______________________________________________________________________________________
Figure 11. Aperture Jitter/Delay Specifications
Pin-Compatible Higher Speed/
Lower Resolution Versions
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
68 QFN-EP G6800-4
21-0122
CLKP
CLKN
ANALOG
INPUT
t
AD
SAMPLED
DATA (T/H)
TRACK TRACK
T/H
t
AJ
HOLD
PART
MAX1122 10 170
MAX1124 10 250
MAX1121 8 250
RESOLUTION
(Bits)
SPEED GRADE
(Msps)
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
17
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
0 10/03 Initial release —
1 2/04 — —
2 8/08
REVISION
DATE
DESCRIPTION
Minor corrections to the data sheet to fix problems found during off-shore
transfer.
PAGES
CHANGED
3, 4
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