Maxim MAX1101CWG Datasheet

_______________General Description

The MAX1101 is a highly integrated IC designed primarily for digitizing the output of a linear CCD array. It provides the components required for all necessary analog functions, including clamp circuitry for blacklevel correction or correlated double sampling (CDS), a three-input multiplexer (mux), and an 8-bit analog-todigital converter (ADC).

The MAX1101 operates with a sample rate up to 1MHz and with a wide range of linear CCDs. The logic interface is serial, and a single input sets the bidirectional data line as either data in or data out, thus minimizing the I/O pins required for communication.

Packaged in a 24-pin SO, the MAX1101 is available in the commercial (0°C to +70°C) temperature range.

________________________Applications

Scanners Fax Machines Digital Copiers CCD Imaging

____________________________Features

♦ 1.0 Million Pixels/sec Conversion Rate ♦ Built-In Clamp Circuitry for Black-Level

Correction or Correlated Double Sampling

♦ 64-Step PGA, Programmable from Gain = -2 to -10 ♦ Auxiliary Mux Inputs for Added Versatility ♦ Compatible with a Large Range of CCDs ♦ 8-Bit ADC Included ♦ Space-Saving, 24-Pin SO Package

MAX1101

Single-Chip, 8-Bit CCD Digitizer

with Clamp and 6-Bit PGA

________________________________________________________________

Maxim Integrated Products

GND

0.1µF

21 20

19 18

17 16 15

14 13

2 3

4 5

GND

CLAMP

+5V DC (SUPPLY)

+5V DC (REFERENCE)

VIDSAMP

LOAD DATA

SCLK

MODE

GND

REFBIAS

REF+

AIN2

REFGND

REF-

AIN1

GND

CCDIN

EXT

0.047µF

AUXILIARY

ANALOG INPUTS

CCD

ARRAY

MAX1101

µP/µC/

STATE LOGIC

___________________________________________________Typical Operating Circuit

19-1166; Rev 0; 12/96

PART

MAX1101CWG 0°C to +70°C

TEMP. RANGE PIN-PACKAGE

24 Wide SO

______________Ordering Information

Pin Configuration appears on last page.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

MAX1101

Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= V

REFBIAS

= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, C

EXT

= 47nF, TA= T

MIN

to T

MAX

unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND............................................................-0.3V to +12V

All Pins to GND...........................................-0.3V to (V

+ 0.3V)

Current into Every Pin (except V

).................................±20mA

Current into V

...............................................................±50mA

Continuous Power Dissipation (T

= +70°C)

SO (derate 11.76mW/°C above +70°C)......................941mW

Operating Temperature Range...............................0°C to +70°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

WHITE

REF+

- V

REF-

) / G

PGA

nA1 50I

L(CCDIN)

Input Leakage (Note 2)

Ω60 150R

ON(BSS)

Black Sample Switch On-Resistance

% Gain±5PGA Gain Error

V/V0.125Gain Adjust Step Size

Steps64Gain Adjust Resolution

V/V-9.375 -9.875 -10.375Maximum PGA Gain Setting

V/V-1.9 -2 -2.1Minimum PGA Gain Setting

0.25

WHITE

Maximum Peak CCD Differential Signal Range

1.25

LSB±0.5 ±1DNLDifferential Nonlinearity

Bits8NResolution

ns10t

Aperture Delay

MHz1Input Full-Power Bandwidth

kHz1Minimum Sample Rate

MHz0.67 1.2f

Maximum Sample Rate

LSB±1 ±1.5INLIntegral Nonlinearity

LSB±2.5TUETotal Unadjusted Error %µV/°C125TCVOSZero-Scale Drift %FS/°C0.016TCFSFull-Scale Drift

UNITSMIN TYP MAXSYMBOLPARAMETER

Including black sample switch off-leakage

No-missing-codes guaranteed

PGA

= -10

PGA

= -2

VIN= 2.5Vp-p

(Note 1)

Best straight-line fit

CONDITIONS

CCD Interface Offset Voltage V

OS(CCD)VVIDEO

= V

RESET

(Figure 4) 0 4 8 LSB

Input Voltage Range V

REF-

REF+

IN(ON)

Channel on 45

Input Capacitance (Note 1)

IN(OFF)

Channel off 10

On-Resistance R

120 Ω

ANALOG-TO-DIGITAL CONVERTER

ANALOG INPUT—CCD INTERFACE

ANALOG INPUT—AUXILIARY INPUTS

MAX1101

Single-Chip, 8-Bit CCD Digitizer

with Clamp and 6-Bit PGA

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= V

REFBIAS

= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, C

EXT

= 47nF, TA= T

MIN

to T

MAX

unless otherwise noted.)

V1.5V

Digital Input Voltage Low

V3.5V

Digital Input Voltage High

mA20 40I

Supply Current

dB48 60PSRRPSRR, PGA and ADC

V4.75 5 5.25V

Positive Supply-Voltage Range

V0.49 0.50 0.51V

REF-

Negative Reference Voltage

V2.94 3.00 3.06V

REF+

Positive Reference Voltage

UNITSMIN TYP MAXSYMBOLPARAMETER

Internally generated, V

REFBIAS

= 5V

4.75V ≤ VDD≤ 5.25V

Internally generated, V

REFBIAS

= 5V

CONDITIONS

Digital Input Leakage Current I

-10 10 µA

Digital Output Voltage High V

SOURCE

= 4mA VDD- 0.5 V

Digital Output Voltage Low V

SINK

= 4mA 0.5 V

Digital Output Leakage Current I

Output in high-impedance mode -10 10 µA

SCLK Frequency f

SCLK

10 MHz

VIDSAMP Pulse Width t

500 ns

VIDSAMP to CLAMP Separation t

50 ns

LOAD Pulse Width t

50 ns

VIDSAMP Fall to SCLK Rise Time t

VLS

MODE = 1 50 ns

VIDSAMP Fall to DATA t

VLD

MODE = 1 60 ns

SCLK Rise to DATA t

60 ns

DATA Set-Up Time t

DSU

20 ns

DATA Hold Time t

20 ns

LOAD Fall to SCLK Rise Time t

MODE = 0 50 ns

SCLK Rise to LOAD Rise Time t

MODE = 0 50 ns

MODE Setup Time t

MSU

Same as bus-relinquish time 50 ns

CLAMP Pulse Width t

300 ns

CLAMP Fall to Video Update t

(Note 1) 20 ns

Digital Quiet Time (Note 3) t

± around VIDSAMP falling edge 20 ns

SCLK Pulse Width t

SPW

50 ns

Reset to CLAMP Separation t

(Note 2) 50 ns

Note 1: Due to leakage in the PGA and ADC, operation at sample rates below 1ksps is not recommended, as

performance may degrade, particularly at high temperatures.

Note 2: Production test equipment settling time prohibits leakage measurements below 1nA.

Lab equipment has shown the MAX1101 switch input leakage below 1pA at T

= +25°C, and below 50pA at TA= +70°C.

Note 3: Not a test parameter. Recommended for optimal performance.

VIDSAMP to Reset Separation t

(Note 2) 50 ns

REFERENCE VOLTAGE INPUT

POWER SUPPLIES

DIGITAL INPUTS/OUTPUTS

DIGITAL TIMING SPECIFICATIONS (t

, tf≤ 10ns, CL≤ 50pF, unless otherwise noted)

MAX1101

Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA

4 _______________________________________________________________________________________

______________________________________________________________Pin Description

NAME FUNCTION

1, 3, 5, 7,

10, 16, 24

GND Ground

2 CCDIN CCD Input. Connect CCD through a series 0.047µF capacitor (C

EXT

4 AIN1 Auxiliary Analog Input Channel 1 6 AIN2 Auxiliary Analog Input Channel 2

12 REF-

Lower Limit of Reference Span. Sets the zero-code voltage. Range is GND ≤ REF- ≤ REF+. Nominally 0.5V.

11 REFGND Reference Ground. Ground reference for all analog signals.

8, 9, 10 I.C. Internally Connected. Do not connect to this pin.

18 SCLK Serial Clock Input

17 MODE

Control Input. Set high, DATA is an output of the ADC. Set low, DATA enables programming of the PGA and mux.

15, 23 V

Power Supply, +5V. Bypass to ground very close to the device and connect the two pins together, close to the MAX1101.

14 REFBIAS Reference Power Supply. Connect to external +5.0V to set V

REF+

to +3.0V and V

REF-

to +0.5V.

13 REF+

Upper Limit of Reference Span. Sets the full-scale input. Voltage range is REF- ≤ REF+ ≤ VDD. Nominally 3.0V.

19 DATA Data Input or Output, as controlled by MODE 20 LOAD Control Input. Loads serial shift-register data to PGA and multiplexer registers when MODE = 0. 21 VIDSAMP Control Input. Samples the video level and initiates the ADC conversion. 22 CLAMP Control Input. Samples black level. Can be used for correlated double sampling.

_______________Detailed Description

Overview

The MAX1101 directly processes the pixel stream from a monochrome CCD, and removes black level, offset, and noise errors through an internal clamp circuit, which can be used as a correlated double sampler (CDS). It uses a 6-bit, programmable-gain amplifier (PGA) to adjust gain. A three-input multiplexer (mux) selects either the PGA output or two unassigned inputs (AIN1, AIN2). The processed analog signal is digitized by an 8-bit, half-flash analog-to-digital converter (ADC), and output serially through the DATA pin.

Digital data is input and output through the bidirectional serial pin (DATA) synchronously with the external serial clock (SCLK). When MODE = 0, the mux channels and the PGA gain can be programmed via DATA. With MODE = 1 (high), ADC serial data is output through this pin.

PGA

GAIN

CLAMP

CIRCUIT

MUX

ADC

6 2

2 1

SERIAL

PORT

DATA SCLK LOAD MODE

REFBIAS

REF+

REF-

REFGND

AIN2 AIN1

CLAMP

CCDIN

VIDSAMP

Figure 1. MAX1101 Functional Diagram

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