Maxim MAX1093AEEG, MAX1093ACEG, MAX1091BCEI, MAX1091AEEI, MAX1091ACEI Datasheet

...
General Description
The MAX1091/MAX1093 low-power, 10-bit analog-to­digital converters (ADCs) feature a successive-approxi­mation ADC, automatic power-down, fast wake-up (2µs), an on-chip clock, +2.5V internal reference, and a high-speed, byte-wide parallel interface. They operate with a single +3V analog supply and feature a V
pin that allows them to interface directly with a +1.8V to +3.6V digital supply.
Power consumption is only 5.7mW (V
DD
= V
LOGIC
) at the maximum sampling rate of 250ksps. Two software­selectable power-down modes enable the MAX1091/ MAX1093 to be shut down between conversions; accessing the parallel interface returns them to normal operation. Powering down between conversions can cut supply current to under 10µA at reduced sampling rates.
Both devices offer software-configurable analog inputs for unipolar/bipolar and single-ended/pseudo-differen­tial operation. In single-ended mode, the MAX1091 has eight input channels and the MAX1093 has four input channels (four and two input channels, respectively, when in pseudo-differential mode).
Excellent dynamic performance and low power com­bined with ease of use and small package size make these converters ideal for battery-powered and data­acquisition applications or for other circuits with demand­ing power consumption and space requirements.
The MAX1091 is available in a 28-pin QSOP package, while the MAX1093 is available in a 24-pin QSOP. For pin-compatible +5V, 10-bit versions, refer to the MAX1090/MAX1092 data sheet.
Applications
Industrial Control Systems Data Logging
Energy Management Patient Monitoring
Data-Acquisition Systems Touch Screens
Features
10-Bit Resolution, ±0.5LSB Linearity
+3V Single-Supply Operation
User-Adjustable Logic Level (+1.8V to +3.6V)
Internal +2.5V Reference
Software-Configurable, Analog Input Multiplexer
8-Channel Single-Ended/ 4-Channel Pseudo-Differential (MAX1091) 4-Channel Single-Ended/ 2-Channel Pseudo-Differential (MAX1093)
Software-Configurable, Unipolar/Bipolar Inputs
Low Power: 1.9mA (250ksps)
1.0mA (100ksps) 400µA (10ksps) 2µA (Shutdown)
Internal 3MHz Full-Power Bandwidth Track/Hold
Byte-Wide Parallel (8+2) Interface
Small Footprint: 28-Pin QSOP (MAX1091)
24-Pin QSOP (MAX1093)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
________________________________________________________________ Maxim Integrated Products 1
19-1638; Rev 0; 1/00
PART
MAX1091ACEI
0°C to +70°C
TEMP. RANGE
PIN-PACKAGE
28 QSOP
Ordering Information
Pin Configurations
±0.5
INL
(LSB)
MAX1091BCEI
0°C to +70°C
±128 QSOP
Ordering Information continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
Pin Configurations continued at end of data sheet.
EVALUATION KIT
AVAILABLE
MAX1091BEEI
MAX1091AEEI
-40°C to +85°C
±1
-40°C to +85°C
±0.528 QSOP
28 QSOP
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
TOP VIEW
HBEN
D1/D9
1
2
D7
3
D6
4
D5
5
D4
6
D3
7
D2
8
24
V
LOGIC
23
V
DD
22
REF
21
REFADJ
20
GND
MAX1093
19
COM
18
CH0
17
CH1
16
CH2
15
CH3
14
CS
13
CLKWR
9
D0/D8
10
INT
11
RD
12
QSOP
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= V
LOGIC
= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 4.8MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
V
LOGIC
to GND.........................................................-0.3V to +6V
CH0–CH7, COM to GND............................-0.3V to (V
DD
+ 0.3V)
REF, REFADJ to GND ................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to GND ...............................................-0.3V to +6V
Digital Outputs (D0–D9, INT) to GND.....-0.3V to (V
LOGIC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C) ...........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C) .........667mW
Operating Temperature Ranges
MAX1091_C_ _/MAX1093_C_ _...........................0°C to +70°C
MAX1091_E_ _/MAX1093_E_ _ ........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
External acquisition or external clock mode
Internal acquisition/internal clock mode
MAX109_A
External acquisition/internal clock mode
External clock mode
-3dB rolloff
SINAD > 56dB
fIN= 125kHz, VIN= 2.5Vp-p (Note 4)
f
IN1
= 49kHz, f
IN
2
= 52kHz
MAX109_B
No missing codes over temperature
CONDITIONS
ns50Aperture Delay
ns625t
ACQ
Track/Hold Acquisition Time
µs
3.2 3.6 4.1
2.5 3.0 3.5
3.3
t
CONV
Conversion Time (Note 5)
MHz
3
Full-Power Bandwidth
kHz
250
Full-Linear Bandwidth
dB
-78
Channel-to-Channel Crosstalk
dB
76
IMDIntermodulation Distortion
dB
72
SFDRSpurious-Free Dynamic Range
dB
-72
Total Harmonic Distortion (including 5th-order harmonic)
THD
±0.5
INLRelative Accuracy (Note 2)
Bits
10
RESResolution
dB60SINADSignal-to-Noise Plus Distortion
LSB±0.1
Channel-to-Channel Offset Matching
ppm/°C
±2.0
Gain Temperature Coefficient
LSB
±1
LSB
±1
DNLDifferential Nonlinearity
LSB
±2
Offset Error
LSB
±2
Gain Error (Note 3)
UNITSMIN TYP MAXSYMBOLPARAMETER
Internal acquisition/internal clock mode
External acquisition or external clock mode
<200
ps
<50
Aperture Jitter
MHz0.1 4.8f
CLK
External Clock Frequency
%30 70Duty Cycle
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (f
IN(sine wave)
= 50kHz, VIN= 2.5Vp-p, 250ksps, external f
CLK
= 4.8MHz, bipolar input mode)
CONVERSION RATE
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= V
LOGIC
= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 4.8MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
0 to 0.5mA output load
To power down the internal reference
For small adjustments
TA= 0°C to +70°C
On/off-leakage current, VIN= 0 or V
DD
Unipolar, V
COM
= 0
V
1.0
V
DD
+
50mV
V
REF
REF Input Voltage Range
µF
4.7 10
Capacitive Bypass at REF
µF
0.01 1
Capacitive Bypass at REFADJ
mV/mA
0.2 0.5
Load Regulation (Note 7)
V
VDD- 1.0
REFADJ High Threshold
mV
±100
REFADJ Input Range
±20
ppm/°CTC
REF
REF Temperature Coefficient
mA
15
REF Short-Circuit Current
V
2.49 2.5 2.51
REF Output Voltage
pF
12
C
IN
Input Capacitance
µA
±0.01 ±1
Multiplexer Leakage Current
V
Analog Input Voltage Range Single-Ended and Differential (Note 6)
0V
REF
V
IN
CS = V
DD
I
SOURCE
= 1mA
I
SINK
= 1.6mA
VIN= 0 or V
DD
V
LOGIC
= 2.7V
µA
±0.1 ±1
I
LEAKAGE
Three-State Leakage Current
V
V
LOGIC
- 0.5
V
OH
Output High Voltage
V
0.4
V
OL
Output Low Voltage
pF
15
C
IN
Input Capacitance
µA
±0.1 ±1
I
IN
Input Leakage Current
mV
200
V
HYS
Input Hysteresis
2.0
CS = V
DD
pF
15
C
OUT
Three-State Output Capacitance
Bipolar, V
COM
= V
REF
/2
-V
REF
/2 +V
REF
/2
V
REF
= 2.5V, f
SAMPLE
= 250ksps
µA
200 300
I
REF
REF Input Current
Shutdown mode
2
V
LOGIC
= 1.8V
V
1.5
V
IH
Input High Voltage
V
LOGIC
= 1.8V
V
0.5
V
IL
Input Low Voltage
V
LOGIC
= 2.7V
0.8
ANALOG INPUTS
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REF
DIGITAL INPUTS AND OUTPUTS
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD= V
LOGIC
= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 4.8MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
Shutdown mode
Standby mode
Operating mode, f
SAMPLE
= 250ksps
µA
210
0.9 1.2
mA
2.3 2.6
V
2.7 3.6
V
DD
Analog Supply Voltage
150
ELECTRICAL CHARACTERISTICS (continued)
(VDD= V
LOGIC
= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 4.8MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
V
LOGIC
Current I
LOGIC
CL= 20pF
210
µA
Power-Supply Rejection PSR VDD= 3V ±10%, full-scale input
±0.4 ±0.7
mV
f
SAMPLE
= 250ksps
Not converting
V
1.8 VDD+ 0.3
V
LOGIC
Digital Supply Voltage
WR to CLK Fall Setup Time
t
CWS
40
ns
nsCLK Pulse Width High
nsCLK Period
t
CH
40
t
CP
208
CLK Pulse Width Low t
CL
40
ns
Data Valid to WR Rise Time
t
DS
40
ns
WR Rise to Data Valid Hold Time
t
DH
0
ns
CLK Fall to WR Hold Time
t
CWH
40
ns
CS to CLK or WR Setup Time
t
CSWS
60
ns
CLK or WR to CS Hold Time
t
CSWH
0
ns
CS Pulse Width
t
CS
100
ns
WR Pulse Width (Note 8)
t
WR
60
ns
t
TC
20 100
nsC
LOAD
= 20pF, Figure 1
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
CS Rise to Output Disable
POWER REQUIREMENTS
Internal reference
Internal reference
External reference
External reference
1.9 2.3
0.5 0.8
I
DD
Positive Supply Current
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________ 5
Note 1: Tested at VDD= +3V, COM = GND, unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled. Note 4: On channel is grounded; sine wave applied to off channels. Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V
DD
.
Note 7: External load should not change during conversion for specified accuracy. Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS (continued)
(VDD= V
LOGIC
= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 4.8MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
t
TR
20 70
nsC
LOAD
= 20pF, Figure 1
RD Rise to Output Disable RD Fall to Output Data Valid
t
DO
20 70
ns
RD Fall to INT High Delay
t
INT1
100
ns
CS Fall to Output Data Valid
t
DO2
110
ns
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
HBEN to Output Data Valid t
DO1
20 110
nsC
LOAD
= 20pF, Figure 1
Figure 1. Load Circuits for Enable/Disable Times
DOUT
V
LOGIC
3k
C
3k
LOAD
20pF
DOUT
C
LOAD
20pF
a) HIGH-Z TO VOH AND VOL TO V
OH
b) HIGH-Z TO VOL AND VOH TO V
OL
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
6 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD= V
LOGIC
= +3V, V
REF
= +2.500V, f
CLK
= 4.8MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
-0.4
-0.2
-0.3
-0.1
0
0.1
0.2
0.3
0.4
0 400200 600 800 1000 1200
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1091/93 TOC01
OUTPUT CODE
INL (LSB)
-0.25
-0.10
-0.15
-0.20
-0.5
0
0.05
0.10
0.15
0.20
0.25
0 400200 600 800 1000 1200
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1091/93 TOC02
OUTPUT CODE
INL (LSB)
0.1 10k101 100 1k 100k 1M
SUPPLY CURRENT
vs. SAMPLE FREQUENCY
MAX1291/93 toc03
f
SAMPLE
(Hz)
I
DD
(µA)
1
10
100
1000
10,000
WITH INTERNAL REFERENCE
WITH EXTERNAL REFERENCE
1.80
1.90
1.85
2.00
1.95
2.05
2.10
2.7 3.0 3.3 3.6
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1291/93 toc04
VDD (V)
I
DD
(mA)
RL = CODE = 1010100000
1.6
1.8
1.7
2.0
1.9
2.1
2.2
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
MAX1291/3 toc05
TEMPERATURE (°C)
I
DD
(mA)
RL = CODE = 1010100000
880
890
910
900
920
930
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX1291/3 toc06
V
DD
(V)
STANDBY I
DD
(µA)
2.7 3.33.0 3.6
880
890
910
900
920
930
STANDBY CURRENT vs. TEMPERATURE
MAX1291/3 toc07
TEMPERATURE (°C)
STANDBY I
DD
(µA)
-40 10-15 35 8560
0.50
1.00
0.75
1.25
1.50
2.7 3.0 3.3 3.6
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1291/3 toc08
VDD (V)
POWER-DOWN I
DD
(µA)
0.8
0.9
1.0
1.1
1.2
POWER-DOWN CURRENT
vs. TEMPERATURE
MAX1291/3 toc09
TEMPERATURE (°C)
POWER-DOWN I
DD
(µA)
-40 35-15 10 60 85
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(VDD= V
LOGIC
= +3V, V
REF
= +2.500V, f
CLK
= 4.8MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
2.48
2.49
2.51
2.50
2.52
2.53
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1291/3 toc10
VDD (V)
V
REF
(V)
2.7 3.33.0 3.6
-140
-120
-100
-80
-60
-40
-20
0
20
0 400200 600 800 1000 1200
FFT PLOT
MAX1091/93 toc18
FREQUENCY (kHz)
AMPLITUDE (dB)
VDD = 3V f
IN
= 50kHz
f
SAMPLE
= 250ksps
1.0
0.5
0
OFFSET ERROR (LSB)
-0.5
OFFSET ERROR
vs. TEMPERATURE
OFFSET ERROR
vs. SUPPLY VOLTAGE
V
(V)
DD
GAIN ERROR vs. TEMPERATURE
2.53
2.52
2.51
(V)
REF
V
2.50
2.49
2.48
0.250
MAX1091/93 TOC13
-0.250
GAIN ERROR (LSB)
-0.500
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
-40 10-15 35 60 85 TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
0
MAX1291/3 toc11
OFFSET ERROR (LSB)
-0.5
-1.0
0.125
MAX1291/3 toc14
-0.125
-0.250
GAIN ERROR (LSB)
-0.375
1.0
0.5
0
2.7 3.33.0 3.6
0
MAX1091/93 TOC12
MAX1291/3 toc15
-1.0
-40 10-15 35 60 85 TEMPERATURE (°C)
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
250
200
(µA)
150
LOGIC
I
100
50
2.7 3.33.0 3.6
-0.750
2.7 3.33.0 3.6 VDD (V)
-0.500
-40 10-15 35 60 85
TEMPERATURE (°C)
LOGIC SUPPLY CURRENT
vs. TEMPERATURE
250
max1291/3 toc17
VDD (V)
MAX1291/3 toc16
(µA)
I
200
150
LOGIC
100
50
-40 10 35-15 60 85 TEMPERATURE (°C)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
8 _______________________________________________________________________________________
Pin Description
NAME
1 HBEN
High Byte Enable. Used to multiplex the 10-bit conversion result. 1: 2 MSBs are multiplexed on the data bus. 0: 8 LSBs are available on the data bus.
2 D7 Three-State Digital I/O Line (D7)
3 D6 Three-State Digital I/O Line (D6)
4 D5 Three-State Digital I/O Line (D5)
5 D4 Three-State Digital I/O Line (D4)
6 D3 Three-State Digital I/O Line (D3)
7 D2 Three-State Digital I/O Line (D2)
8 D1/D9 Three-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
9 D0/D8 Three-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
10
INT INT goes low when the conversion is complete and the output data is ready.
11
RD
Active-Low Read Select. If CS is low, a falling edge on RD will enable the read operation on the data bus.
12
WR
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. When CS is low in external acquisition mode, the first rising edge on WR ends acquisition and starts a conversion.
13 CLK
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode, connect this pin to either V
DD
or GND.
14
CS
Active-Low Chip Select. When CS is high, digital outputs (INT, D7–D0) are high imped­ance.
15 CH7 Analog Input Channel 7
16 CH6 Analog Input Channel 6
17 CH5 Analog Input Channel 5
18 CH4 Analog Input Channel 4
19 CH3 Analog Input Channel 3
20 CH2 Analog Input Channel 2
21 CH1 Analog Input Channel 1
22 CH0 Analog Input Channel 0
23 COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and must be stable to ±0.5LSB during conversion.
24 GND Analog and Digital Ground
25 REFADJ
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a
0.01µF capacitor. When using an external reference, connect REFADJ to V
DD
to disable
the internal bandgap reference.
26 REF
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to GND when using the internal reference.
27 V
DD
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.
28 V
LOGIC
Digital Power Supply. V
LOGIC
powers the digital outputs of the data converter and can
range from +1.8V to V
DD
+ 300mV.
1
2
PIN
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FUNCTION
MAX1091 MAX1093
Detailed Description
Converter Operation
The MAX1091/MAX1093 ADCs use a successive­approximation (SAR) conversion technique and an input track/hold (T/H) stage to convert an analog input signal to a 10-bit digital output. Their parallel 8+2 out­put format provides an easy interface to standard microprocessors (µPs). Figure 2 shows the simplified internal architecture of the MAX1091/MAX1093.
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog com­parator is illustrated in the equivalent input circuit in Figure 3. In single-ended mode, IN+ is internally switched to channels CH0–CH7 for the MAX1091 (Figure 3a) and to CH0–CH3 for the MAX1093 (Figure 3b), while IN- is switched to COM (Table 3).
In differential mode IN+ and IN- are selected from ana­log input pairs (Table 4) and are internally switched to either of the analog inputs. This configuration is pseu­do-differential in that only the signal at IN+ is sampled.
The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best performance) with respect to GND during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor C
HOLD
. At the end of the acquisition interval, the T/H switch opens, retaining charge on C
HOLD
as a sample of the
signal at IN+.
The conversion interval begins with the input multiplex­er switching C
HOLD
from the positive input (IN+) to the negative input (IN-). This unbalances node ZERO at the comparator’s positive input. The capacitive digital-to­analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 10-bit resolution. This action is equivalent to transferring a 12pF[(V
IN+
) - (V
IN-
)] charge from C
HOLD
to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal.
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________ 9
Figure 2. Simplified Internal Architecture for 8-/4-Channel MAX1091/MAX1093
REF REFADJ
(CH7) (CH6) (CH5) (CH4)
CH3 CH2 CH1 CH0
COM
CLK
CS
WR
RD
INT
( ) ARE FOR MAX1091 ONLY.
MULTIPLEXER
CLOCK
ANALOG
INPUT
T/H
CHARGE REDISTRIBUTION
MAX1091 MAX1093
CONTROL LOGIC
&
LATCHES
8
10-BIT DAC
10
SUCCESSIVE-
APPROXIMATION
REGISTER
2
2
MUX
8
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
D0–D7
8-BIT DATA BUS
AV =
2.05
8
8
17k
COMP
1.22V
REFERENCE
HBEN
V
DD
V
LOGIC
GND
MAX1091/MAX1093
Analog Input Protection
Internal protection diodes, which clamp the analog input to VDDand GND, allow each input channel to swing within (GND - 300mV) to (VDD+ 300mV) without damage. However, for accurate conversions near full scale, both inputs must not exceed (VDD+ 50mV) or be less than (GND - 50mV).
If an off-channel analog input voltage exceeds the supplies by more than 50mV, limit the forward-bias input current to 4mA.
Track/Hold
The MAX1091/MAX1093 T/H stage enters its tracking mode on the rising edge of WR. In external acquisition mode, the part enters its hold mode on the next rising edge of WR. In internal acquisition mode, the part enters its hold mode on the fourth falling edge of clock after writing the control byte. Note that in internal clock mode this occurs approximately 1µs after writing the control byte. In single-ended operation, IN- is connect­ed to COM and the converter samples the positive (+) input. In pseudo-differential operation, IN- connects to the negative input (-), and the difference of (IN+) - (IN-) is sampled. At the beginning of the next conversion, the positive input connects back to IN+ and C
HOLD
charges to the input signal.
The time required for the T/H stage to acquire an input signal depends on how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, t
ACQ
, is the maximum time the device takes to acquire the signal and is also the minimum time required for the signal to be acquired. Calculate this with the following equation:
t
ACQ
= 7 (RS+ RIN) C
IN
where RSis the source impedance of the input signal, RIN(800) is the input resistance, and CIN(12pF) is the ADC’s input capacitance. Source impedances below 3khave no significant impact on the MAX1091/ MAX1093’s AC performance.
Higher source impedances can be used if a 0.01µF capacitor is connected to the individual analog inputs. Together with the input impedance, this capacitor forms an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX1091/MAX1093 T/H stage offers a 250kHz full­linear and a 3MHz full-power bandwidth, enabling these parts to use undersampling techniques to digitize high-speed transients and measure periodic signals with bandwidths exceeding the ADCs sampling rate. To avoid high-frequency signals being aliased into the fre­quency band of interest, anti-alias filtering is recom­mended.
Starting a Conversion
Initiate a conversion by writing a control byte that selects the multiplexer channel and configures the MAX1091/MAX1093 for either unipolar or bipolar opera­tion. A write pulse (WR + CS) can either start an acqui­sition interval or initiate a combined acquisition plus
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
10 ______________________________________________________________________________________
Figure 3a. MAX1091 Simplified Input Structure
Figure 3b. MAX1093 Simplified Input Structure
10-BIT CAPACITIVE DAC
REF
INPUT
C
C
SWITCH
C
SWITCH
C
HOLD
12pF
TRACK
HOLD
12pF
TRACK
+
SWITCH
+
T/H
SWITCH
R 800
T/H
IN
R
IN
800
ZERO
HOLD
ZERO
HOLD
CH0
CH1 CH2
CH3 CH4
CH5 CH6 CH7
COM
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
CH0
CH1
CH2
CH3
COM
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1 AND CH2/CH3
MUX
10-BIT CAPACITIVE DAC
REF
INPUT
MUX
COMPARATOR
AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
COMPARATOR
AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD (acquisition mode) bit in the input control byte (Table 1) offers two options for acquiring the signal: an internal and an external acquisition. The conversion period lasts for 13 clock cycles in either the internal or external clock or acquisition mode. Writing a new control byte during a conversion cycle will abort the conversion and start a new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this acquisition interval ends (three external cycles or approximately 1µs in internal clock mode) (Figure 4). Note that when the internal acquisition is combined with the internal clock, the aperture jitter can be as high as 200ps. Internal clock users wishing to achieve the 50ps jitter specification should always use external acquisition mode.
External Acquisition
Use external acquisition mode for precise control of the sampling aperture and/or dependent control of acquisi­tion and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0, terminates acquisition and starts conversion on WR’s rising edge (Figure 5).
The address bits for the input multiplexer must have the same values on the first and second write pulse. Power-down mode bits (PD0, PD1) can assume new values on the second write pulse (see the Power-Down Modes section). Changing other bits in the control byte will corrupt the conversion.
Reading a Conversion
A standard interrupt signal INT is provided to allow the MAX1091/MAX1093 to flag the µP when the conversion has ended and a valid result is available. INT goes low when the conversion is complete and the output data is ready (Figures 4 and 5). It returns high on the first read cycle or if a new control byte is written.
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________ 11
Table 1. Control Byte Functional Description
ACQMOD = 0: Internal Acquisition Mode ACQMOD = 1: External Acquisition Mode
ACQMODD5
Full Power-Down Mode. Clock mode is unaffected.
PD1 and PD0 select the various clock and power-down modes.
D7, D6
0
PD1, PD0
BIT
Normal Operation Mode. Internal clock mode selected.
Address bits A2–A0 select which of the 8/4 (MAX1091/MAX1093) channels are to be converted (see Tables 3 and 4).
A2, A1, A0
1
Normal Operation Mode. External clock mode selected.
D2, D1, D0
UNI/BIP = 0: Bipolar Mode UNI/BIP = 1: Unipolar Mode In unipolar mode, an analog input signal from 0 to V
REF
can be converted; in bipolar mode, the sig-
nal can range from -V
REF
/2 to +V
REF
/2.
1 1
0
Standby Power-Down Mode. Clock mode is unaffected.
UNI/BIP
D3
0 1
SGL/DIF = 0: Pseudo-Differential Analog Input Mode SGL/DIF = 1: Single-Ended Analog Input Mode In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage difference between two channels is measured (see Tables 2 and 3).
SGL/DIF
0
D4
FUNCTIONNAME
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
12 ______________________________________________________________________________________
Figure 4. Conversion Timing Using Internal Acquisition Mode
Figure 5. Conversion Timing Using External Acquisition Mode
t
CS
CS
WR
D7–D0
INT
RD
HBEN
t
CSWS
t
WR
t
DS
t
ACQ
CONTROL
BYTE
ACQMOD = "0"
t
t
CSWH
DH
DOUT
CS
t
CSWS
WR
D7–D0
t
CS
t
WR
t
DS
ACQMOD = "1"
CONTROL
BYTE
t
CSHW
t
DH
t
ACQ
t
CONV
CONTROL
BYTE
ACQMOD = "0"
t
CONV
t
INT1
t
D0
HIGH / LOW BYTE VALID
t
D01
HIGH / LOW BYTE VALID
t
INT1
t
TR
HIGH-ZHIGH-Z
INT
RD
HBEN
t
HIGH / LOW BYTE VALID
D01
HIGH / LOW BYTE VALID
DOUT
HIGH-Z
t
D0
t
TR
HIGH-Z
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________ 13
Selecting Clock Mode
The MAX1091/MAX1093 operate with either an internal or an external clock. Control bits D6 and D7 select either internal or external clock mode. The parts retain the last requested clock mode if a power-down mode is selected in the current input word. For both internal and external clock modes, internal or external acquisition can be used. At power-up, the MAX1091/MAX1093 enter the default external clock mode.
Internal Clock Mode
Select internal clock mode to release the µP from the burden of running the SAR conversion clock. To select this mode, bit D7 of the control byte must be set to 1 and D6 must be set to 0; the internal clock frequency is then selected, resulting in a conversion time of 3.6µs. When using the internal clock mode, tie the CLK pin either high or low to prevent the pin from floating.
External Clock Mode
To select the external clock mode, bits D6 and D7 of the control byte must be set to one. Figure 6 shows the clock and WR timing relationship for internal (Figure 6a) and external (Figure 6b) acquisition modes with an external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is recommended. Operating the MAX1091/MAX1093 with clock frequencies lower than 100kHz is not recom­mended because it will cause a voltage droop across
the hold capacitor in the T/H stage that will result in degraded performance.
Digital Interface
Input (control byte) and output data are multiplexed on a three-state parallel interface. This parallel interface (I/O) can easily be interfaced with standard µPs. The signals CS, WR, and RD control the write and read operations. CS represents the chip select signal, which enables a µP to address the MAX1091/MAX1093 as an I/O port. When high, CS disables the CLK WR and RD inputs and forces the interface into a high-impedance (high-Z) state.
Input Format
The control byte is latched into the device on pins D7–D0 during a write command. Table 2 shows the control byte format.
Output Format
The output format for both the MAX1091/MAX1093 is binary in unipolar mode and two’s complement in bipo­lar mode. When reading the output data, CS and RD must be low. When HBEN = 0, the lower 8 bits are read. With HBEN = 1, the upper 2 bits are available and the output data bits D7–D2 are set either low in unipolar mode or set to the value of the MSB in bipolar mode (Table 5).
Figure 6a. External Clock and WRTiming (Internal Acquisition Mode)
ACQUISITION STARTS
CLK
WR
ACQMOD = "0"
t
CWH
CLK
WR
ACQMOD = "0"
ACQUISITION STARTS
t
CWS
t
CP
t
CH
ACQUISITION ENDS
t
CL
WR GOES HIGH WHEN CLK IS HIGH.
ACQUISITION ENDS
WR GOES HIGH WHEN CLK IS LOW.
CONVERSION STARTS
CONVERSION STARTS
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
14 ______________________________________________________________________________________
Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
*Channels CH4–CH7 apply to MAX1091 only.
A1 CH0
0 +00
A0
0 1
CH2 CH4*
+0
1 0 +
CH3
-
0
CH1 CH7*
-
CH6*
-
COM
1
CH5*
1 + -0
0 0
A2
+1
0 1 +1
-
-
1 01
1 1
+
1
-
+ -
Figure 6b. External Clock and WRTiming (External Acquisition Mode)
Table 2. Control Byte Format
D7 (MSB) D3 D1 D0 (LSB)D2D5
PD1
UNI/BIP
A1 A0A2ACQMOD
SGL/DIF
PD0
D4D6
ACQUISITION STARTS
CLK
t
DH
WR
WR GOES HIGH WHEN CLK IS HIGH.
WR GOES HIGH WHEN CLK IS LOW.
CLK
WR
ACQMOD = "1"
ACQMOD = "1"
ACQUISITION STARTS
t
DH
ACQUISITION ENDS
ACQUISITION ENDS
t
CWH
ACQMOD = "0"
t
CWS
ACQMOD = "0"
CONVERSION STARTS
CONVERSION STARTS
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________ 15
Table 4. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
*Channels CH4–CH7 apply to MAX1091 only.
A1 CH0
0 +0 -0
A0
0 -1
CH2 CH4*
+0
1 0 + -
CH3
0
CH1 CH7*CH6*
1
CH5*
1 - +0
0 0
A2
+ -1
0 1 - +1
1 0 -1
1 1
+
1 +-
Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir­cuitry activates the MAX1091/MAX1093 in external clock mode and sets INT high. After the power supplies stabilize, the internal reset time is 10µs, and no conver­sions should be attempted during this phase. When using the internal reference, 500µs is required for V
REF
to stabilize.
Internal and External Reference
The MAX1091/MAX1093 can be used with an internal or external reference voltage. An external reference can be connected directly to REF or REFADJ.
An internal buffer is designed to provide +2.5V at REF for the both the MAX1091 and the MAX1093. The internally trimmed +1.22V reference is buffered with a +2.05V/V gain.
Internal Reference
With the internal reference, the full-scale range is +2.5V with unipolar inputs and ±1.25V with bipolar inputs. The internal reference buffer allows for small adjustments (±100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with an external capacitor (4.7µF min) connected between REF and GND to reduce reference noise and switching spikes from the ADC. To further minimize noise on the reference, connect a 0.01µF capacitor between REFADJ and GND.
External Reference
With both the MAX1091 and MAX1093, an external ref­erence can be placed at either the input (REFADJ) or the output (REF) of the internal reference buffer amplifier.
Using the REFADJ input makes buffering the external reference unnecessary. The REFADJ input impedance is typically 17k.
Table 5. Data-Bus Output (8+2 Parallel Interface)
UNIPOLAR
(UNI/BIP = 1)
BIPOLAR
(UNI/BIP = 0)
0
0
0
D6
D7 Bit 9Bit 7
Bit 9Bit 6
D2 Bit 9Bit 2
D1 Bit 9 (MSB)Bit 1
HBEN = 1
Bit 8
HBEN = 0
Bit 0 (LSB)
PIN
D0
Figure 7. Reference Voltage Adjustment with External Potentiometer
0D3 Bit 9Bit 3
0D4 Bit 9Bit 4
0D5 Bit 9Bit 5
VDD = +3V
50k
MAX1091
50k
GND
330k
0.01µF
GND
4.7µF
MAX1093
REFADJ
REF
MAX1091/MAX1093
When applying an external reference to REF, disable the internal reference buffer by connecting REFADJ to VDD. The DC input resistance at REF is 25kΩ. Therefore, an external reference at REF must deliver up to 200µA DC load current during a conversion and have an output impedance less than 10. If the refer­ence has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor.
Power-Down Modes
Save power by placing the converter in a low-current shutdown state between conversions. Select standby mode or shutdown mode via bits D6 and D7 of the con­trol byte (Tables 1 and 2). In both software power-down modes, the parallel interface remains active, but the ADC does not convert.
Standby Mode
While in standby mode, the supply current is 850µA (typ). The part will power up on the next rising edge on WR and is ready to perform conversions. This quick turn-on time allows the user to realize significantly reduced power consumption for conversion rates below 250ksps.
Shutdown Mode
Shutdown mode turns off all chip functions that draw qui­escent current, reducing the typical supply current to 2µA immediately after the current conversion is complet-
ed. A rising edge on WR causes the MAX1091/MAX1093 to exit shutdown mode and return to normal operation. To achieve full 10-bit accuracy with a 4.7µF reference bypass capacitor, 500µs is required after power-up. Waiting this 500µs in standby mode instead of in full­power mode can reduce power consumption by a factor of 3 or more. When using an external reference, only 50µs is required after power-up. Enter standby mode by performing a dummy conversion with the control byte specifying standby mode.
Note: Bypassing capacitors larger than 4.7µF between REF and GND will result in longer power-up delays.
Transfer Function
Table 6 shows the full-scale voltage ranges for unipolar and bipolar modes.
Figure 8 depicts the nominal, unipolar input/output (I/O) transfer function and Figure 9 shows the bipolar I/O transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = V
REF
/ 1024.
Maximum Sampling Rate/
Achieving 300ksps
When running at the maximum clock frequency of
4.8MHz, the specified throughput of 250ksps is achieved by completing a conversion every 19 clock cycles: 1 write cycle, 3 acquisition cycles, 13 conver-
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
16 ______________________________________________________________________________________
Figure 8. Unipolar Transfer Function
Figure 9. Bipolar Transfer Function
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
*COM V
OUTPUT CODE
FS
ZS = COM
-FS = + COM
1LSB =
- FS
/2
REF
REF
+ COM
=
2
-REF 2
REF
1024
COM*
INPUT VOLTAGE (LSB)
OUTPUT CODE
111 . . . 111
111 . . . 110
100 . . . 010
100 . . . 001
100 . . . 000
011 . . . 111
011 . . . 110
011 . . . 101
000 . . . 001
000 . . . 000
FS = REF + COM
ZS = COM
1LSB =
102
(COM)
REF 1024
INPUT VOLTAGE (LSB)
FULL-SCALE TRANSITION
FS -
3
/2LSB
FS512
+FS - 1LSB
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________ 17
Table 6. Full-Scale and Zero-Scale for Unipolar and Bipolar Operation
UNIPOLAR MODE BIPOLAR MODE
COM COMZero ScaleZero Scale
-V
REF
/2 + COM Negative Full Scale
V
REF
+ COM V
REF
/2 + COMPositive Full ScaleFull Scale
sion cycles, and 2 read cycles. This assumes that the results of the last conversion are read before the next control byte is written. Throughputs up to 300ksps can be achieved by first writing a control word to begin the acquisition cycle of the next conversion, and then read­ing the results of the previous conversion from the bus (Figure 10). This technique allows a conversion to be completed every 16 clock cycles. Note that the switch­ing of the data bus during acquisition or conversion can cause additional supply noise, which may make it difficult to achieve true 10-bit performance.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and don’t lay out digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only one star point (Figure 11) connecting the two ground systems (analog and digital). For lowest-noise opera­tion, ensure the ground return to the star ground’s power supply is low impedance and as short as possi­ble. Route digital signals far away from sensitive analog and reference inputs.
High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC’s fast com­parator. Bypass VDDto the star ground with a network of two parallel capacitors, 0.1µF and 4.7µF, located as close as possible to the MAX1091/MAX1093s’ power supply pin. Minimize capacitor lead length for best sup­ply-noise rejection; add an attenuation resistor (5) if the power supply is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1091/MAX1093 are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture delay (tAD) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full­scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR = (6.02 · N + 1.76)dB
In reality, there are other noise sources besides quanti­zation noise: thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to RMS equivalent of all other ADC output signals:
SINAD (dB) = 20 · log (Signal
RMS
/ Noise
RMS
)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quanti­zation noise only. With an input range equal to the full­scale range of the ADC, calculate the effective number of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through V5are the amplitudes of the 2nd- through 5th-order har­monics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next-largest distortion component.
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
18 ______________________________________________________________________________________
Figure 11. Power-Supply and Grounding Connections
Figure 10. Timing Diagram for Fastest Conversion
Chip Information
TRANSISTOR COUNT: 5781
123 456 78910111213141516
CLK
WR
RD
HBEN
D7–D0
STATE
CONTROL
BYTE
D7–D0 D9–D8
LOW
HIGH
BYTE
BYTE
ACQUISITION
SAMPLING INSTANT
THD 20 log V V V V / V
=+++
2
2
2
3
2
4
5
2
SUPPLIES
D7–D0 D9–D8
HIGH
LOW
BYTE
BYTE
ACQUISITION
V
= +2V/+3V
LOGIC
GND
DGND+2V/+3VCOM
DIGITAL
CIRCUITRY
CONTROL BYTE
CONVERSION
1
R* = 5
+3V
V
DD
*OPTIONAL
4.7µF
0.1µF
GND
MAX1091 MAX1093
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________ 19
Typical Operating Circuits
Pin Configurations (continued)
PART TEMP. RANGE PIN-PACKAGE
INL
(LSB)
MAX1093ACEG
0°C to +70°C ±0.524 QSOP
MAX1093BEEG
MAX1093AEEG
-40°C to +85°C ±1
-40°C to +85°C ±0.524 QSOP
24 QSOP
Ordering Information (continued)
MAX1093BCEG 0°C to +70°C ±124 QSOP
µP
CONTROL
INPUTS
µP DATA BUS
CLK
CS
WR
RD
HBEN
D7
D6
D5
D4
D3
D2
D1/D9
D0/D8
MAX1091
V
LOGIC
V
REF
REFADJ
INT
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
COM
GND
+1.8V TO +3.6V
ANALOG
INPUTS
+3V
+2.5V
4.7µF
µP
CONTROL
INPUTS
µP DATA BUS
DD
0.1µF
OUTPUT STATUS
CLK
CS
WR
RD
HBEN
D7
D6
D5
D4
D3
D2
D1/D9
D0/D8
MAX1093
V
LOGIC
V
REF
REFADJ
CH3
CH2
CH1
CH0
COM
GND
DD
INT
+1.8V TO +3.6V
0.1µF
OUTPUT STATUS
+3V
+2.5V
4.7µF
ANALOG
INPUTS
TOP VIEW
1
HBEN
2
D7
3
D6
4
D5
5
D4
D3
D2
D1/D9
D0/D8
INT
RD
WR
MAX1091
6
7
8
9
10
11
12
13
QSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
1514 CH7CS
V
LOGIC
V
DD
REF
REFADJ
GND
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6CLK
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
QSOP.EPS
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