Maxim MAX106CHC Datasheet

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone].

General Description

The MAX106 PECL-compatible, 600Msps, 8-bit analog-to­digital converter (ADC) allows accurate digitizing of ana­log signals with bandwidths to 2.2GHz. Fabricated on
Maxim’s proprietary advanced GST-2 bipolar process, the
MAX106 integrates a high-performance track/hold (T/H)
amplifier and a quantizer on a single monolithic die.

The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high, 7.6 effective bits performance at the
Nyquist frequency. A fully differential comparator design
and decoding circuitry combine to reduce out-of­sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance of
one error per 1027clock cycles. Unlike other ADCs, which
can have errors that result in false full- or zero-scale out­puts, the MAX106 limits the error magnitude to 1LSB.

The analog input is designed for either differential or sin­gle-ended use with a ±250mV input voltage range. Dual,
differential, PECL-compatible output data paths ensure
easy interfacing and include an 8:16 demultiplexer feature
that reduces output data rates to one-half the sampling
clock rate. The PECL outputs can be operated from any
supply between +3V to +5V for compatibility with +3.3V or
+5V referenced systems. Control inputs are provided for
interleaving additional MAX106 devices to increase the
effective system sampling rate.

The MAX106 is packaged in a 25mm x 25mm, 192-con­tact Enhanced Super-Ball-Grid Array (ESBGA™), and is
specified over the commercial (0°C to +70°C) temperature
range. For a pin-compatible higher speed upgrade, refer
to the MAX104 (1Gsps) and MAX108 (1.5Gsps) data
sheets.

Applications

Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/ECM Systems
ATE Systems

Features

♦ 600Msps Conversion Rate
♦ 2.2GHz Full-Power Analog Input Bandwidth
♦ 7.6 Effective Bits at f

IN

= 300MHz

(Nyquist frequency)

♦ ±0.25LSB INL and DNL
♦ 50Ω Differential Analog Inputs
♦ ±250mV Input Signal Range
♦ On-Chip, +2.5V Precision Bandgap Voltage

Reference

♦ Latched, Differential PECL Digital Outputs
♦ Low Error Rate: 10

-27

Metastable States

♦ Selectable 8:16 Demultiplexer
♦ Internal Demux Reset Input with Reset Output
♦ 192-Contact ESBGA
♦ Pin Compatible with Faster MAX104/MAX108

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

________________________________________________________________

Maxim Integrated Products

1

19-1486; Rev 0; 7/99

PART

MAX106CHC 0°C to +70°C

TEMP. RANGE PIN-PACKAGE

192 ESBGA

Typical Operating Circuit appears at end of data sheet.

Ordering Information

ESBGA

TOP VIEW

MAX106

192-Contact ESBGA

Ball Assignment Matrix

ESBGA is a trademark of Amkor/Anam.

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCA to GNDA .........................................................-0.3V to +6V

VCCD to GNDD.........................................................-0.3V to +6V

VCCI to GNDI............................................................-0.3V to +6V

VCCO to GNDD........................................-0.3V to (VCCD + 0.3V)

AUXEN1, AUXEN2 to GND .....................-0.3V to (VCCD + 0.3V)

VEEto GNDI..............................................................-6V to +0.3V

Between GNDs......................................................-0.3V to +0.3V

VCCA to VCCD .......................................................-0.3V to +0.3V

VCCA to VCCI.........................................................-0.3V to +0.3V

PECL Digital Output Current...............................................50mA

REFIN to GNDR ........................................-0.3V to (VCCI + 0.3V)

REFOUT Current ................................................+100µA to -5mA

ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V

TTL/CMOS Control Inputs

(DEMUXEN, DIVSELECT) ....................-0.3V to (VCCD + 0.3V)

RSTIN+, RSTIN- ......................................-0.3V to (VCCO + 0.3V)

VOSADJ Adjust Input ................................-0.3V to (VCCI + 0.3V)

CLK+ to CLK- Voltage Difference..........................................±3V

CLK+, CLK-.....................................(VEE- 0.3V) to (GNDD + 1V)

CLKCOM.........................................(VEE- 0.3V) to (GNDD + 1V)

VIN+ to VIN- Voltage Difference............................................±2V

VIN+, VIN- to GNDI................................................................±2V

Continuous Power Dissipation (TA= +70°C)

192-Contact ESBGA (derate 61mW/°C above +70°C) ...4.88W
(with heatsink and 200LFM airflow,

derate 106mW/°C above +70°C) ....................................8.48W

Operating Temperature Range

MAX106CHC........................................................0°C to +70°C

Operating Junction Temperature.....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

TA= +25° C

Referenced to GNDR

0 < I

SOURCE

< 2.5mA

Driving REFIN input only

VIN+ and VIN- to GNDI, TA= +25°C

VOSADJ = 0 to 2.5V

Signal + offset w.r.t. GNDI

TA= +25° C
No missing codes guaranteed

CONDITIONS

kΩ

45

R

REF

Reference Input Resistance

mV5∆REFOUT

Reference Output Load
Regulation

V

2.475 2.50 2.525

REFOUTReference Output Voltage

LSB

±4 ±5.5

Input VOSAdjust Range

kΩ

14 25

R

VOS

Input Resistance (Note 2)

ppm/°C

150

TC

R

Input Resistance Temperature
Coefficient

LSB

-0.5 ±0.25 0.5

INLIntegral Nonlinearity (Note 1)

Bits

8

RESResolution

Ω

49 50 51

R

IN

Input Resistance

V

±0.8

V

CM

Common-Mode Input Range

mVp-p

475 500 525

V

FSR

Full-Scale Input Range (Note 1)

LSB

-0.5 ±0.25 0.5

DNLDifferential Nonlinearity (Note 1)

CodesNoneMissing Codes

UNITSMIN TYP MAXSYMBOLPARAMETER

ACCURACY

ANALOG INPUTS

VOSADJUST CONTROL INPUT

REFERENCE INPUT AND OUTPUT

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.)

CLK+ and CLK- to CLKCOM, TA= +25°C

CONDITIONS

ppm/°C

150

TC

R

Input Resistance Temperature
Coefficient

Ω

48 50 52

R

CLK

Clock Input Resistance

UNITSMIN TYP MAXSYMBOLPARAMETER

(Note 10)

(Note 9)

VIN+ = VIN- = ±0.1V

VIH= 2.4V
VIL= 0

dB

40 68

PSRR-

Negative Power-Supply
Rejection Ratio (Note 8)

dB

40 73

PSRR+

Positive Power-Supply Rejection
Ratio (Note 8)

dB

40 68

CMRR

Common-Mode Rejection Ratio
(Note 7)

W

5.25

P

DISS

Power Dissipation (Note 6)

Output Supply Current (Note 6) mA

75 115

ICCO

mA

205 340

ICCDDigital Supply Current

mA

-290 -210

I

EE

Negative Input Supply Current

mA

108 150

I

CCI

Positive Input Supply Current

mA

480 780

I

CCA

Positive Analog Supply Current

V0.8V

IL

Low-Level Input Voltage

V

2.0

V

IH

High-Level Input Voltage

V

-1.810 -1.620

V

OL

Digital Output Low Voltage

V

-1.025 -0.880

V

OH

Digital Output High Voltage

V-1.475V

IL

Digital Input Low Voltage

µA

50

I

IH

High-Level Input Current

µA

-1 1

I

IL

Low-Level Input Current

V

-1.165

V

IH

Digital Input High Voltage

CLOCK INPUTS (Note 3)

TTL/CMOS CONTROL INPUTS (DEMUXEN, DIVSELECT)

DEMUX RESET INPUT (Note 4)

PECL DIGITAL OUTPUTS (Note 5)

POWER REQUIREMENTS

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

4 _______________________________________________________________________________________

fIN= 600MHz

fIN= 500MHz

fIN= 125MHz

fIN= 300MHz

fIN= 600MHz

fIN= 600MHz

fIN= 125MHz

fIN= 300MHz

fIN= 125MHz

fIN= 300MHz

CONDITIONS

56.7

dB

57.4

SFDR

600

Spurious-Free Dynamic
Range

-67.5

-63.0 -67.5

THD

125

-56.5

-52.0 -56.5

THD

300

-56.1

dB

-57.0

THD

600

Total Harmonic Distortion
(Note 12)

47.4

44.2 47.4

SNR

125

47.1

43.8 47.1

SNR

300

46.8

V/V1.1:1VSWRAnalog Input VSWR

GHz2.2BW

-3dB

Analog Input Full-Power
Bandwidth

dB

46.8

SNR

600

Signal-to-Noise Ratio
(No Harmonics)

7.74

7.4 7.74

ENOB

125

7.65

Bits

7.63

ENOB

600

7.62

7.3 7.65

ENOB

300

Effective Number of Bits
(Note 11)

UNITS

MIN TYP MAX

SYMBOLPARAMETER

fIN= 125MHz

fIN= 300MHz

f

IN

1

= 124MHz, f

IN2

= 126MHz,

at -7dB below full scale

fIN= 125MHz

fIN= 300MHz

63.0 69.9

SFDR

125

57.4

52.0 57.5

SFDR

300

dB-61.8IMDTwo-Tone Intermodulation

48.4

46.3 48.4

SINAD

125

47.8

69.9

dB

47.7

SINAD

600

Signal-to-Noise Ratio and
Distortion (Note 11)

47.6

45.7 47.8

SINAD

300

fIN= 600MHz

Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended

fIN= 600Hz

Differential
Single-ended
Differential
Single-ended
Differential
Single-ended

AC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)

VOSADJ control input open LSB-1.5 0 1.5V

OS

Transfer Curve Offset

ANALOG INPUT

DYNAMIC SPECIFICATIONS

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

_______________________________________________________________________________________ 5

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

20% to 80%, CL= 3pF

20% to 80%, CL= 3pF

20% to 80%, CL= 3pF

Figure 17

Figure 17

Figure 15

Figure 15

Figure 4

Figure 17

ps220t

RDREADY

DREADY Rise Time

ps360t

FDATA

DATA Fall Time

ps420t

RDATA

DATA Rise Time

ps-50 150 350t

PD2

DREADY to DATA Propagation
Delay (Note 14)

ns2.2t

PD1

CLK to DREADY Propagation
Delay

ps0t

HD

Reset Input Data Hold Time
(Note 13)

ps0t

SU

Reset Input Data Setup Time
(Note 13)

ps< 0.5t

AJ

Aperture Jitter

ps100t

AD

Aperture Delay

DIV1, DIV2 modes

DIV1, DIV2 modes

20% to 80%, CL= 3pF

9.5

Clock

Cycles

8.5

t

PDA

Auxiliary Port Pipeline Delay

Clock

Cycles

7.5

t

PDP

Primary Port Pipeline Delay

ps180t

FDREADY

DREADY Fall Time

AC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)

Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale

range (FSR) is defined as 256

· slope of the line.

Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit

voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.

Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings on

the CLK+ and CLK- inputs.

Note 4: Input logic levels are measured with respect to the V

CC

O power-supply voltage.

Note 5: All PECL digital outputs are loaded with 50Ω to V

CC

O - 2.0V. Measurements are made with respect to the VCCO power-

supply voltage.

Note 6: The current in the V

CC

O power supply does not include the current in the digital output’s emitter followers, which is a func-

tion of the load resistance and the V

TT

termination voltage.

Note 7: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the

common-mode voltage, expressed in dB.

Note 8: Measured with the positive supplies tied to the same potential, V

CC

A = VCCD = VCCI. VCCvaries from +4.75V to +5.25V.

Note 9: V

EE

varies from -5.25V to -4.75V.

Note 10: Power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power

supply voltage, expressed in dB.

Note 11: Effective number of bits (ENOB) and signal-to-noise plus distortion (SINAD) are computed from a curve fit referenced to the

theoretical full-scale range.

7.5

Msps600f

MAX

Maximum Sample Rate

Figure 17 ns0.75t

PLW

Clock Pulse WidthLow

Figure 17 ns0.75 5t

PWH

Clock Pulse Width High

TIMING CHARACTERISTICS

Figures 6, 7, 8

Figures 6, 7, 8

DIV4 mode

DIV4 mode

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

6 _______________________________________________________________________________________

Typical Operating Characteristics

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other­wise noted.)

8.00

10 100 1000

EFFECTIVE NUMBER OF BITS vs.

ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

MAX106 toc01

ANALOG INPUT FREQUENCY (MHz)

ENOB (Bits)

6.75

6.50

7.25

7.50

7.00

7.75

-6dBFS

-1dBFS

-12dBFS

8.00

10 100 1000

EFFECTIVE NUMBER OF BITS vs.

ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

MAX106 toc02

ANALOG INPUT FREQUENCY (MHz)

ENOB (Bits)

6.75

6.50

7.25

7.50

7.00

7.75

-6dBFS

-1dBFS

-12dBFS

50

10 100 1000

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

MAX106 toc03

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

47

48

46

49

-1dBFS

-12dBFS

-6dBFS

50

10 100 1000

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

MAX106 toc04

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

47

48

46

49

-1dBFS

-12dBFS

-6dBFS

50

10 100 1000

SIGNAL-TO-NOISE RATIO vs.

ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

MAX106 toc05

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

30

38

42

34

46

-1dBFS

-12dBFS

-6dBFS

50

10 100 1000

SIGNAL-TO-NOISE RATIO vs.

ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

MAX106 toc06

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

30

38

42

34

46

-6dBFS

-1dBFS

-12dBFS

Note 12: Total harmonic distortion (THD) is computed from the first five harmonics.
Note 13: Guaranteed by design with a reset pulse width of one clock period or longer.
Note 14: The DREADY to DATA propagation delay is measured from the 50% point on the rising edge of the DREADY signal (when

the output data changes) to the 50% point on a data output bit. This places the falling edge of the DREADY signal in the
middle of the data output valid window, within the differences between the DREADY and DATA rise and fall times, which
gives maximum setup and hold time for latching external data latches.

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

_______________________________________________________________________________________

7

75

10 100 1000

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

MAX106 toc10

ANALOG INPUT FREQUENCY (MHz)

SFDR (dB)

50

60

65

55

70

-12dBFS

-6dBFS

-1dBFS

8.00

100 600

EFFECTIVE NUMBER OF BITS vs.

CLOCK FREQUENCY

MAX106 toc11

CLOCK FREQUENCY (MHz)

ENOB (Bits)

6.75

6.50

7.25

7.50

7.00

7.75

fIN = 125MHz, -1dBFS

6.50

7.00

6.75

7.50

7.25

7.75

8.00

-12 -8 -6 -4-10 -20246810

EFFECTIVE NUMBER OF BITS

vs. CLOCK POWER

MAX106toc12

CLOCK POWER PER SIDE (dBm)

ENOB (Bits)

SINGLE-ENDED CLOCK DRIVE

DIFFERENTIAL CLOCK DRIVE

f

IN

= 125MHz, -1dBFS

6.50

7.00

6.75

7.50

7.25

7.75

8.00

4.50 5.304.70 5.504.90 5.10

EFFECTIVE NUMBER OF BITS vs.

V

CC

I = VCCA = VCCD

MAX106toc13

VCC (V)

ENOB (Bits)

f

IN

= 125MHz, -1dBFS

65

67

66

70

69

68

71

72

74

73

75

SPURIOUS-FREE DYNAMIC RANGE

vs. V

CC

I = VCCA = VCCD

MAX106 toc16

V

CC

(V)

SFDR (dB)

4.50 5.304.70 5.504.90 5.10

fIN = 125MHz, -1dBFS

6.50

7.00

6.75

7.50

7.25

7.75

8.00

-4.50-5.30 -4.70-5.50 -4.90-5.10

EFFECTIVE NUMBER OF BITS vs. V

EE

MAX106toc14

VEE (V)

ENOB (Bits)

55

59

57

65

63

61

67

69

73

71

75

-12 -8 -6-10 -4-20246810

SPURIOUS-FREE DYNAMIC RANGE

vs. CLOCK POWER

MAX106 toc15

CLOCK POWER PER SIDE (dBm)

SFDR (dB)

SINGLE-ENDED CLOCK DRIVE

DIFFERENTIAL CLOCK DRIVE

fIN = 125MHz, -1dBFS

65

67

66

70

69

68

71

72

74

73

75

SPURIOUS-FREE DYNAMIC RANGE

vs. V

EE

MAX106 toc17

V

EE

(V)

SFDR (dB)

-4.50-5.30 -4.70-5.50 -4.90-5.10

f

IN

= 125MHz, -1dBFS

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other­wise noted.)

75

10 100 1000

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

MAX106 toc09

ANALOG INPUT FREQUENCY (MHz)

SFDR (dB)

50

60

65

55

70

-12dBFS

-6dBFS

-1dBFS

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

8 _______________________________________________________________________________________

-70

-68

-69

-66

-67

-64

-65

-63

-61

-62

-60

4.50 4.70 4.90 5.10 5.30 5.50

TOTAL HARMONIC DISTORTION

vs. V

CC

I = VCCA = VCCD

MAX106 toc19

VCC (V)

THD (dB)

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 12060 180 240 300

FFT PLOT

(f

IN

= 125.1708984MHz, RECORD LENGTH 8192)

MAX106 toc20

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

H3

H2

ENOB = 7.75 BITS
SNR = 47.5dB
THD = -68.8dB
SFDR = 70.8dB

FUNDAMENTAL

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 12060 180 240 300

FFT PLOT

(f

IN

= 304.4677734MHz, RECORD LENGTH 8192)

MAX106 toc21

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

H2

ENOB = 7.67 BITS
SNR = 47.2dB
THD = -56.8dB
SFDR = 57.4dB

FUNDAMENTAL

H3

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 12060 180 240 300

FFT PLOT

(f

IN

= 1001.8798828MHz, RECORD LENGTH 8192)

MAX106 toc22

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

H3

H2

ENOB = 7.48 BITS
SNR = 46.0dB
THD = -52.9dB
SFDR = 54.7dB

FUNDAMENTAL

0

-1

-2

-3

-4

-5
500 1500 2500

ANALOG INPUT BANDWIDTH

FULL-POWER

MAX106toc25

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

FULL-POWER BANDWIDTH = 2.2GHz

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 12060 180 240 300

TWO-TONE INTERMODULATION DISTORTION

FFT PLOT (RECORD LENGTH 8192,

-7dB BELOW FULL-SCALE)

MAX106 toc23

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

f1 = 123.9990235MHz
f

2

= 126.0498047MHz

SFDR = 61.6dB

f

1

f

2

(2 x f2) - f

1

(2 x f1) - f

2

-5

-6

-7

-8

-9

-10
500 1500 2500

ANALOG INPUT BANDWIDTH

-6dB BELOW FULL-SCALE

MAX106toc24

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

SMALL-SIGNAL BANDWIDTH = 2.4GHz

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

(LOW-FREQUENCY SERVO-LOOP DATA)

MAX106 toc26

OUTPUT CODE

INL (LSB)

0 32 64 96 128 160 192 224 256

-70

-68

-69

-65

-66

-67

-64

-63

-61

-62

-60

TOTAL HARMONIC DISTORTION

vs. V

EE

MAX106 toc18

V

EE

(V)

THD (dB)

-4.50-5.30 -4.70-5.50 -4.90-5.10

f

IN

= 125MHz, -1dBFS

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other­wise noted.)

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

DIFFERENTIAL NONLINEARITY

vs. OUTPUT

(LOW-FREQUENCY SERVO-LOOP DATA)

MAX106 toc27

OUTPUT CODE

DNL (LSB)

0 32 64 96 128 160 192 224 256

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

_______________________________________________________________________________________ 9

Pin Description

DREADY

200mV/div

DATA

200mV/div

DREADY RISE/FALL TIME,

DATA RISE/FALL TIME

MAX106 toc28

500ps/div

1.0

1.1

1.2

1.3

1.4

1.5

0 1000500 1500 2000 2500

VOLTAGE STANDING-WAVE RATIO

vs. ANALOG INPUT FREQUENCY

MAX106 toc29

ANALOG INPUT FREQUENCY (MHz)

VSWR

Test Point. Do not connect.

TESTPOINT

(T.P.)

A10, E17, F2, P3, R17, R18

Digital GroundGNDD

A11, B11, B16, B17, C11, C16, U9, U17,

V9, V17, V18, W9

PECL Supply Voltage, +3V to +5VVCCO

A12–A19, B19, C19, D19, E19, F19, G19,
H19, J19, K19, L19, M19, N19, P19, T19,

U19, V19, W10–W19

Analog Supply Voltage, +5V. Supplies analog comparator array.VCCAA9, B9, C9, U7, V7, W7

Analog Ground—For comparator array.GNDAA8, B8, C8, U6, V6, W6

CONTACT

Analog Supply Voltage, +5V. Supplies T/H amplifier, clock distribu­tion, bandgap reference, and reference amplifier.

VCCIA5, B5, C5, H2, H3, M2, M3, U5, V5, W5

Analog Ground—for T/H amplifier, clock distribution, bandgap refer­ence, and reference amplifier.

GNDI

A1–A4, A6, A7, B1, B2, C1, C2, D1, D2,

D3, G1, H1, J2, J3, K1, K2, K3, L2, L3,

M1, N1, T2, T3, U1, V1, V2, W1–W4

FUNCTIONNAME

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other­wise noted.)

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

10 ______________________________________________________________________________________

Pin Description (continued)

CONTACT

Analog Supply Voltage, -5V. Supplies T/H amplifier, clock distribu­tion, bandgap reference, and reference amplifier.

V

EE

B3, B4, C3, C4, E3, F3, G2, G3, N2, N3,

U2, U3, U4, V3, V4

FUNCTIONNAME

Reference Ground. Must be connected to GNDI.

GNDRB6, B7

Primary Output Data Bit 0 (LSB)P0+B12

Digital Supply Voltage, +5VVCCD

B10, B18, C10, C17, C18, T17, T18, U8,

U18, V8, W8

Primary Output Data Bit 1P1+B14

Reference InputREFINC6

Auxiliary Output Data Bit 1A1+B15

Auxiliary Output Data Bit 0 (LSB)A0+B13

Complementary Primary Output Data Bit 0 (LSB)P0-C12

Complementary Primary Output Data Bit 1P1-C14

Complementary Auxiliary Output Data Bit 0 (LSB)A0-C13

TTL/CMOS Demux Divide-Selection Input
1: Decimation DIV4 mode
0: Demultiplexed DIV2 mode

DIVSELECTD17

Die Temperature Measurement Test Point. See

Die Temperature

Measurement

section.

ICONSTE1

Tie to VCCO to power the auxiliary port. Tie to GNDD to power
down.

AUXEN2D18

Complementary Auxiliary Output Data Bit 1A1-C15

Reference OutputREFOUTC7

Die Temperature Measurement Test Point. See

Die Temperature

Measurement

section.

IPTATE2

Offset Adjust InputVOSADJF1

TTL/CMOS Demux Enable Control
1: Enable Demux
0: Disable Demux

DEMUXENE18

Primary Output Data Bit 2P2+F18

Auxiliary Output Data Bit 2A2+G18

Complementary Auxiliary Output Data Bit 2A2-G17

Complementary Primary Output Data Bit 2P2-F17

Complementary Primary Output Data Bit 3P3-H17
Primary Output Data Bit 3P3+H18