MAXIM DS2149 User Manual

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www.maxim-ic.com

GENERAL DESCRIPTION

The DS2149 is a fully integrated LIU for long­haul or short-haul T1 applications over twisted­pair installations. It interfaces to two twisted-pair
lines—one pair for transmit and one pair for
receive through an appropriate network
interface. The device can be configured for
control through software or hardware mode.
Software control is accomplished over a serial
port, in hardware mode; individual pin settings
allow standalone operation. The device provides
a precise, crystal-less jitter attenuator that can be
placed in either the transmit or receive path.

APPLICATIONS

Routers
Data Service Units (DSUs)
Channel Service Units (CSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment

PIN CONFIGURATION

TOP VIEW

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DS2149

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DEMO KIT AVAILABLE

DS2149

5V T1/J1 Line Interface Unit

FEATURES

§ Fully Integrated Line Interface Unit (LIU)

§ Pin Compatible with LevelOne LXT362

§ Supports Both Long Haul and Short Haul

§ Crystal-Less Jitter Attenuator

§ Jitter Attenuator Programmable for Transmit

or Receive Path

§ Meets ANSI T1.102, T1.403, T1.408, and
AT&T 62411

§ Usable Receive Sensitivity of 0dB to -36dB
That Allows the Device to Operate on

0.63mm (22AWG) Cables Up to 6k Feet in
Length

§ Five Line Build-Out Settings for Short-Haul
Applications

§ Four CSU Filters from 0dB to -22.5dB

§ Transmit/Receive Performance Monitors

with Driver-Fail, Monitor-Open, and Loss­of-Signal Outputs

§ Bipolar or NRZ Interface

§ Programmable B8ZS Encoder/Decoder

§ QRSS Generator/Detector

§ Local, Remote, and Analog Loopbacks

§ Generates and Detects In-Band Loop-Up and

Loop-Down Codes

§ Serial Interface Provides Access to Control
Registers

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS2149Q 0°C to +70°C 28 PLCC
DS2149QN -40°C to +85°C 28 PLCC

PLCC

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

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DS2149

TABLE OF CONTENTS

1. DETAILED DESCRIPTION................................................................................................. 4

2. OPERATING MODES......................................................................................................... 5

3. INITIALIZATION AND RESET............................................................................................ 9

4. REGISTER DEFINITIONS .................................................................................................. 9

5. TRANSMITTER................................................................................................................... 15

5.1 TRANSMIT DIGITAL DATA INTERFACE ................................................................................... 15

5.2 TRANSMIT MONITORING ...................................................................................................... 15

5.3 TRANSMIT IDLE MODE......................................................................................................... 15

5.4 TRANSMIT PULSE SHAPE ....................................................................................................15

6. RECEIVER.......................................................................................................................... 15

6.1 RECEIVE EQUALIZER ..........................................................................................................15

6.2 RECEIVE DATA RECOVERY..................................................................................................15

6.3 RECEIVE DIGITAL-DATA INTERFACE ..................................................................................... 16

6.4 RECEIVE MONITOR MODE ...................................................................................................16

7. JITTER ATTENUATION .....................................................................................................16

8. HARDWARE MODE ...........................................................................................................16

9. SOFTWARE MODE ............................................................................................................ 17

9.1 INTERRUPT HANDLING ........................................................................................................17

10. DIAGNOSTIC MODE OPERATION.................................................................................... 19

10.1 LOOPBACK MODES............................................................................................................. 20

10.1.1 Local Loopback (LLB).................................................................................................................20

10.1.2 Analog Loopback (ALB)..............................................................................................................20

10.1.3 Remote Loopback (RLB) ............................................................................................................20

10.1.4 Network Loopback......................................................................................................................20

10.1.5 Dual Loopback ...........................................................................................................................20

10.2 INTERNAL PATTERN GENERATION AND DETECTION ............................................................... 21

10.2.1 Transmit Alarm-Indication Signal (TAIS).....................................................................................21

10.2.2 Quasirandom Signal Source (QRSS) .........................................................................................21

10.2.3 In-Band Network Loop-Up or Loop-Down Code Generator.........................................................22

10.3 E

10.3.1 Bipolar Violation Insertion (INSBPV)...........................................................................................22

10.3.2 Logic Error Insertion (INSLE)......................................................................................................22

10.3.3 Logic Error Detection (QPD).......................................................................................................22

10.3.4 Bipolar Violation Detection (BPV) ...............................................................................................22

10.4 A

10.4.1 Receive-Carrier Loss (RCL) .......................................................................................................23

10.4.2 Alarm-Indication-Signal Detection (AIS)......................................................................................23

10.4.3 Driver-Fail Monitor-Open (DFMO) ..............................................................................................23

10.4.4 Jitter Attenuator Limit Trip (JALT)...............................................................................................23

10.5 O

10.5.1 Receive Line-Attenuation Indication ...........................................................................................23

11. NETWORK INTERFACE ....................................................................................................24

12. DC CHARACTERISTICS.................................................................................................... 28

13. PACKAGE INFORMATION ................................................................................................ 32

RROR INSERTION AND DETECTION ..................................................................................... 22

LARM MONITORING........................................................................................................... 23

THER DIAGNOSTIC REPORTS ............................................................................................23

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DS2149

LIST OF FIGURES

Figure 1-1. Block Diagram....................................................................................................................................... 4

Figure 2-1. Hardware Mode Pinout ........................................................................................................................ 6

Figure 2-2. Serial Port Mode Pinout....................................................................................................................... 6

Figure 9-1. Serial Data Port Operation for Read Access.................................................................................. 18

Figure 9-2. Serial Data Port Operation for Write Access.................................................................................. 18

Figure 10-1. Loopbacks in the DS2149 Block Diagram.................................................................................... 21

Figure 11-1. Basic Network Interface .................................................................................................................. 25

Figure 11-2. T1 Transmit Pulse Template .......................................................................................................... 26

Figure 11-3. Jitter Tolerance................................................................................................................................. 27

Figure 11-4. Jitter Attenuation............................................................................................................................... 27

Figure 12-1. Serial Bus Read Timing (MODE1 = 1).......................................................................................... 29

Figure 12-2. Serial Bus Write Timing (MODE1 = 1) .......................................................................................... 29

Figure 12-3. AC Characteristics for Receive Side ............................................................................................. 30

Figure 12-4. AC Characteristics for Transmit Side ............................................................................................ 31

LIST OF TABLES

Table 2-A. Operating Modes ................................................................................................................................... 5

Table 2-B. Control Pins for Hardware and Software Modes .............................................................................. 5

Table 2-C. Signal Descriptions ............................................................................................................................... 7

Table 4-A. Register Map.......................................................................................................................................... 9

Table 4-B. Register Bit Positions............................................................................................................................ 9

Table 4-C. Jitter Attenuator Selection.................................................................................................................. 10

Table 4-D. Line Code and Interface Selection ................................................................................................... 10

Table 4-E. Line Build-out Selection...................................................................................................................... 10

Table 4-F. Data Pattern Selection ........................................................................................................................ 11

Table 9-A. CLKE Pin Selection............................................................................................................................. 17

Table 9-B. Control and Operation Mode Selection............................................................................................ 19

Table 10-A. Diagnostic Modes.............................................................................................................................. 19

Table 11-A. Specifications for Receive Transformer......................................................................................... 24

Table 11-B. Specifications for Transmit Transformer........................................................................................ 24

Table 11-C. Transformer Turns Ratio vs. Series Resistance .......................................................................... 24

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DS2149

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1. DETAILED DESCRIPTION

The DS2149 is a complete T1 line interface unit (LIU) for short-haul and long-haul applications. Receive
sensitivity adjusts automatically to the incoming signal and can be limited to -18dB, -26dB, or

-36dB. The device can generate the necessary DSX-1 line build-outs or CSU line build-outs of 0dB,

-7.5dB, -15dB, and -22.5dB. The on-board crystal-less jitter attenuator requires a 1.544MHz reference
clock. The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can be placed in
either the transmit or receive data paths. The DS2149 has diagnostic capabilities such as loopbacks and
QRSS pattern generation and detection. The device can also generate and detect the in-band loop-up and
loop-down codes specified in AT&T 62411. The device can be configured for control using a serial
interface, or for hardware mode. The device fully meets all of the latest T1 specifications including ANSI
T1.102-1999, ANSI T1.403-1999, ANSI T1.408, and AT&T 62411.

Figure 1-1. Block Diagram

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RCL/QPD

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RCLK

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RPOS

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S

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RNEG

A

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T
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TCLK

L

TPOS

TNEG

Power connections Hardware Interface Serial Interface

L0L1L2

L3

LLB

VDD

VSM

GND

GND

TVDD

JASEL

RLB

TBL/QRSS

MODE0

MODE1

4 of 32

INT

CS

SDI

SDO

CLKE

SCLK

DS2149

2. OPERATING MODES

The DS2149 has several pins with multiple functions and names according to the selected operating
mode. These operating modes are summarized in the tables below.

Table 2-A. Operating Modes

PIN

1 MCLK
2 TCLK
3 TPOS TDATA INSLER
4 TNEG INSBPV INSBPV
6 RNEG BPV RNEG BPV
7 RPOS RDATA RPOS RDATA

8 RCLK
13 TTIP
16 TRING
19 RTIP
20 RRING

Control pins are affected by serial port and hardware modes.

QRSS DISABLED QRSS ENABLED

BIPOLAR NRZ BIPOLAR NRZ

Table 2-B. Control Pins for Hardware and Software Modes

PIN

5 MODE1 MODE1

9 MODE0 MODE0
11 JASEL N.C.
12 RCL RCL/QPD RCL RCL/QPD
23 L0 INT
24 L1 SDI
25 L2 SDO
17 L3 N.C.
18 NLOOP NLOOP
26 RLB NLB CS
27 LLB ALB SCLK
28 TAIS QRSS CLKE

HARDWARE MODE SERIAL PORT MODE

NRZ QRSS NRZ QRSS

5 of 32

Figure 2-1. Hardware Mode Pinout

MODE1

RNEG

RPOS

RCLK

MODE0

VSM

JASEL

TNEG

TPOS

432

5
6
7

DS2149

8
9
10
11

12131415161718

TTIP

RCL/QPD

Figure 2-2. Serial Port Mode Pinout

TCLK

GND

MCLK

1

282726

TVDD

DS2149

TAIS/QRSS

LLB

RLB

L2

25

L1

24

L0

23

GND

22

VDD

21

RRING

20

RTIP

19

L3

TRING

NLOOP

TNEG

TPOS

TCLK

MCLK

CLKE

SCLK

CS

MODE1

RNEG

RPOS

RCLK

MODE0

VSM

N/C

432

5
6
7

DS2149

8
9
10
11

12131415161718

RCL/QPD

TTIP

1

GND

TVDD

282726

N/C

TRING

NLOOP

25
24
23
22
21
20
19

SDO
SDI
INT
GND
VDD
RRING
RTIP

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Table 2-C. Signal Descriptions

PIN NAME I/O FUNCTION

DS2149

1 MCLK I

2 TCLK I

TPOS

3

TDATA

INSLER

TNEG

4

INSBPV

5 MODE1 I

Master Clock. A 1.544MHz clock source with TTL levels is applied at this pin. This
clock is used internally for both clock/data recovery and for jitter attenuation.
Transmit Clock. A 1.544MHz primary clock. Used to clock data through the transmit
side formatter. Can be sourced internally by MCLK or RCLK.
Transmit Positive Data. Sampled on the falling edge of TCLK for data to be
transmitted out onto the line.
Transmit NRZ Data. Sampled on the falling edge of TCLK for data to be transmitted

I

onto the line.

Transmit Insert Logic Error. Rising edge on INSLER inserts a logic error into the
outbound QRSS pattern. Sampled on falling edge of TCLK.

Transmit Negative Data. Sampled on the falling edge of TCLK for data to be
transmitted out onto the line.

I

Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge of TCLK.
Rising edge inserts one BPV.
Mode Select 1. Connect low to select hardware mode. Connect high to select serial

2

port mode. See also MODE0.
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge

RNEG

6

BPV

(CCR2.0 = 1) of RCLK with the bipolar data out of the line interface. Always valid
on rising edge of RCLK in hardware mode.

O

Receive Bipolar Violation. Transitions high for one clock cycle marking an inbound
bipolar violation. Valid on rising edge of RCLK.

Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge

RPOS

(CCR2.0 = 1) of RCLK with bipolar data out of the line interface. Always valid on
rising edge of RCLK in hardware mode.

7

RDATA

O

Receive Data. RDATA is the NRZ output from the line interface. Set NRZE
(CCR1.6) to a 1 for NRZ applications. In NRZ mode, data is output on RPOS while a
received error causes a positive-going pulse synchronous with RCLK at RNEG
(Section 6

8

RCLK

9 MODE0 I

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in

O

absence of signal at RTIP and RRING.
Mode Select 0. Set high to disable all output pins (including the serial control port).

2

Set low for normal operation. Useful in board level testing. See also MODE1.

).

1

10 VSM I

Voltage Supply Mode. Connect high for 5V operation. Has 10kW pullup.

Jitter Attenuator Select
0 = Place the jitter attenuator on the transmit side

11 JASEL I

2

1 = Place the jitter attenuator on the receive side
Float = Disable jitter attenuator
Not used in software mode

RCL Receive Carrier Loss. An output that toggles high during a receive carrier loss.

12

QPD

QPD. Output high when QRSS detector is searching for QRSS data pattern. Output

O

high for one-half clock cycle on bit error. Connect to external counter to count bit
errors.

13/

16
14 VSS —

15

TTIP/

TRING

TVDD

Transmit Tip and Ring. Analog line driver outputs. These pins connect through a

O

step-up transformer to the line (Section 5
Ground for Transmitter Block

— Positive Supply. 5.0V ±5% for the transmitter block. See also VSM pin 10.

7 of 32

).

PIN NAME I/O FUNCTION

DS2149

17 L3 I

LBO3. LBO0 through LBO3 are used to select transmitter output pulse, and receiver
gain.
Network Loopback Active. Output high when RLB is activated by in-band loop-up

18 NLOOP O

command present for 5 seconds. Output is reset when RLP is deactivated by in-band
loop-down command present for 5 seconds. Activation of remote loopback through
hardware pin 26 or control bit RLB releases the NLOOP output.

19/

20

RTIP/

RRING

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect

I

through a 1:1 transformer to the line (Section 6
21 VDD — Positive Supply. 5V ±5%. See also VSM pin 10.
22 VSS — Signal Ground

23

L0

INT

L1

24

SDI

L2

25

SDO

LBO0. LBO0 through LBO3 are used to select transmitter output pulse, and receiver

gain.

I/O

INT. Used to alert the host when one or more bits are set in the status register.

LBO1. LBO0 through LBO3 are used to select transmitter output pulse, and receiver

gain.

I

Serial Data Input. Input for serial address and data stream. Sampled on rising of

SCLK.

LBO2. LBO0 through LBO3 are used to select transmitter output pulse, and receiver

gain.

O

Serial Data Output. Updated on falling edge of SCLK if CLKE is connected high.

Updated on rising edge of SCLK if CLKE is connected low. SDO is high-Z during

write cycle or when CS is high.

Remote Loopback. Used to invoke remote loopback. When held high, the transmitter

RLB

26

inputs are ignored and inbound data received at RTIP and RRING is routed to the

transmitter outputs, TTIP and TRING and transmitted at the inbound recovered clock

2

rate.

I

NLB Network Loopback. Enables network loopback detection when RLB floats.

).

CS

Chip Select. Must be low to read or write to the device. CS is an active-low signal.

Local Loopback. Used to invoke local loopback. When held high, digital inputs

27

LLB

TPOS and TNEG are looped back to RPOS and RNEG, through the jitter attenuator

2

if enabled. Floating this input invokes analog loopback. The analog output signal at

I

TTIP and TRING is routed to the receive inputs RTIP and RRING.

SCLK

TAIS

QRSS

28

Serial Clock Input. Input clock to operate serial port. Max clock rate, 2.048MHz.

Transmit AIS. Input high forces transmitter to output unframed all ones. Unavailable

in remote loopback.

QRSS. Floating this pin enables QRSS pattern generator and detector. Input low

enables normal transmission of data.

2

I

Clock Edge Select

0 = Update RNEG/RPOS on falling edge of RCLK, SDO updated on rising edge of

CLKE

SCLK.

1 = Update RNEG/RPOS on rising edge of RCLK, SDO updated on falling edge of

SCLK.

Note 1: G.703 requires an accuracy of ±50ppm for T1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 interfaces.
Note 2: Input pins have three operating modes.

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DS2149

3. INITIALIZATION AND RESET

During power-up, all control registers are cleared, disabling the transmitter outputs. The device requires a
master clock supplied to the MCLK input pin to operate the PLL. This master clock must be independent,
free-running, and jitter free.

A reset initializes the status and state machines for the RCL, AIS, NLOOP, and QRSS blocks. Under
software control, setting the RESET bit (CR2.7) clears all registers. Allow up to 100ms for the receiver to
recover from initialization.

4. REGISTER DEFINITIONS

The DS2149 contains eight registers for configuring the device and reading status. These are accessible
using the serial port. Table 4-A lists the register names and addresses.

Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSb) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 6 bits identify the register address.

The last bit (MSb) of the address/command byte is the burst mode bit. When the burst bit is enabled (set
to 1) and a READ operation is performed, addresses 10h through 17h are read sequentially, starting at
address 10h. And when the burst bit is enabled and a WRITE operation is performed, addresses 10h
through 17h are written sequentially, starting at address 10h. Burst operation is stopped once address 17h
is read. All data transfers are initiated by driving the CS input low. All data transfers are terminated if the
CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.

Table 4-A. Register Map

REGISTER SYMBOL ADDRESS

Control Register 1 CR1 B010000
Control Register 2 CR2 B010001
Control Register 3 CR3 B010010
Interrupt Mask Register IMR B010011
Transition Status Register TSR B010100
Status Register SR B010101
Information Register IR B010110
Control Register 4 CR4 B010111

Table 4-B. Register Bit Positions

SYMBOL 7 (MSb) 6 5 4 3 2 1 0 (LSb)

CR1 JASEL1 JASEL0 ENCENB UNIENB L3 L2 L1 L0
CR2 RESET PAT1 PAT0 TAIS ENLOOP ALB LLB RLB

CR3 JA6HZ TPD — EQZMON20 EQZMON26 JA128 LIRST TAOZ
IMR Z16D JALT DFMO B8ZSD QRSS AIS NLOOP RCL
TSR Z16D JALT DFMO B8ZSD QRSS AIS NLOOP RCL

SR — — DFMO — QRSS AIS NLOOP RCL

IR RL3 RL2 RL1 RL0 LUP LDN TSCD LOTC

CR4 — — — — — RCL2048 XFMR2 XFMR1

Note: Set unused bits to 0 for normal operation.

9 of 32

CR1 (B010000): Control Register 1

MSb LSb

JASEL1 JASEL0 ENCENB UNIENB L3 L2 L1 L0

SYMBOL POSITION FUNCTION

JASEL1 CR1.7 Jitter attenuator select (Table 4-C)
JASEL0 CR1.6 Jitter attenuator select (Table 4-C)

ENCENB CR1.5 B8ZS and NRZ control (Table 4-D)

UNIENB CR1.4 BPV and NRZ control (Table 4-D)

L3 CR1.3 Line build-out control (Table 4-E)
L2 CR1.2 Line build-out control (Table 4-E)
L1 CR1.1 Line build-out control (Table 4-E)
L0 CR1.0 Line build-out control (Table 4-E)

Table 4-C. Jitter Attenuator Selection

JASEL1 JASEL0 JITTER ATTENUATOR FUNCTION

0 1 Transmit path
1 1 Receive path

X 0 Disabled

Table 4-D. Line Code and Interface Selection

DS2149

UNIENB ENCENB LINE CODE INTERFACE

0 0 AMI Bipolar
1 0 AMI NRZ

X 1 B8ZS NRZ

Table 4-E. Line Build-out Selection

L3 L2 L1 L0 APPLICATION OUTPUT SIGNAL Rx GAIN (dB)

0 0 0 0 T1 Long Haul 0dB 36
0 0 1 0 T1 Long Haul -7.5dB 36
0 1 0 0 T1 Long Haul -15dB 36
0 1 1 0 T1 Long Haul -22.5dB 36
0 0 0 1 T1 Long Haul 0dB 26
0 0 1 1 T1 Long Haul -7.5dB 26
0 1 0 1 T1 Long Haul -15dB 26
0 1 1 1 T1 Long Haul -22.5dB 26
1 0 0 1 D4 Short Haul 6V 18
1 0 1 1 T1 Short Haul DSX-1 (0ft to 133ft) 18
1 1 0 0 T1 Short Haul DSX-1 (133ft to 266ft) 18
1 1 0 1 T1 Short Haul DSX-1 (266ft to 399ft) 18
1 1 1 0 T1 Short Haul DSX-1 (399ft to 533ft) 18
1 1 1 1 T1 Short Haul DSX-1 (533ft to 655ft) 18

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