MAXIM DS21352 Technical data
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3.3V DS21352 and 5V DS21552
T1 Single-Chip Transceivers
FEATURES
§ Complete DS1/ISDN–PRI/J1 transceiver functionality
§ Long and Short haul LIU
§ Crystal–less jitter attenuator
§ Generates DSX–1 and CSU line build-outs
§ HDLC controller with 64-byte buffers Configurable for
FDL or DS0 operation
§ Dual two–frame elastic store slip buffers that can
connect to asynchronous backplanes up to 8.192MHz
§ 8.192MHz clock output locked to RCLK
§ Interleaving PCM Bus Operation
§ Per-channel loopback and idle code insertion
§ 8-bit parallel control port muxed or nonmuxed buses
(Intel or Motorola)
§ Programmable output clocks for Fractional T1
§ Fully independent transmit and receive functionality
§ Generates/detects in-band loop codes from 1 to 8 bits
in length including CSU loop codes
§ IEEE 1149.1 JTAG-Boundary Scan
§ Pin compatible with DS2152/54/354/554 SCTs
§ 100-pin LQFP package (14 mm x 14 mm) 3.3V
(DS21352) or 5V (DS21552) supply; low power
CMOS
PIN ASSIGNMENT
DS21352
DS21552
100
1
ORDERING INFORMATION
DS21352L (0°C to +70°C)
DS21352LN (-40°C to +85°C)
DS21552L (0°C to +70°C)
DS21552LN (-40°C to +85°C)
DESCRIPTION
The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1
lines whether they are DS1 long haul or DSX–1 short haul. The clock recovery circuitry automatically
adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX–1 line build
outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator
(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The
framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also
used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of
internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12–90),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
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DS21352/DS21552
TABLE OF CONTENTS
1. LIST OF FIGURES .........................................................................................................................5
2. LIST OF TABLES ...........................................................................................................................6
3. INTRODUCTION............................................................................................................................7
3.1 FUNCTIONAL DESCRIPTION..............................................................................................8
3.2 DOCUMENT REVISION HISTORY....................................................................................10
4. PIN DESCRIPTION ......................................................................................................................11
4.1 PIN FUNCTION DESCRIPTION..........................................................................................17
4.1.1 Transmit Side Pins ........................................................................................................17
4.1.2 Receive Side Pins ..........................................................................................................20
4.1.3 Parallel Control Port Pins............................................................................................23
4.1.4 JTAG Test Access Port Pins .........................................................................................25
4.1.5 Interleave Bus Operation Pins......................................................................................25
4.1.6 Line Interface Pins........................................................................................................26
4.1.7 Supply Pins....................................................................................................................27
5. PARALLEL PORT........................................................................................................................28
5.1 REGISTER MAP ...................................................................................................................28
6. CONTROL, ID, AND TEST REGISTERS .................................................................................32
6.1 POWER-UP SEQUENCE......................................................................................................32
6.2 DEVICE ID ............................................................................................................................32
6.3 PAYLOAD LOOPBACK.......................................................................................................37
6.4 FRAMER LOOPBACK .........................................................................................................38
6.5 PULSE DENSITY ENFORCER............................................................................................40
6.6 REMOTE LOOPBACK .........................................................................................................44
7. STATUS AND INFORMATION REGISTERS..........................................................................45
8. ERROR COUNT REGISTERS....................................................................................................52
8.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR) ................................................53
8.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) ...............................................54
8.3 MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)....................................55
9. DSO MONITORING FUNCTION...............................................................................................56
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DS21352/DS21552
10. SIGNALING OPERATION..........................................................................................................58
10.1 PROCESSOR-BASED SIGNALING ....................................................................................58
10.2 HARDWARD-BASED SIGNALING ...................................................................................60
10.2.1 Receive Side.................................................................................................................60
10.2.2 Transmit Side...............................................................................................................61
11. PER-CHANNEL CODE (IDLE) GENERATION ......................................................................61
11.1 TRANSMIT SIDE CODE GENERATION ...........................................................................62
11.1.1 Fixed Per-Channel Idle Code Insertion ......................................................................62
11.1.2 Unique Per-Channel Idle Code Insertion....................................................................63
11.2 RECEIVE SIDE CODE GENERATION...............................................................................63
11.2.1 Fixed Per-Channel Idle Code Insertion ......................................................................64
11.2.3 Unique Per-Channel Idle Code Insertion....................................................................64
12. PER-CHANNEL LOOPBACK.....................................................................................................65
13. CLOCK BLOCKING REGISTERS ............................................................................................65
14. ELASTIC STORES OPERATION ..............................................................................................66
14.1 RECEIVE SIDE .....................................................................................................................66
14.2 TRANSMIT SIDE..................................................................................................................67
14.3 ELASTIC STORES INITIALIZATION................................................................................67
14.4 MINIMUM DELAY MODE..................................................................................................67
15. HDLC CONTROLLER.................................................................................................................68
15.1 HDLC FOR DS0S ..................................................................................................................68
15.1.1 Receive an HDLC Message .........................................................................................68
15.1.2 Transmit an HDLC Message .......................................................................................68
15.2 FDL/Fs EXTRACTION AND INSERTION .........................................................................69
15.3 HDLC and BOC CONTROLLER FOR THE FDL................................................................69
15.3.1 General Overview........................................................................................................69
15.3.2 Status Register for the HDLC......................................................................................70
15.3.3 Basic Operation Details ..............................................................................................71
15.3.4 HDLC/BOC Register Description ...............................................................................72
15.4 LEGACY FDL SUPPORT.....................................................................................................82
15.4.1 Overview......................................................................................................................82
15.4.2 Receive Section ............................................................................................................82
15.4.3 Transmit Section..........................................................................................................84
15.5 D4/SLC-96 OPERATION......................................................................................................84
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DS21352/DS21552
16. LINE INTERFACE FUNCTION .................................................................................................85
16.1 RECEIVE CLOCK AND DATA RECOVERY ....................................................................85
16.2 TRANSMIT WAVE SHAPING AND LINE DRIVING.......................................................86
16.3 JITTER ATTNUATOR..........................................................................................................86
16.4 PROTECTED INTERFACES................................................................................................92
16.5 RECEIVE MONITOR MODE...............................................................................................95
17. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION............96
18. TRANSMIT TRANSPARENCY ..................................................................................................99
19. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................99
19.1 DESCRIPTION ......................................................................................................................99
19.2 TAP CONTROLLER STATE MACHINE ..........................................................................101
19.3 INSTRUCTION REGISTER ...............................................................................................103
19.4 TEST REGISTERS ..............................................................................................................105
20. INTERLEAVED PCM BUS OPERATION ..............................................................................109
20.1 CHANNEL INTERLEAVE .................................................................................................111
20.2 FRAME INTERLEAVE.......................................................................................................111
21. FUNCTIONAL TIMING DIAGRAMS .....................................................................................111
22. RECEIVE AND TRANSMIT DATA FLOW DIAGRAMS.....................................................123
23. OPERATING PARAMETERS...................................................................................................125
24. AC TIMING PARAMETERS AND DIAGRAMS....................................................................126
24.1 MULTIPLEXED BUS AC CHARACTERISTICS .............................................................126
24.2 NON-MULTIPLEXED BUS AC CHARACTERISTICS ...................................................129
24.3 RECEIVE SIDE AC CHARACTERISTICS .......................................................................132
24.4 TRANSMIT AC CHARACTERISTICS..............................................................................136
25. MECHANICAL DESCRIPTTION ............................................................................................139
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DS21352/DS21552
1. LIST OF FIGURES
Figure 3-1 SCT BLOCK DIAGRAM.........................................................................................................9
Figure 16-1 EXTERNAL ANALOG CONNECTIONS ..........................................................................87
Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS ..........................................................................88
Figure 16-3 TRANSMIT WAVEFORM TEMPLANE............................................................................89
Figure 16-4 JITTER TOLERANCE.........................................................................................................91
Figure 16-5 JITTER ATTENUATION ....................................................................................................91
Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552...........................................93
Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR TE DS21352..............................................94
Figure 16-8 TYPICAL MONITOR PORT APPLICATION....................................................................95
Figure 19-1 JTAG FUNCTIONAL BLOCK DIAGRAM......................................................................100
Figure 19-2 TAP CONTROLLER STATE DIAGRAM ........................................................................103
Figure 20-1 IBO BASIC CONFIGURATION USING 4 SCTS ............................................................110
Figure 21-1 RECEIVE SIDE D4 TIMING.............................................................................................111
Figure 21-2 RECEIVE SIDE ESF TIMING...........................................................................................112
Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled)..............................113
Figure 21-4 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) ...........113
Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) ...........114
Figure 21-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE ..............................115
Figure 21-7 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE ...........................116
Figure 21-8 TRANSMIT SIDE D4 TIMING .........................................................................................117
Figure 21-9 TRANSMIT SIDE ESF TIMING.......................................................................................118
Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) ........................119
Figure 21-11 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)......119
Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)......120
Figure 21-13 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE.........................121
Figure 21-14 TRANSMIT SIDE INTERLEAVE BUS OPERATION, FRAME MODE .....................122
Figure 22-1 RECEIVE DATA FLOW ...................................................................................................123
Figure 22-2 TRANSMIT DATA FLOW................................................................................................124
Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX=1) .............................................................127
Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) ...........................................................127
Figure 24-3 MOTOROLA BUS TIMING (BTS=1 / MUX=1)..............................................................128
Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX=0) ..............................................................130
Figure 24-5 INTEL BUS READ TIMING (BTS=0 / MUX=0) .............................................................130
Figure 24-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-7 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-8 RECEIVE SIDE TIMING ..................................................................................................133
Figure 24-9 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED...............................................134
Figure 24-10 RECEIVE LINE INTERFACE TIMING .........................................................................135
Figure 24-11 TRANSMIT SIDE TIMING.............................................................................................137
Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED .........................................138
Figure 24-13 TRANSMIT LINE INTERFACE TIMING......................................................................138
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DS21352/DS21552
2. LIST OF TABLES
Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER................................................................11
Table 4-2 PIN DESCRIPTION SORTED BY PIN SYMBOL ................................................................14
Table 5-1 REGISTER MAP SORTED BY ADDRESS...........................................................................29
Table 6-1 DEVICE ID BIT MAP .............................................................................................................33
Table 6-2 OUTPUT PIN TEST MODES .................................................................................................36
Table 7-1 RECEIVE T1 LEVEL INDICATION .....................................................................................47
Table 7-2 ALARM CRITERIA ................................................................................................................49
Table 8-1 LINE CODE VIOLATION COUNTING ARRANGEMENTS ..............................................53
Table 8-2 PATH CODE VIOLATION COUNTING ARRANGEMENTS.............................................54
Table 8-3 MULTIFRAMES OUT OF SYNC COUNTING ARRANGMENTS .....................................55
Table 14-1 ELASTIC STORE DELAY AFTER INITIALIZATION......................................................67
Table 14-2 MINIMUM DELAY MODE CONFIGURATION................................................................67
Table 15-1 TRANSMIT HDLC CONFIGURATION...............................................................................68
Table 15-2 HDLC/BOC CONTROLLER REGISTERS..........................................................................70
Table 16-1 LINE BUILD OUT SELECT IN LICR .................................................................................86
Table16-2 TRANSMIT TRANSFORMER SELECTION .......................................................................87
Table 16-3 TRANSFORMER SPECIFICATIONS..................................................................................88
Table 16-4 PULSE TEMPLATE CORNER POINTS..............................................................................90
Table 16-5 RECEIVE MONITOR MODE GAIN....................................................................................95
Table 17-1 TRANSMIT CODE LENGTH...............................................................................................97
Table 17-2 RECEIVE CODE LENGTH ..................................................................................................97
Table 19-1 INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE .......................................104
Table 19-2 ID CODE STRUCTURE .....................................................................................................105
Table 19-3 DEVICE ID CODES............................................................................................................105
Table 19-4 BOUNDARY SCAN CONTROL BITS ..............................................................................106
Table 20-1 MASTER DEVICE BUS SELECT.....................................................................................110
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DS21352/DS21552
3. INTRODUCTION
The DS21352/552 are 3.3V/5V superset versions of the popular DS2152 T1 single-chip transceiver
offering the new features listed below. All of the original features of the DS2152 have been retained and
software created for the original devices is transferable into the DS21352/552.
NEW FEATURES (after the DS2152)
§ Interleaving PCM Bus Operation
§ Integral HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation
§ IEEE 1149.1 JTAG-Boundary Scan Architecture
§ 3.3V (DS21352 only) supply
FEATURES
§ option for non–multiplexed bus operation
§ crystal–less jitter attenuation
§ 3.3V I/O on all SCTs
§ additional hardware signaling capability including:
– receive signaling reinsertion to a backplane multiframe sync
– availability of signaling in a separate PCM data stream
– signaling freezing
– interrupt generated on change of signaling data
§ ability to calculate and check CRC6 according to the Japanese standard
§ ability to pass the F–Bit position through the elastic stores in the 2.048 MHz backplane mode
§ programmable in–band loop code generator and detector
§ per channel loopback and idle code insertion
§ RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
§ 8.192 MHz clock output synthesized to RCLK
§ HDLC controller can be configured for FDL
§ addition of hardware pins to indicate carrier loss & signaling freeze
§ line interface function can be completely decoupled from the framer/formatter to allow:
– interface to optical, HDSL, and other NRZ interfaces
– be able to “tap” the transmit and receive bipolar data streams for monitoring purposes
– be able corrupt data and insert framing errors, CRC errors, etc.
§ transmit and receive elastic stores now have independent backplane clocks
7 of 137
DS21352/DS21552
3.1 FUNCTIONAL DESCRIPTION
The analog AMI/B8ZS waveform off of the T1 line is transformer coupled into the RRING and RTIP
pins of the DS21352/552. The device recovers clock and data from the analog signal and passes it
through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to
locate the framing/multi-frame pattern. The DS21352/552 contains an active filter that reconstructs the
analog received signal for the nonlinear losses that occur in transmission. The device has a usable receive
sensitivity of 0 dB to –36 dB, which allows the device to operate on cables up to 6000 feet in length. The
receive side framer locates D4 (SLC–96) or ESF multiframe boundaries as well as detects incoming
alarms including, carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the
receive side elastic store can be enabled in order to absorb the phase and frequency differences between
the recovered T1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK
input. The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock.
The RSYSCLK can be a bursty clock with speeds up to 8.192 MHz.
The transmit side of the DS21352/552 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
T1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter
attenuation mux to the waveshaping and line driver functions. The DS21352/552 will drive the T1 line
from the TTIP and TRING pins via a coupling transformer. The line driver can handle both long haul
(CSU) and short haul (DSX–1) lines.
Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In
each 125 ms frame, there are 24 eight–bit channels plus a framing bit. It is assumed that the framing bit is
sent first followed by channel 1. Each channel is made up of eight bits, which are numbered, 1 to 8. Bit
number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. The term
“locked” is used to refer to two clock signals that are phase or frequency locked or derived from a
common clock (i.e., a 1.544 MHz clock may be locked to a 2.048MHz clock if they share the same 8 kHz
component). Throughout this data sheet, the following abbreviations will be used:
B8ZS Bipolar with 8 Zero Substitution
BOC Bit Oriented Code
CRC Cyclical Redundancy Check
D4 Superframe (12 frames per multiframe) Multiframe Structure
ESF Extended Superframe (24 frames per multiframe) Multiframe Structure
FDL Facility Data Link
FPS Framing Pattern Sequence in ESF
Fs Signaling Framing Pattern in D4
Ft Terminal Framing Pattern in D4
HDLC High Level Data Link Control
MF Multiframe
SLC–96 Subscriber Loop Carrier – 96 Channels (SLC–96 is an AT&T registered trademark)
8 of 137
Figure 3-1 SCT BLOCK DIAGRAM
RSIGF
RCHCLK
RCL
RCHBLK
RLINK
RLOS/LOTC
RCLK
RLCLK
8MCLK
Synthesizer
8.192MHz Clock
RSER
RSIG
DS21352/DS21552
RMSYNC
RSYSCLK
RSYNC
RFSYNC
RDATA
Interleave
Bus
TSYNC
TESO
TDATA
TSSYNC
Interleave
TSYSCLK
Bus
TSER
TSIG
TCHBLK
TCLK
TCHCLK
TLINK
TLCLK
CO
RPOSI
RCLKI
RNEGI
RNEGO
RCLKO
RPOSO
8XCLK
XTALD
MCLK
Buffer
Signaling
Control
Framer
Receive Side
24.7MHz
Clock / Data
Recovery
RSYSCLK
Store
Elastic
Payload Loopback
DATA
SYNC
CLOCK
Framer Loopback
Remote Loopback
Jitter Attenuator
Either trans mit or receive pa th
Local Loopback
Receive
Line I/F
Timing Control
Hardware
Signaling
Insertion
LOTC
Store
Elastic
Sync C ontrol
SYNC
CLOCK
Formatter
Transmit Side
s
n
a
r
T
m
F
/
I
e
n
i
L
MUX
HDLC/BOC
Controller
FDL / DS0
INT*
FDL
DATA
(routed to all block s)
Parallel & Test Control Port
MUX
JTAG PORT
t
i
MUX
D0 to D7 /
AD0 to AD7
8
A0 to A6
7
ALE(AS) / A7
RD*(DS*)
WR*(R/W*)
BTS
CS*
TEST
TPOSO
TCLKO
TNEGO
TNEGI
TCLKI
TPOSI
LIUC
JTDO
JTDI
JTCLK
JTMS
J
R
S
T
CI
Timing
HDLC/BOC
Contr oller
FDL / DS0
LIUC
MUX
12.352 MHz
VCO / PLL
RTIP
RRING
9 of 137
TTIP
TRING
DS21352/DS21552
3.2 DOCUMENT REVISION HISTORY
Revision Notes
12-10-98 Initial Release
12-18-98 Add LIUODO (LIU Open Drain Output) to CCR7.0
Add CDIG (Customer Disconnect Indication Generator) to CCR7.1
Add LIUSI (Line Interface Unit Synchronization Interface) to CCR7.2
Correct IBO register bit functions order
Add bit level description to CCR3.6
1-4-99 Delete “The elastic stores can be forced to a known depth via the Elastic Store Reset bit (CCR3.6).
Toggling the CCR3.6 bit forces the read and write pointers into opposite frames” from section 12.0
1-18-99 Add receive IBO operation PCM timing diagram
1-18-99 Correct Device ID register bit definitions
1-28-99 Correct TSYSCLK and RSYSCLK AC timing and add 4.096 MHz and 8.192 MHz AC timing
2-2-99 Correct definition and label or TUDR bit in TPRM register
2-11-99 Correct format of register definitions in body of data sheet
4-1-99 Add Receive Monitor Mode section
4-15-99 Add section on Protected Interfaces
5-7-99 Correct FMS pin # and description in JTAG section
5-17-99 Correct name of status registers in section 15.3.2
5-19-99 Correct definition of RIR3.4
7-27-99 Correct Receive Monitor Mode section
8-16-99 Remove “Preliminary” notice from data sheet
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4. PIN DESCRIPTION
Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER
PIN SYMBOL TYPE DESCRIPTION
1 RCHBLK O Receive Channel Block
2 JTMS I IEEE 1149.1 Test Mode Select
3 8MCLK O 8.192 MHz Clock
4 JTCLK I IEEE 1149.1 Test Clock Signal
5 JTRST I IEEE 1149.1 Test Reset
6 RCL O Receive Carrier Loss
7 JTDI I IEEE 1149.1 Test Data Input
8 NC – No Connect
9 NC – No Connect
10 JTDO O IEEE 1149.1 Test Data Output
11 BTS I Bus Type Select
12 LIUC I Line Interface Connect
13 8XCLK O Eight Times Clock
14 TEST I Test
15 NC – No Connect
16 RTIP I Receive Analog Tip Input
17 RRING I Receive Analog Ring Input
18 RVDD – Receive Analog Positive Supply
19 RVSS – Receive Analog Signal Ground
20 RVSS – Receive Analog Signal Ground
21 MCLK I Master Clock Input
22 XTALD O Quartz Crystal Driver
23 NC – No Connect
24 RVSS – Receive Analog Signal Ground
25 INT* O Interrupt
26 NC – No Connect
27 NC – No Connect
28 NC – No Connect
29 TTIP O Transmit Analog Tip Output
30 TVSS – Transmit Analog Signal Ground
31 TVDD – Transmit Analog Positive Supply
32 TRING O Transmit Analog Ring Output
33 TCHBLK O Transmit Channel Block
34 TLCLK O Transmit Link Clock
35 TLINK I Transmit Link Data
36 CI I Carry In
37 TSYNC I/O Transmit Sync
38 TPOSI I Transmit Positive Data Input
39 TNEGI I Transmit Negative Data Input
40 TCLKI I Transmit Clock Input
41 TCLKO O Transmit Clock Output
42 TNEGO O Transmit Negative Data Output
43 TPOSO O Transmit Positive Data Output
Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER (cont.)
PIN SYMBOL TYPE DESCRIPTION
44 DVDD – Digital Positive Supply
45 DVSS – Digital Signal Ground
46 TCLK I Transmit Clock
47 TSER I Transmit Serial Data
48 TSIG I Transmit Signaling Input
49 TESO O Transmit Elastic Store Output
DS21352/DS21552
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50 TDATA I Transmit Data
51 TSYSCLK I Transmit System Clock
52 TSSYNC I Transmit System Sync
53 TCHCLK O Transmit Channel Clock
54 CO O Carry Out
55 MUX I Bus Operation
56 D0/AD0 I/O Data Bus Bit0/ Address/Data Bus Bit 0
57 D1/AD1 I/O Data Bus Bit1/ Address/Data Bus Bit 1
58 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus 2
59 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3
60 DVSS – Digital Signal Ground
61 DVDD - Digital Positive Supply
62 D4/AD4 I/O Data Bus Bit4/Address/Data Bus Bit 4
63 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5
64 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6
65 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7
66 A0 I Address Bus Bit 0
67 A1 I Address Bus Bit 1
68 A2 I Address Bus Bit 2
69 A3 I Address Bus Bit 3
70 A4 I Address Bus Bit 4
71 A5 I Address Bus Bit 5
72 A6 I Address Bus Bit 6
73 ALE (AS)/A7 I Address Latch Enable/Address Bus Bit 7
74 RD*(DS*) I Read Input(Data Strobe)
75 CS* I Chip Select
76 FMS I Framer Mode Select
77 WR*(R/W*) I Write Input(Read/Write)
78 RLINK O Receive Link Data
79 RLCLK O Receive Link Clock
80 DVSS – Digital Signal Ground
81 DVDD – Digital Positive Supply
82 RCLK O Receive Clock
83 DVDD – Digital Positive Supply
84 DVSS – Digital Signal Ground
85 RDATA O Receive Data
86 RPOSI I Receive Positive Data Input
87 RNEGI I Receive Negative Data Input
88 RCLKI I Receive Clock Input
Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER (cont.)
PIN SYMBOL TYPE DESCRIPTION
89 RCLKO O Receive Clock Output
90 RNEGO O Receive Negative Data Output
91 RPOSO O Receive Positive Data Output
92 RCHCLK O Receive Channel Clock
93 RSIGF O Receive Signaling Freeze Output
94 RSIG O Receive Signaling Output
95 RSER O Receive Serial Data
96 RMSYNC O Receive Multiframe Sync
97 RFSYNC O Receive Frame Sync
98 RSYNC I/O Receive Sync
99 RLOS/LOTC O Receive Loss Of Sync/ Loss Of Transmit Clock
100 RSYSCLK I Receive System Clock
DS21352/DS21552
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Table 4-1 PIN DESCRIPTION SORTED BY PIN SYMBOL
PIN SYMBOL TYPE DESCRIPTION
3 8MCLK O 8.192 MHz Clock
13 8XCLK O Eight Times Clock
66 A0 I Address Bus Bit 0
67 A1 I Address Bus Bit 1
68 A2 I Address Bus Bit 2
69 A3 I Address Bus Bit 3
70 A4 I Address Bus Bit 4
71 A5 I Address Bus Bit 5
72 A6 I Address Bus Bit 6
73 ALE (AS)/A7 I Address Latch Enable/Address Bus Bit 7
11 BTS I Bus Type Select
36 CI I Carry In
54 CO O Carry Out
75 CS* I Chip Select
56 D0/AD0 I/O Data Bus Bit0/ Address/Data Bus Bit 0
57 D1/AD1 I/O Data Bus Bit1/ Address/Data Bus Bit 1
58 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus 2
59 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3
62 D4/AD4 I/O Data Bus Bit4/Address/Data Bus Bit 4
63 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5
64 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6
65 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7
44 DVDD – Digital Positive Supply
81 DVDD – Digital Positive Supply
45 DVSS – Digital Signal Ground
60 DVSS – Digital Signal Ground
80 DVSS – Digital Signal Ground
84 DVSS – Digital Signal Ground
76 FMS I Framer Mode Select
61 DVDD - Digital Positive Supply
83 DVDD – Digital Positive Supply
25 INT* O Interrupt
4 JTCLK I IEEE 1149.1 Test Clock Signal
7 JTDI I IEEE 1149.1 Test Data Input
10 JTDO O IEEE 1149.1 Test Data Output
2 JTMS I IEEE 1149.1 Test Mode Select
5 JTRST I IEEE 1149.1 Test Reset
12 LIUC I Line Interface Connect
21 MCLK I Master Clock Input
55 MUX I Bus Operation
8 NC – No Connect
9 NC – No Connect
15 NC – No Connect
23 NC – No Connect
26 NC – No Connect
Table 4-1 PIN DESCRIPTION SORTED BY PIN SYMBOL (cont.)
PIN SYMBOL TYPE DESCRIPTION
27 NC – No Connect
28 NC – No Connect
1 RCHBLK O Receive Channel Block
92 RCHCLK O Receive Channel Clock
6 RCL O Receive Carrier Loss
82 RCLK O Receive Clock
DS21352/DS21552
13 of 137
88 RCLKI I Receive Clock Input
89 RCLKO O Receive Clock Output
74 RD*(DS*) I Read Input(Data Strobe)
85 RDATA O Receive Data
97 RFSYNC O Receive Frame Sync
79 RLCLK O Receive Link Clock
78 RLINK O Receive Link Data
99 RLOS/LOTC O Receive Loss Of Sync/ Loss Of Transmit Clock
96 RMSYNC O Receive Multiframe Sync
87 RNEGI I Receive Negative Data Input
90 RNEGO O Receive Negative Data Output
86 RPOSI I Receive Positive Data Input
91 RPOSO O Receive Positive Data Output
17 RRING I Receive Analog Ring Input
95 RSER O Receive Serial Data
94 RSIG O Receive Signaling Output
93 RSIGF O Receive Signaling Freeze Output
98 RSYNC I/O Receive Sync
100 RSYSCLK I Receive System Clock
16 RTIP I Receive Analog Tip Input
18 RVDD – Receive Analog Positive Supply
19 RVSS – Receive Analog Signal Ground
20 RVSS – Receive Analog Signal Ground
24 RVSS – Receive Analog Signal Ground
33 TCHBLK O Transmit Channel Block
53 TCHCLK O Transmit Channel Clock
46 TCLK I Transmit Clock
40 TCLKI I Transmit Clock Input
41 TCLKO O Transmit Clock Output
50 TDATA I Transmit Data
49 TESO O Transmit Elastic Store Output
14 TEST I Test
34 TLCLK O Transmit Link Clock
35 TLINK I Transmit Link Data
39 TNEGI I Transmit Negative Data Input
42 TNEGO O Transmit Negative Data Output
38 TPOSI I Transmit Positive Data Input
43 TPOSO O Transmit Positive Data Output
32 TRING O Transmit Analog Ring Output
Table 4-1 PIN DESCRIPTION SORTED BY PIN SYMBOL (cont.)
47 TSER I Transmit Serial Data
48 TSIG I Transmit Signaling Input
52 TSSYNC I Transmit System Sync
37 TSYNC I/O Transmit Sync
51 TSYSCLK I Transmit System Clock
29 TTIP O Transmit Analog Tip Output
31 TVDD – Transmit Analog Positive Supply
30 TVSS – Transmit Analog Signal Ground
77 WR*(R/W*) I Write Input(Read/Write)
22 XTALD O Quartz Crystal Driver
DS21352/DS21552
14 of 137
4. PIN FUNCTION DESCRIPTION
4.1.1 TRANSMIT SIDE PINS
Signal Name:
Signal Description:
Signal Type:
A 1.544 MHz primary clock. Used to clock data through the transmit side formatter.
TCLK
Transmit Clock
Input
DS21352/DS21552
Signal Name:
Signal Description:
Signal Type:
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on
the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the transmit side elastic
store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial
conversion of channel data.
Signal Name:
Signal Description:
Signal Type:
A user programmable output that can be forced high or low during any of the 24 T1 channels. Synchronous with TCLK when
the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful
for blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional
T1, 384 kbps (H0), 768 kbps or ISDN–PRI . Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See section 13 on page 76 for more information.
Signal Name:
Signal Description:
Signal Type:
1.544 MHz , 2.048 MHz , 4.096 MHz or 8.192 MHz clock. Only used when the transmit side elastic store function is enabled.
Should be tied low in applications that do not use the transmit side elastic store. See section 20 on page 129 for details on
4.096 MHz and 8.192 MHz operation using the Interleave Bus Option.
TSER
Transmit Serial Data
Input
TCHCLK
Transmit Channel Clock
Output
TCHBLK
Transmit Channel Block
Output
TSYSCLK
Transmit System Clock
Input
Signal Name:
Signal Description:
Signal Type:
4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See Section 15 for details. Transmit Link Data [TLINK].
TLCLK
Transmit Link Clock
Output
15 of 137
DS21352/DS21552
4.1.1 TRANSMIT SIDE PINS (cont.)
Signal Name:
Signal Description:
Signal Type:
If enabled via TCR1.2, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream
(ESF) or the Fs–bit position (D4) or the Z–bit position (ZBTSI). See Section 15 for details.
TLINK
Transmit Link Data
Input
Signal Name:
Signal Description:
Signal Type:
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR2.2, the DS21352/552
can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame
boundaries, it can also be set via TCR2.4 to output double–wide pulses at signaling frames. See Section 20 for details.
Signal Name:
Signal Description:
Signal Type:
Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or multiframe
boundaries for the transmit side. Should be tied low in applications that do not use the transmit side elastic store.
Signal Name:
Signal Description:
Signal Type:
When enabled, this input will sample signaling bits for insertion into outgoing PCM T1 data stream. Sampled on the falling
edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit
side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of TCLK with data out of the transmit side elastic store whether the elastic store is enabled or not.
This pin is normally tied to TDATA.
TSYNC
Transmit Sync
Input / Output
TSSYNC
Transmit System Sync
Input
TSIG
Transmit Signaling Input
Input
TESO
Transmit Elastic Store Data Output
Output
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLK with data to be clocked through the transmit side formatter. This pin is normally tied to
TESO.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. Can be programmed to source
NRZ data via the Output Data Format (CCR1.6) control bit. This pin is normally tied to TPOSI.
TDATA
Transmit Data
Input
TPOSO
Transmit Positive Data Output
Output
16 of 137
DS21352/DS21552
4.1.1 TRANSMIT SIDE PINS (cont.)
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. This pin is normally tied to
TNEGI.
TNEGO
Transmit Negative Data Output
Output
Signal Name:
Signal Description:
Signal Type:
Buffered clock that is used to clock data through the transmit side formatter (i.e., either TCLK or RCLKI). This pin is normally
tied to TCLKI.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO
by tying the LIUC pin high.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO
by tying the LIUC pin high.
Signal Name:
Signal Description:
Signal Type:
Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high.
TCLKO
Transmit Clock Output
Output
TPOSI
Transmit Positive Data Input
Input
TNEGI
Transmit Negative Data Input
Input
TCLKI
Transmit Clock Input
Input
17 of 137
DS21352/DS21552
4.1.2 RECEIVE SIDE PINS
Signal Name:
Signal Description:
Signal Type:
Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame. See Section 20
for details.
RLINK
Receive Link Data
Output
Signal Name:
Signal Description:
Signal Type:
A 4 kHz or 2 kHz (ZBTSI) clock for the RLINK output.
Signal Name:
Signal Description:
Signal Type:
1.544 MHz clock that is used to clock data through the receive side framer.
Signal Name:
Signal Description:
Signal Type:
A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the receive side elastic
store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for parallel to serial
conversion of channel data.
Signal Name:
Signal Description:
Signal Type:
A user programmable output that can be forced high or low during any of the 24 T1 channels. Synchronous with RCLK when
the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for
blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional T1,
384K bps service, 768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See Section 13 page 76 for details.
RLCLK
Receive Link Clock
Output
RCLK
Receive Clock
Output
RCHCLK
Receive Channel Clock
Output
RCHBLK
Receive Channel Block
Output
Signal Name:
Signal Description:
Signal Type:
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR2.4 = 0) or multiframe (RCR2.4 =
1) boundaries. If set to output frame boundaries then via RCR2.5, RSYNC can also be set to output double–wide pulses on
signaling frames. If the receive side elastic store is enabled via CCR1.2, then this pin can be enabled to be an input via RCR2.3
at which a frame or multiframe boundary pulse is applied. See Section 21 for details.
RSER
Receive Serial Data
Output
RSYNC
Receive Sync
Input/Output
18 of 137
4.1.2 RECEIVE SIDE PINS (cont.)
Signal Name:
Signal Description:
Signal Type:
An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries.
RFSYNC
Receive Frame Sync
Output
DS21352/DS21552
Signal Name:
Signal Description:
Signal Type:
Only used when the receive side elastic store is enabled. An extracted pulse, one RSYSCLK wide, is output at this pin which
identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will output multiframe boundaries
associated with RCLK.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLK with the data out of the receive side framer.
Signal Name:
Signal Description:
Signal Type:
1.544 MHz , 2.048 MHz , 4.096 MHz or 8.192 MHz clock. Only used when the receive side elastic store function is enabled.
Should be tied low in applications that do not use the receive side elastic store. See section 20 on page 129 for details on 4.096
MHz and 8.192 MHz operation using the Interleave Bus Option.
Signal Name:
Signal Description:
Signal Type:
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is disabled.
Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
RMSYNC
Receive Multiframe Sync
Output
RDATA
Receive Data
Output
RSYSCLK
Receive System Clock
Input
RSIG
Receive Signaling Output
Output
Signal Name:
Signal Description:
Signal Type:
A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high when the
synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5 msec.
Signal Name:
Signal Description:
Signal Type:
Set high when the line interface detects a carrier loss.
Signal Name:
Signal Description:
Signal Type:
Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of
the condition.
RLOS/LOTC
Receive Loss of Sync / Loss of Transmit Clock
Output
RCL
Receive Carrier Loss
Output
RSIGF
Receive Signaling Freeze
Output
4.1.2 RECEIVE SIDE PINS (cont.)
Signal Name:
Signal Description:
Signal Type:
An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name:
Signal Description:
Signal Type:
8MCLK
8 MHz Clock
Output
RPOSO
Receive Positive Data Input
Output
19 of 137
DS21352/DS21552
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RPOSI.
Signal Name:
Signal Description:
Signal Type:
Buffered recovered clock from the T1 line. This pin is normally tied to RCLKI.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.
Signal Name:
Signal Description:
Signal Type:
Clock used to clock data through the receive side framer. This pin is normally tied to RCLKO. Can be internally connected to
RCLKO by tying the LIUC pin high.
RNEGO
Receive Negative Data Input
Output
RCLKO
Receive Clock Output
Output
RPOSI
Receive Positive Data Input
Input
RNEGI
Receive Negative Data Input
Input
RCLKI
Receive Clock Input
Input
20 of 137
DS21352/DS21552
4.1.3 PARALLEL CONTROL PORT PINS
Signal Name:
Signal Description:
Signal Type:
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status
Register. Active low, open drain output
INT*
Interrupt
Output
Signal Name:
Signal Description:
Signal Type:
Selects the DS2152 mode when high or the DS21352/552 mode when low. If high, the JTRST is internally pulled low. If low,
JTRST has normal JTAG functionality. This pin has a 10k pull up resistor.
Signal Name:
Signal Description:
Signal Type:
Set high to 3–state all output and I/O pins (including the parallel control port) when FMS = 1 or when FMS = 0 and JTRST* is
tied low. Set low for normal operation. Ignored when FMS = 0 and JTRST* = 1. Useful for board level testing.
Signal Name:
Signal Description:
Signal Type:
Set low to select non–multiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
Signal Description:
Signal Type:
In non–multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as a 8–
bit multiplexed address / data bus.
Signal Name:
Signal Description:
Signal Type:
In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins
are not used and should be tied low.
FMS
Framer Mode Select
Input
TEST
3–State Control
Input
MUX
Bus Operation
Input
AD0 TO AD7
Data Bus [D0 to D7] or Address/Data Bus
Input
A0 TO A6
Address Bus
Input
Signal Name:
Signal Description:
Signal Type:
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD*(DS*),
ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis ().
Signal Name:
Signal Description:
Signal Type:
RD* and DS* are active low signals. DS active HIGH when MUX = 0. See bus timing diagrams.
BTS
Bus Type Select
Input
RD*(DS*)
Read Input - Data Strobe
Input
21 of 137
4.1.3 PARALLEL CONTROL PORT PINS (cont.)
Signal Name:
Signal Description:
Signal Type:
Must be low to read or write to the device. CS* is an active low signal.
CS*
Chip Select
Input
DS21352/DS21552
Signal Name:
Signal Description:
Signal Type:
In non–multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves
to de-multiplex the bus on a positive–going edge.
Signal Name:
Signal Description:
Signal Type:
WR* is an active low signal.
ALE(AS)/A7
Address Latch Enable(Address Strobe) or A7
Input
WR*(R/W*)
Write Input(Read/Write)
Input
22 of 137
DS21352/DS21552
4.1.4 JTAG TEST ACCESS PORT PINS
Signal Name:
Signal Description:
Signal Type:
If FMS = 1: JTAG functionality is not available and JTRST is held LOW internally.
If FMS = 0: JTAG functionality is available and JTRST is pulled up internally by a 10kΩ resistor.
If FMS = 0 and boundary scan is not used, this pin should be held low. This signal is used to asynchronously reset the test
access port controller. The device operates as a T1/E1 transceiver if JTRST is pulled low.
JTRST
IEEE 1149.1 Test Reset
Input
Signal Name:
Signal Description:
Signal Type:
This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1
states. This pin has a 10k pull up resistor.
Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pull up resistor.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left
unconnected.
JTMS
IEEE 1149.1 Test Mode Select
Input
JTCLK
IEEE 1149.1 Test Clock Signal
Input
JTDI
IEEE 1149.1 Test Data Input
Input
JTDO
IEEE 1149.1 Test Data Output
Output
4.1.5 INTERLEAVE BUS OPERATION PINS
Signal Name:
Signal Description:
Signal Type:
A rising edge on this pin causes RSER and RSIG to come out of high Z state and TSER and TSIG to start sampling on the next
rising edge of RSYSCLK/TSYSCLK beginning an I/O sequence of 8 or 256 bits of data. This pin has a 10k pull up resistor.
CI
Carry In
Input
Signal Name:
Signal Description:
Signal Type:
CO
Carry Out
Output
An output that is set high when the last bit of the 8 or 256 IBO output sequence has occurred on RSER
and RSIG.
23 of 137
DS21352/DS21552
4.1.6 LINE INTERFACE PINS
Signal Name:
Signal Description:
Signal Type:
A 1.544 MHz (50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data
recovery and for jitter attenuation. A quartz crystal of 1.544 MHz may be applied across MCLK and XTALD instead of the
TTL level clock source.
MCLK
Master Clock Input
Input
Signal Name:
Signal Description:
Signal Type:
A quartz crystal of 1.544 MHz may be applied across MCLK and XTALD instead of a TTL level clock source at MCLK.
Leave open circuited if a TTL clock source is applied at MCLK.
Signal Name:
Signal Description:
Signal Type:
A 12.352 MHz clock that is locked to the 1.544 MHz clock provided from the clock/data recovery block (if the jitter attenuator
is enabled on the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally
disabled by writing a 08h to TEST2.3 if not needed.
Signal Name:
Signal Description:
Signal Type:
Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/ RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter
circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, the
TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low.
Signal Name:
Signal Description:
Signal Type:
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the T1 line. See Section 16 for details.
XTALD
Quartz Crystal Driver
Output
8XCLK
Eight Times Clock
Output
LIUC
Line Interface Connect
Input
RTIP & RRING
Receive Tip and Ring
Input
Signal Name:
Signal Description:
Signal Type:
Analog line driver outputs. These pins connect via a transformer to the T1 line. See Section 16 for details.
TTIP & TRING
Transmit Tip and Ring
Output
24 of 137
4.1.7 SUPPLY PINS
Signal Name:
Signal Description:
Signal Type:
5.0 volts +/-5% (DS21552) or 3.3 volts +/-5% (DS21352). Should be tied to the RVDD and TVDD pins.
DVDD
Digital Positive Supply
Supply
DS21352/DS21552
Signal Name:
Signal Description:
Signal Type:
5.0 volts +/-5% (DS21552) or 3.3 volts +/-5% (DS21352). Should be tied to the DVDD and TVDD pins.
Signal Name:
Signal Description:
Signal Type:
5.0 volts +/-5% (DS21552) or 3.3 volts +/-5% (DS21352). Should be tied to the RVDD and DVDD pins.
Signal Name:
Signal Description:
Signal Type:
Should be tied to the RVSS and TVSS pins.
Signal Name:
Signal Description:
Signal Type:
0.0 volts. Should be tied to DVSS and TVSS.
Signal Name:
Signal Description:
Signal Type:
0.0 volts. Should be tied to DVSS and RVSS.
RVDD
Receive Analog Positive Supply
Supply
TVDD
Transmit Analog Positive Supply
Supply
DVSS
Digital Signal Ground
Supply
RVSS
Receive Analog Signal Ground
Supply
TVSS
Transmit Analog Signal Ground
Supply
25 of 137
DS21352/DS21552
5. PARALLEL PORT
The SCT is controlled via either a non–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an
external microcontroller or microprocessor. The SCT can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.
Electrical Characteristics in Section 24 for more details.
5.1 REGISTER MAP
Table 5-1 REGISTER MAP SORTED BY ADDRESS
ADDRESS R/W REGISTER NAME REGISTER
ABBREVIATION
00 R/W HDLC Control HCR
01 R/W HDLC Status HSR
02 R/W HDLC Interrupt Mask HIMR
03 R/W Receive HDLC Information RHIR
04 R/W Receive Bit Oriented Code RBOC
05 R Receive HDLC FIFO RHFR
06 R/W Transmit HDLC Information THIR
07 R/W Transmit Bit Oriented Code TBOC
08 W Transmit HDLC FIFO THFR
09 R/W Test 2 SEE NOTE 1 TEST2 (set to 00h)
0A R/W Common Control 7 CCR7
0B – not present –
0C – not present –
0D – not present –
0E – not present –
0F R Device ID IDR
10 R/W Receive Information 3 RIR3
11 R/W Common Control 4 CCR4
12 R/W In–Band Code Control IBCC
13 R/W Transmit Code Definition TCD
14 R/W Receive Up Code Definition RUPCD
15 R/W Receive Down Code Definition RDNCD
16 R/W Transmit Channel Control 1 TCC1
17 R/W Transmit Channel Control 2 TCC2
18 R/W Transmit Channel Control 3 TCC3
19 R/W Common Control 5 CCR5
1A R Transmit DS0 Monitor TDS0M
1B R/W Receive Channel Control 1 RCC1
1C R/W Receive Channel Control 2 RCC2
1D R/W Receive Channel Control 3 RCC3
1E R/W Common Control 6 CCR6
1F R Receive DS0 Monitor RDS0M
20 R/W Status 1 SR1
Table 5-1 REGISTER MAP SORTED BY ADDRESS (Cont.)
ADDRESS R/W REGISTER NAME REGISTER
ABBREVIATION
21 R/W Status 2 SR2
22 R/W Receive Information 1 RIR1
23 R Line Code Violation Count 1 LCVCR1
24 R Line Code Violation Count 2 LCVCR2
25 R Path Code Violation Count 1 SEE NOTE 3 PCVCR1
26 R Path Code violation Count 2 PCVCR2
26 of 137
ADDRESS R/W REGISTER NAME REGISTER
ABBREVIATION
27 R Multiframe Out of Sync Count 2 MOSCR2
28 R Receive FDL Register RFDL
29 R/W Receive FDL Match 1 RMTCH1
2A R/W Receive FDL Match 2 RMTCH2
2B R/W Receive Control 1 RCR1
2C R/W Receive Control 2 RCR2
2D R/W Receive Mark 1 RMR1
2E R/W Receive Mark 2 RMR2
2F R/W Receive Mark 3 RMR3
30 R/W Common Control 3 CCR3
31 R/W Receive Information 2 RIR2
32 R/W Transmit Channel Blocking 1 TCBR1
33 R/W Transmit Channel blocking 2 TCBR2
34 R/W Transmit Channel Blocking 3 TCBR3
35 R/W Transmit Control 1 TCR1
36 R/W Transmit Control 2 TCR2
37 R/W Common Control 1 CCR1
38 R/W Common Control 2 CCR2
39 R/W Transmit Transparency 1 TTR1
3A R/W
3B R/W Transmit Transparency 3 TTR3
3C R/W Transmit Idle 1 TIR1
3D R/W Transmit Idle 2 TIR2
3E R/W Transmit Idle 3 TIR3
3F R/W Transmit Idle Definition TIDR
40 R/W Transmit Channel 9 TC9
41 R/W Transmit Channel 10 TC10
42 R/W Transmit Channel 11 TC11
43 R/W Transmit Channel 12 TC12
44 R/W Transmit Channel 13 TC13
45 R/W Transmit Channel 14 TC14
46 R/W Transmit Channel 15 TC15
47 R/W Transmit Channel 16 TC16
48 R/W Transmit Channel 17 TC17
49 R/W Transmit Channel 18 TC18
4A R/W Transmit Channel 19 TC19
4B R/W Transmit Channel 20 TC20
4C R/W Transmit Channel 21 TC21
Transmit Transparency 2
TTR2
Table 5-1 REGISTER MAP SORTED BY ADDRESS (Cont.)
ADDRESS R/W REGISTER NAME REGISTER
ABBREVIATION
4D R/W Transmit Channel 22 TC22
4E R/W Transmit Channel 23 TC23
4F R/W Transmit Channel 24 TC24
50 R/W Transmit Channel 1 TC1
51 R/W Transmit Channel 2 TC2
52 R/W Transmit Channel 3 TC3
53 R/W Transmit Channel 4 TC4
54 R/W Transmit Channel 5 TC5
55 R/W Transmit Channel 6 TC6
56 R/W Transmit Channel 7 TC7
57 R/W Transmit Channel 8 TC8
58 R/W Receive Channel 17 RC17
59 R/W Receive Channel 18 RC18
27 of 137
DS21352/DS21552
5A R/W Receive Channel 19 RC19
5B R/W Receive Channel 20 RC20
5C R/W Receive Channel 21 RC21
5D R/W Receive Channel 22 RC22
5E R/W Receive Channel 23 RC23
5F R/W Receive Channel 24 RC24
60 R Receive Signaling 1 RS1
61 R Receive Signaling 2 RS2
62 R Receive Signaling 3 RS3
63 R Receive Signaling 4 RS4
64 R Receive Signaling 5 RS5
65 R Receive Signaling 6 RS6
66 R Receive Signaling 7 RS7
67 R Receive Signaling 8 RS8
68 R Receive Signaling 9 RS9
69 R Receive Signaling 10 RS10
6A R Receive Signaling 11 RS11
6B R Receive Signaling 12 RS12
6C R/W Receive Channel Blocking 1 RCBR1
6D R/W Receive Channel Blocking 2 RCBR2
6E R/W Receive Channel Blocking 3 RCBR3
6F R/W Interrupt Mask 2 IMR2
70 R/W Transmit Signaling 1 TS1
71 R/W Transmit Signaling 2 TS2
72 R/W Transmit Signaling 3 TS3
73 R/W Transmit Signaling 4 TS4
74 R/W Transmit Signaling 5 TS5
75 R/W Transmit Signaling 6 TS6
76 R/W Transmit Signaling 7 TS7
77 R/W Transmit Signaling 8 TS8
78 R/W Transmit Signaling 9 TS9
Table 5-1 REGISTER MAP SORTED BY ADDRESS (Cont.)
ADDRESS R/W REGISTER NAME REGISTER
ABBREVIATION
79 R/W Transmit Signaling 10 TS10
7A R/W Transmit Signaling 11 TS11
7B R/W Transmit Signaling 12 TS12
7C R/W Line Interface Control LICR
7D R/W Test 1 SEE NOTE 1 TEST1 (set to 00h)
7E R/W Transmit FDL Register TFDL
7F R/W Interrupt Mask Register 1 IMR1
80 R/W Receive Channel 1 RC1
81 R/W Receive Channel 2 RC2
82 R/W Receive Channel 3 RC3
83 R/W Receive Channel 4 RC4
84 R/W Receive Channel 5 RC5
85 R/W Receive Channel 6 RC6
86 R/W Receive Channel 7 RC7
87 R/W Receive Channel 8 RC8
88 R/W Receive Channel 9 RC9
89 R/W Receive Channel 10 RC10
8A R/W Receive Channel 11 RC11
8B R/W Receive Channel 12 RC12
8C R/W Receive Channel 13 RC13
8D R/W Receive Channel 14 RC14
8E R/W Receive Channel 15 RC15
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DS21352/DS21552
DS21352/DS21552
8F R/W Receive Channel 16 RC16
90 R/W Receive HDLC DS0 Control Register 1 RDC1
91 R/W Receive HDLC DS0 Control Register 2 RDC2
92 R/W Transmit HDLC DS0 Control Register 1 TDC1
93 R/W Transmit HDLC DS0 Control Register 2 TDC2
94 R/W Interleave Bus Operation Register IBO
95 R/W Test 3 SEE NOTE 1 TEST3 (set to 00h)
96 R/W Test 4 SEE NOTE 1 TEST4 (set to 00h)
97 - not present -
98 - not present -
99 - not present 9A - not present 9B - not present 9C - not present 9D - not present 9E - not present -
9F - not present -
NOTES:
1. TEST1, TEST2, TEST3 and TEST4 registers are used by the factory; these registers must be cleared (set to 00h) on power–
up initialization to insure proper operation.
2. Register banks Axh, Bxh, Cxh, Dxh, Exh, and Fxh are not accessible.
3. Upper nibble of the PCVCR1 register is used for MOSCR1
6. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21352/552 is configured via a set of eleven control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the DS21352/552 has been
initialized, the control registers will only need to be accessed when there is a change in the system
configuration. There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control
Registers (TCR1 and TCR2), and seven Common Control Registers (CCR1 to CCR7). Each of the eleven
registers are described in this section.
6.1 POWER-UP SEQUENCE
On power–up, after the supplies are stable the DS21352/552 should be configured for operation by
writing to all of the internal registers (this includes setting the Test Registers to 00h) since the contents of
the internal registers cannot be predicted on power–up. The LIRST (CCR7.7) should be toggled from
zero to one to reset the line interface circuitry (it will take the DS21352/552 about 40ms to recover from
the LIRST bit being toggled). Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit
should be toggled from a zero to a one (this step can be skipped if the elastic stores are disabled).
6.2 DEVICE ID
There is a device IDentification Register (IDR) at address 0Fh. The MSB of this read–only register is
fixed to a zero indicating that a T1 device is present. The next 3 MSBs are used to indicate which T1
device is present; DS2152, DS21352, or DS21552. The E1 pin–for–pin compatible SCTs will have a
logic one in the MSB position with the following 3 MSBs indicating which E1 SCT is present; DS2154,
DS21354, or DS21554. Table 6-1 represents the possible variations of these bits and the associated SCT.
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB) (LSB)
T1E1 Bit 6 Bit 5 Bit 4 ID3 ID2 ID1 ID0
SYMBOL POSITION NAME AND DESCRIPTION
T1E1 IDR.7
T1 or E1 Chip Determination Bit.
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Bit 6 IDR.6
DS21352/DS21552
0=T1 chip
1=E1 chip
Bit 6.
Bit 5 IDR.5
Bit 4 IDR.4
ID3 IDR.3 Chip Revision Bit 3. MSB of a decimal code that represents the chip revision.
ID2 IDR.1
ID1 IDR.2
Bit 5.
Bit 4.
Chip Revision Bit 2.
Chip Revision Bit 1.
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