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DS1330Y/AB
256k Nonvolatile SRAM
with Battery Monito
FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Power supply monitor resets processor when
power loss occurs and holds processor in
V
CC
reset during VCC ramp-up
Battery monitor checks remaining capacity
daily
Read and write access times as fast as 70ns
Unlimited write cycle endurance
Typical standby current 50µA
Upgrade for 32k x 8 SRAM, EEPROM or
Flash
Lithium battery is electrically disconnected to
retain freshness until power is applied for the
first time
Full ±10% V
or optional ±5% VCC operating range
(DS1330AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
operating range (DS1330Y)
CC
PIN ASSIGNMENT
BW
NC
NC
RST
V
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
CC
5
6
7
8
9
10
11
12
13
14
15
16
17
34-Pin POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
GND
V
BAT
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
14
12
11
10
9
0
PIN DESCRIPTION
A0 – A14 - Address Inputs
DQ0 – DQ7 - Data In/Data Out
CE - Chip Enable
WE - Write Enable
OE - Output Enable
RST - Reset Output
BW - Battery Warning
- Power (+5V)
V
CC
GND - Ground
NC - No Connect
- Standardized pinout for all nonvolatile
(NV) SRAM products
- Detachment feature on PowerCap allows
easy removal using a regular screwdriver
DESCRIPTION
The DS1330 256k NV SRAMs are 262,144-bit, fully static, NV SRAMs organized as 32,768 words by 8
bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly
monitors V
is automatically switched on and write protection is unconditionally enabled to prevent data corruption.
Additionally, the DS1330 devices have dedicated circuitry for monitoring the status of VCC and the status
of the internal lithium battery. DS1330 devices in the PowerCap module package are directly surface
mountable and are normally paired with a DS9034PC PowerCap to form a complete NV SRAM module.
The devices can be used in place of 32k x 8 SRAM, EEPROM, or Flash components.
for an out-of-tolerance condition. When such a condition occurs, the lithium energy source
CC
1 of 11 032904
DS1330Y/AB
READ MODE
The DS1330 devices execute a read c ycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs
(A0 – A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t
CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
that
satisfied, then data access must be m easured from the later occu rring signal (
(Access Time) after the last address input signal is stable, providing
ACC
CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1330 devices execute a write cycle whenever the WE and CE signals are in the active (low) state
after address inputs are stable. The later-occu rring falling edge of CE or WE will determine the start of
the write cycle. The writ e cycle is termi nated by the ea rlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE
active) then WE will disable the outputs in t
from its falling edge.
ODW
DATA RETENTION MODE
The DS1330AB provides full-functional capability for VCC greater than 4.75V and write protects by
4.5V. The DS1330Y provides full-functional capability for VCC greater than 4.5V and write protects by
4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The NV
SRAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write
protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls
below approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 2.7V, the power switching circuit
connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation
can resume after VCC exceeds 4.75V for the DS1330AB and 4.5V for the DS1330Y.
SYSTEM POWER MONITORING
DS1330 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power
failure by asserting
operation during power-on transients and to allow t
RST . On power-up, RST is held active for 200ms nominal to prevent system
to elapse. RST has an open drain output driver.
REC
BATTERY MONITORING
The DS1330 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within t
failure occurs.
After each 24-hour period has elapsed, the b attery is connected to an internal 1MΩ test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output
BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open drain output driver.
after VCC rises above VTP and is suspended when power
REC
2 of 11
DS1330Y/AB
PACKAGES
The 34-pin PowerCap module integrates SRAM memory and NV control along with contacts for
connection to the lithium battery in the DS9034PC PowerCap. The PowerCap module package design
allows a DS1330 PCM device to be surface mounted without subjecting its lithium backup battery to
destructive high-temperature reflow soldering. After a DS1330 PCM is reflow soldered, a DS9034 PC is
snapped on top of the PCM to form a complete NV SRAM module. The DS9034PC is keyed to prevent
improper attachment. DS1330 PowerCap modules and DS9034PC PowerCaps are ordered separately and
shipped in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature Range 0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature Range -40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1330AB Power Supply Voltage V
CC
4.75 5.0 5.25 V
DS1330Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 0.8 V
DC ELECTRICAL (V
CHARACTERISTICS (t
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current I
I/O Leakage Current CE ≥ VIH ≤ V
Output Current @ 2.4V I
Output Current @ 0.4V I
Standby Current CE =2.2V
Standby Current CE =VCC-0.5V
Operating Current I
Write Protection Voltage (DS1330AB) V
Write Protection Voltage (DS1330Y) V
CC
: See Note 10) (V
A
IL
I
IO
OH
OL
I
CCS1
I
CCS2
CCO1
TP
TP
-1.0 +1.0
-1.0 +1.0
-1.0 mA 14
2.0 mA 14
200 600
50 150
85 mA
4.50 4.62 4.75 V
4.25 4.37 4.5 V
= 5V ±=5% for DS1330AB)
CC
= 5V ±=10% for DS1330Y)
CC
µA
µA
µA
µA
3 of 11
DS1330Y/AB
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
Input/Output Capacitance C
IN
I/O
5 10 pF
5 10 pF
AC ELECTRICAL (V
CHARACTERISTICS (t
PARAMETER SYMBOL
Read Cycle Time t
Access Time t
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
Output High Z from Deselection t
Output Hold from Address
Change
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time t
Output High Z from WE
t
: See Note 10) (V
A
DS1330AB-70
DS1330Y-70
MIN MAX MIN MAX
RC
ACC
t
OE
t
CO
t
COE
OD
t
OH
WC
WP
AW
WR1
t
WR2
ODW
70 100 ns
70 100 ns
45 50 ns
70 100 ns
5 5 ns 5
25 35 ns 5
5 5 ns
70 100 ns
55 75 ns 3
0 0 ns
5
12
25 35 ns 5
5
= 5V ±=5% for DS1330AB)
CC
= 5V ±=10% for DS1330Y)
CC
DS1330AB-100
DS1330Y-100
UNITS NOTES
ns 12
12
13
Output Active from WE
Data Setup Time t
Data Hold Time t
READ CYCLE
SEE NOTE 1
t
OEW
DS
DH1
t
DH2
5 5 ns 5
30 40 ns 4
0
7
4 of 11
0
7
ns 12
13
WRITE CYCLE 1
DS1330Y/AB
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
5 of 11
POWER-DOWN/POWER-UP CONDITION
DS1330Y/AB
BATTERY WARNING DETECTION
6 of 11
DS1330Y/AB
POWER-DOWN/POWER-UP TIMING (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to CE and WE Inactive
VCC slew from VTP to 0V t
VCC Fail Detect to RST Active
VCC slew from 0V to V
TP
t
VCC Valid to CE and WE Inactive
VCC Valid to End of Write Protection t
VCC Valid to RST Inactive
VCC Valid to BW Valid
t
t
t
PD
F
RPD
t
R
t
PU
REC
RPU
BPU
1.5
150
15
150
µs
µs
µs
µs
11
14
2 ms
125 ms
150 200 350 ms 14
1 s 14
BATTERY WARNING TIMING (t
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Battery Test Cycle t
Battery Test Pulse Width t
Battery Test to BW Active
BTC
BTPW
t
BW
24 hr
1 s
1 s
: See Note 10)
A
(t
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
= 25°C)
A
Expected Data Retention Time t
DR
10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
7 of 11
DS1330Y/AB
9. Each DS1330 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. t
13. t
WR1
WR2
and t
and t
are measured from WE going high.
DH1
are measured from CE going high.
DH2
14. RST and BW are open drain outputs and cannot source cu rrent. External pull-up resistors should be
connected to these pins for proper operation. Both pins will sink 10mA.
15. DS1330 modules are recognized by Underwriters Laboratory (U.L.®) under file E99151.
DC TEST CONDITIONS AC TEST CONDITIONS
Outputs Open Output Load: 100 pF + 1TTL Gate
Cycle = 200ns for operating current Input Pulse Levels: 0 – 3.0V
All voltages are referenced to ground Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1330 TTP - SSS - III
Operating Temperature Range
blank: 0° to 70°
Access Speed
70: 70ns
100: 100ns
Package Type
P: 34-pin PowerCap Module
V
AB: ±5%
Y: ±10%
IND: -40° to +85°C
Tolerance
CC
8 of 11
DS1330Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE
PKG
DIM
A
B
C
D
E
F
G
INCHES
MIN NOM MAX
0.920 0.925 0.930
0.980 0.985 0.990
- - 0.080
0.052 0.055 0.058
0.048 0.050 0.052
0.015 0.020 0.025
0.020 0.025 0.030
DS1330Y/AB
9 of 11
DS1330Y/AB
DS1330Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH
POWERCAP
PKG
DIM
A
B
C
D
E
F
G
INCHES
MIN NOM MAX
0.920 0.925 0.930
0.955 0.960 0.965
0.240 0.245 0.250
0.052 0.055 0.058
0.048 0.050 0.052
0.015 0.020 0.025
0.020 0.025 0.030
ASSEMBLY AND USE
Reflow soldering
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented label-side up (live-bug).
Hand soldering and touch-up
Do not touch soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the
lead frame pad and apply solder. To remove part, apply flux, heat pad until solder reflows, and use a
solder wick.
LPM replacement in a socket
To replace a Low Profile Module in a 68-pin PLCC socket, attach a DS9034PC PowerCap to a module
base then insert the complete module into the socket one row of leads at a time, pushing only on the
corners of the cap. Never appl y force to the center of the device. To rem ove from a socket, use a PLCC
extraction tool and ensure that it does not hit or damage any of the module IC components. Do not use
any other tool for extraction.
10 of 11
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
A
B
C
D
E
MIN NOM MAX
INCHES
- 1.050 -
- 0.826 -
- 0.050 -
- 0.030 -
- 0.112 -
RECOMMENDED POWERCAP MODULE SOLDER STENCIL
PKG
DIM
A
B
C
D
E
MIN NOM MAX
INCHES
- 1.050 -
- 0.890 -
- 0.050 -
- 0.030 -
- 0.080 -
DS1330Y/AB
11 of 11
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