MAXIM DS12885, DS12887, DS12C887 User Manual

General Description

The DS12885, DS12887, and DS12C887 real-time
clocks (RTCs) are designed to be direct replacements
for the DS1285 and DS1287. The devices provide a
real-time clock/calendar, one time-of-day alarm, three
maskable interrupts with a common interrupt output, a
programmable square wave, and 114 bytes of battery­backed static RAM (113 bytes in the DS12C887 and
DS12C887A). The DS12887 integrates a quartz crystal
and lithium energy source into a 24-pin encapsulated
DIP package. The DS12C887 adds a century byte at
address 32h. For all devices, the date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including correction for leap years. The
devices also operate in either 24-hour or
12-hour format with an AM/PM indicator. A precision
temperature-compensated circuit monitors the status of
VCC. If a primary power failure is detected, the device
automatically switches to a backup supply. A lithium
coin-cell battery can be connected to the V

BAT

input
pin on the DS12885 to maintain time and date operation
when primary power is absent. The device is accessed
through a multiplexed byte-wide interface, which sup­ports both Intel and Motorola modes.

Applications

Embedded Systems

Utility Meters

Security Systems

Network Hubs, Bridges, and Routers

Features

♦ Drop-In Replacement for IBM AT Computer

Clock/Calendar

♦ RTC Counts Seconds, Minutes, Hours, Day, Date,

Month, and Year with Leap Year Compensation
Through 2099

♦ Binary or BCD Time Representation

♦ 12-Hour or 24-Hour Clock with AM and PM in

12-Hour Mode

♦ Daylight Saving Time Option

♦ Selectable Intel or Motorola Bus Timing

♦ Interfaced with Software as 128 RAM Locations

♦ 14 Bytes of Clock and Control Registers

♦ 114 Bytes of General-Purpose, Battery-Backed

RAM (113 Bytes in the DS12C887 and
DS12C887A)

♦ RAM Clear Function (DS12885, DS12887A, and

DS12C887A)

♦ Interrupt Output with Three Independently

Maskable Interrupt Flags

♦ Time-of-Day Alarm Once Per Second to Once

Per Day

♦ Periodic Rates from 122µs to 500ms

♦ End-of-Clock Update Cycle Flag

♦ Programmable Square-Wave Output

♦ Automatic Power-Fail Detect and Switch Circuitry

♦ Optional 28-Pin PLCC Surface Mount Package or

32-Pin TQFP (DS12885)

♦ Optional Encapsulated DIP (EDIP) Package with

Integrated Crystal and Battery (DS12887,
DS12887A, DS12C887, DS12C887A)

♦ Optional Industrial Temperature Range Available

♦ Underwriters Laboratory (UL) Recognized

DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

______________________________________________ Maxim Integrated Products 1

DS12885

DS83C520

R/W

AS

GND

X2X1

V

CC

V

CC

CRYSTAL

DS

V

BAT

AD(0–7) SQW

RESET

IRQ

RCLR

CS

MOT

Typical Operating Circuit

Rev 2; 5/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configurations and Ordering Information appear at end of data sheet.

DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

2 _____________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on VCCPin Relative to Ground .....-0.3V to +6.0V

Operating Temperature Range ...................................................

Commercial (noncondensing) .............................0°C to +70°C

Operating Temperature Range ...................................................

Industrial (noncondensing)...............................-40°C to +85°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature .......................................See IPC/JEDEC

J-STD-020 Specification (Note 1)

Soldering Temperature (leads, 10s) ................................+260°C

DC ELECTRICAL CHARACTERISTICS

(V

CC

= +4.5V to +5.5V, TA= over the operating range, unless otherwise noted.) (Note 2)

PARAMETER

CONDITIONS

UNITS

Supply Voltage V

CC

(Note 3) 4.5 5.5 V

V

BAT

Input Voltage V

BAT

(Note 3) 2.5 4.0 V

Input Logic 1 V

IH

(Note 3) 2.2

V

CC

+

0.3

V

Input Logic 0 V

IL

(Note 3)

V

VCC Power-Supply Current I

CC1

(Note 4) 15 mA

VCC Standby Current I

CCS

(Note 5) mA

Input Leakage I

IL

µA

I/O Leakage I

OL

(Note 6)

µA

Input Current I

MOT

(Note 7)

µA

Output at 2.4V I

OH

(Note 3)

mA

Output at 0.4V I

OL

(Note 3) 4.0 mA

Power-Fail Voltage V

PF

(Note 3) 4.0

4.5 V

VRT Trip Point

1.3 V

SYMBOL

MIN TYP MAX

-0.3 +0.8

-1.0 +1.0

-1.0 +1.0

-1.0 +500

-1.0

4.25

VRT

TRIP

DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

_____________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS

(VCC= 0V, V

BAT

= 3.0V, TA= over the operating range, unless otherwise noted.) (Note 2)

PARAMETER

CONDITIONS

UNITS

V

BAT

Current (OSC On);

T

A

= +25°C, V

BACKUP

= 3.0V

I

BAT

(Note 8) 500 nA

V

BAT

Current (Oscillator Off) I

BATDR

(Note 8) 100 nA

AC ELECTRICAL CHARACTERISTICS

(VCC= 4.5V to 5.5V, TA= over the operating range.) (Note 2)

PARAMETER

CONDITIONS

Cycle Time t

CYC

DC ns

Pulse Width, DS Low or R/W High

PW

EL

ns

Pulse Width, DS High or R/W Low

PW

EH

ns

Input Rise and Fall tR, t

F

30 ns

R/W Hold Time t

RWH

10 ns

R/W Setup Time Before DS/E t

RWS

50 ns

Chip-Select Setup Time Before
DS or R/W

t

CS

20 ns

Chip-Select Hold Time t

CH

0ns

Read-Data Hold Time t

DHR

10 80 ns

Write-Data Hold Time t

DHW

0ns

Address Valid Time to AS Fall t

ASL

30 ns

Address Hold Time to AS Fall t

AHL

10 ns

Delay Time DS/E to AS Rise t

ASD

20 ns

Pulse Width AS High PW

ASH

60 ns

Delay Time, AS to DS/E Rise t

ASED

40 ns

Output Data Delay Time from DS
or R/W

t

DDR

20 120 ns

Data Setup Time t

DSW

ns

Reset Pulse Width t

RWL

5µs

IRQ Release from DS t

IRDS

2µs

IRQ Release from RESET t

IRR

2µs

SYMBOL

SYMBOL

MIN TYP MAX

MIN TYP MAX UNITS

385

150

125

100

DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

4 _____________________________________________________________________

PW

ASH

PW

EL

t

ASED

t

CYC

t

RWS

t

CS

t

RWH

t

CH

PW

EH

t

ASD

AD0–AD7

READ

CS

R/ W

AS

DS

AD0–AD7

WRITE

t

DHW

t

DHR

t

DDR

t

AHL

t

ASL

t

DSW

Motorola Bus Read/Write Timing

Intel Bus Write Timing

PW

ASH

PW

EL

PW

EH

t

CS

t

AHL

t

ASL

t

DSW

t

DHW

t

CH

t

ASD

t

ASD

t

CYC

CS

R/W

AS

DS

AD0–AD7

WRITE

t

ASED

DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

_____________________________________________________________________ 5

t

CS

t

AHL

t

ASL

t

CYC

PW

ASH

PW

ASL

PW

EH

CS

R/W

AS

DS

AD0–AD7

t

ASD

t

ASD

t

ASED

t

DDR

t

DHR

t

CH

Intel Bus Read Timing

t

RWL

t

IRR

t

IRDS

DS

RESET

IRQ

IRQ

Release Delay Timing

OUTPUTS

INPUTS

HIGH-Z

DON'T CARE

VALID

RECOGNIZED

RECOGNIZED

VALID

V

CC

t

F

V

PF(MAX)

V

PF(MIN)

t

RPU

t

R

t

DR

Power-Up/Power-Down Timing

DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

6 _____________________________________________________________________

POWER-UP/POWER-DOWN CHARACTERISTICS

(TA= -40°C to +85°C) (Note 2)

PARAMETER

CONDITIONS

UNITS

Recovery at Power-Up t

RPU

20 200 ms

VCC Fall Time; V

PF(MAX)

to

V

PF(MIN)

t

F

300 µs

VCC Rise Time; V

PF(MIN)

to

V

PF(MAX)

t

R

0µs

CAPACITANCE

(TA= +25°C) (Note 9)

PARAMETER

CONDITIONS

UNITS

Capacitance on All Input Pins
Except X1 and X2

C

IN

5pF

Capacitance on IRQ, SQW, and
DQ Pins

C

IO

7pF

DATA RETENTION

(TA= +25°C)

PARAMETER

CONDITIONS

UNITS

Expected Data Retention t

DR

10

years

AC TEST CONDITIONS

PARAMETER TEST CONDITIONS

Input Pulse Levels 0 to 3.0V

Output Load Including Scope and Jig 50pF + 1TTL Gate

Input and Output Timing Measurement Reference Levels Input/Output: VIL maximum and VIH minimum

Input-Pulse Rise and Fall Times 5ns

WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.

Note 1: RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature

exposure to the lithium energy source contained within does not exceed +85°C. However, post-solder cleaning with water­washing techniques is acceptable, provided that ultrasonic vibrations are not used to prevent crystal damage.

Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: All outputs are open.
Note 5: Specified with

CS = DS = R/W = RESET = VCC; MOT, AS, AD0–AD7 = 0; V

BACKUP

open.

Note 6: Applies to the AD0 to AD7 pins, the IRQ pin, and the SQW pin when each is in a high-impedance state.
Note 7: The MOT pin has an internal 20kΩ pulldown.
Note 8: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 9: Guaranteed by design. Not production tested.
Note 10: Measured with a 50pF capacitance load.

SYMBOL

SYMBOL

SYMBOL

MIN TYP MAX

MIN TYP MAX

MIN TYP MAX

DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

_____________________________________________________________________ 7

Typical Operating Characteristics

(VCC= +5.0V, TA= +25°C, unless otherwise noted.)

OSCILLATOR FREQUENCY

vs. V

CC

DS12885 toc02

VCC (V)

FREQUENCY (Hz)

5.3

5.04.8

32768.10

32768.20

32768.30

32768.40

32768.50

32768.60

32768.70

32768.00

4.5 5.5

I

BAT1

vs. V

BAT

vs. TEMPERATURE

DS12885 toc01

V

BAT

(V)

I

BAT

(nA)

3.82.8

3.0

3.3

3.5

200

300

250

150

2.5

4.0

VCC = 0V

+85°C

+25°C

0°C

-40°C

+70°C

+40°C

POWER

CONTROL

GND

OSC

BUS

INTERFACE

V

CC

X1

X2

RESET

CS

DS

AS

R/W

MOT

AD0–AD7

DIVIDE

BY 8

DIVIDE

BY 64

DIVIDE

BY 64

16:1 MUX

SQUARE-

WAVE

GENERATOR

REGISTERS A, B, C, D

CLOCK/CALENDAR AND

ALARM REGISTERS

USER RAM
114 BYTES

CLOCK/CALENDAR

UPDATE LOGIC

IRQ

SQW

IRQ

GENERATOR

BUFFERED CLOCK/

CALENDAR AND ALARM

REGISTERS

V

BAT

RLCR

DS12885

Functional Diagram

DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

8 _____________________________________________________________________

Pin Description

PIN

SO,

PDIP

FUNCTION

11229

Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When
connected to V

CC

, Motorola bus timing is selected. When connected to GND or
left disconnected, Intel bus timing is selected. The pin has an internal pulldown
resistor.

2—330X1

3—431X2

Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator
circuitry is designed for operation with a crystal having a 6pF specified load
capacitance (C

L

). Pin X1 is the input to the oscillator and can optionally be
connected to an external 32.768kHz oscillator. The output of the internal oscillator,
pin X2, is floated if an external oscillator is connected to pin X1.

4–11

1, 2, 3,
5, 7, 8,

9, 11

Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during
the first portion of the bus cycle and latched into the device by the falling edge of
AS. Write data is latched by the falling edge of DS (Motorola timing) or the rising
edge of R/W (Intel timing). In a read cycle, the device outputs data during the
latter portion of DS (DS and R/W high for Motorola timing, DS low and R/W high for
Intel timing). The read cycle is terminated and the bus returns to a high­impedance state as DS transitions low in the case of Motorola timing or as DS
transitions high in the case of Intel timing.

12, 16

12

Ground

13 13 16 13 CS

Active-Low Chip-Select Input. The chip-select signal must be asserted low for a
bus cycle in the device to be accessed. CS must be kept in the active state during
DS and AS for Motorola timing and during DS and R/W for Intel timing. Bus cycles
that take place without asserting CS will latch addresses, but no access occurs.
When V

CC

is below VPF volts, the device inhibits access by internally disabling the

CS input. This action protects the RTC data and the RAM data during power
outages.

14 14 17 14 AS

Address Strobe Input. A positive-going address-strobe pulse serves to
demultiplex the bus. The falling edge of AS causes the address to be latched
within the device. The next rising edge that occurs on the AS bus clears the
address regardless of whether CS is asserted. An address strobe must
immediately precede each write or read access. If a write or read is performed
with CS deasserted, another address strobe must be performed prior to a read or
write access with CS asserted.

15 15 19 16

Read/Write Input. The R/W pin has two modes of operation. When the MOT pin is
connected to V

CC

for Motorola timing, R/W is at a level that indicates whether the
current cycle is a read or write. A read cycle is indicated with a high level on R/W
while DS is high. A write cycle is indicated when R/W is low during DS. When the
MOT pin is connected to GND for Intel timing, the R/W signal is an active-low
signal. In this mode, the R/W pin operates in a similar fashion as the write-enable
signal (WE) on generic RAMs. Data are latched on the rising edge of the signal.

EDIP PLCC TQFP

4–11

5–10,

12, 14

15, 20 12, 17 GND

NAME

MOT

AD0–

AD7

R/W

DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

_____________________________________________________________________ 9

Pin Description (continued)

PIN

SO,

PDIP

FUNCTION

22

16, 20,

1, 11,

13, 18,

26

4, 6, 10,

15, 20,
23, 25,

No Connection. This pin should remain unconnected. Pin 21 is RCLR for the
DS12887A/DS12C887A. On the EDIP, these pins are missing by design.

17 17 21 18 DS

D ata S tr ob e or Read Inp ut. The D S p i n has tw o m od es of op er ati on d ep end i ng on
the l evel of the M O T p i n. W hen the M O T p i n i s connected to V

C C

, M otor ol a b us
ti m i ng i s sel ected . In thi s m od e, D S i s a p osi ti ve p ul se d ur i ng the l atter p or ti on of the
b us cycl e and i s cal l ed d ata str ob e. D ur i ng r ead cycl es, D S si g ni fi es the ti m e that the
device i s to d r i ve the b i d i r ecti onal b us. In w r i te cycl es, the tr ai l i ng ed g e of D S causes
the device to l atch the w r i tten d ata. W hen the M O T p i n i s connected to GN D , Intel
b

us ti m i ng i s sel ected . D S i d enti fi es the ti m e p er i od w hen the device d r i ves the b us

w i th r ead d ata. In thi s m od e, the D S p i n op er ates i n a si m i l ar fashi on as the outp ut­enab l e ( O E ) si g nal on a g ener i c RAM .

18 18 22 19

Active-Low Reset Input. The RESET pin has no effect on the clock, calendar, or
RAM. On power-up, the RESET pin can be held low for a time to allow the power
supply to stabilize. The amount of time that RESET is held low is dependent on the
application. However, if RESET is used on power-up, the time RESET is low should
exceed 200ms to ensure that the internal timer that controls the device on power-

up has timed out. When RESET is low and VCC is above VPF, the following occurs:

A. Periodic interrupt-enable (PIE) bit is cleared to 0.
B. Alarm interrupt-enable (AIE) bit is cleared to 0.
C. Update-ended interrupt-enable (UIE) bit is cleared to 0.
D. Periodic-interrupt flag (PF) bit is cleared to 0.
E. Alarm-interrupt flag (AF) bit is cleared to 0.
F. Update-ended interrupt flag (UF) bit is cleared to 0.
G. Interrupt-request status flag (IRQF) bit is cleared to 0.
H. IRQ pin is in the high-impedance state.
I. The device is not accessible until RESET is returned high.
J. Square-wave output-enable (SQWE) bit is cleared to 0.
In a typical application, RESET can be connected to V

CC

. This connection allows
the device to go in and out of power fail without affecting any of the control
registers.

EDIP PLCC TQFP

2, 3,

21, 22

27, 32

NAME

N.C.

RESET