MAXIM DS1284, DS1286 User Manual

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DS1284/DS1286

Watchdog Timekeepers

GENERAL DESCRIPTION

The DS1284/DS1286 watchdog timekeepers are self-contained real-time clocks, alarms, watchdog timers, and interval timers in a 28-pin JEDEC DIP and encapsulated DIP package. The DS1286 contains an embedded lithium energy source and a quartz crystal, which eliminates the need for any external circuitry. The DS1284 requires an external quartz crystal and a V lithium battery. Data contained within 64 8-bit registers can be read or written in the same manner as byte-wide static RAM. Data is maintained in the watchdog timekeeper by intelligent control circuitry that detects the status of V memory when V

is out of tolerance. The lithium

energy source can maintain data and real time for over 10 years in the absence of V timekeeper information includes hundredths of seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap year. The DS1284/DS1286 operate in either 24-hour or 12hour format with an AM/PM indicator. The devices provide alarm windows and interval timing between

0.01 seconds and 99.99 seconds. The real-time alarm provides for preset times of up to one week.

source, which could be a

BAT

and write protects

. Watchdog

FEATURES

 Keeps Track of Hundredths of Seconds,

Seconds, Minutes, Hours, Days, Date of the Month, Months, and Years; Valid Leap Year Compensation Up to 2100

 Watchdog Timer Restarts an Out-of-Control

Processor

 Alarm Function Schedules Real-Time-Related

Activities

 Embedded Lithium Energy Cell Maintains

Time, Watchdog, User RAM, and Alarm Information

 Programmable Interrupts and Square-Wave

Outputs Maintain JEDEC Footprint

 All Registers are Individually Addressable via

the Address and Data Bus

 Accuracy is Better than ±1 Minute/Month at

+25°C (EDIP)

 Greater than 10 Years of Timekeeping in the

Absence of V

 50 Bytes of User NV RAM  Underwriters Laboratory (UL) Recognized  -40°C to +85°C Industrial Temperature Range

Option

Pin Configurations appear at end of data sheet.

ORDERING INFORMATION

PART TEMP RANGE VOLTAGE (V) PIN-PACKAGE TOP MARK*

DS1284

DS1284N DS1284Q DS1284Q+ DS1284Q/T&R DS1284Q+T&R DS1284QN DS1284QN+ DS1284QN/T&R DS1284QN+T&R

DS1286

DS1286I DS1286I+

+ Denotes a lead(Pb)-free/RoHS-compliant package.

* A “+” anywhere on the top mark indicates a lead-free package.

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0°C to +70°C 5.0

-40°C to +85°C 5.0 0°C to +70°C 5.0 0°C to +70°C 5.0 0°C to +70°C 5.0 0°C to +70°C 5.0

-40°C to +85°C 5.0

-40°C to +85°C 5.0 0°C to +70°C 5.0

-40°C to +85°C 5.0

28 DIP (600 mils) DS1284 28 DIP (600 mils) DS1284 N 28 PLCC DS1284Q 28 PLCC DS1284Q 28 PLCC/Tape and Reel DS1284Q 28 PLCC/Tape and Reel DS1284Q 28 PLCC DS1284QN 28 PLCC DS1284QN 28 PLCC/Tape and Reel DS1284QN 28 PLCC/Tape and Reel DS1284QN 28 EDIP (720 mils) DS1286 28 EDIP (720 mils) DS1286 IND 28 EDIP (720 mils) DS1286 IND

REV: 032406

DS1284/DS1286

OPERATION—READ REGISTERS

The DS1284/DS1286 execute a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) and OE (output enable) are active (low). The unique address specified by the six address inputs (A0–A5) defines which of the 64 registers is to be accessed. Valid data is available to the eight data output drivers within t

(access time) after the last address input signal is stable, provided that CE and

ACC

OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the latter occurring signal (CE or OE) and the limiting parameter is either t

for CE or t

for OE rather than address access.

OPERATION—WRITE REGISTERS

The DS1284/DS1286 are in the write mode whenever the WE and CE signals are in the active-low state after the address inputs are stable. The latter occurring falling edge of CE or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery state (t

) before another cycle can be initiated. Data must be valid on the data bus with sufficient data

setup (tDS) and data hold time (tDH) with respect to the earlier rising edge of CE or WE. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active), then WE will disable the outputs in t

from its falling edge.

ODW

DATA RETENTION

The watchdog timekeeper provides full functional capability when V maintained in the absence of V

without any additional support circuitry. The DS1284/DS1286

constantly monitor VCC. Should the supply voltage decay, the watchdog timekeeper automatically write protects itself, and all inputs to the registers become “don’t care.” Both INTA and INTB (INTB) are open-drain outputs. The two interrupts and the internal clock continue to run regardless of the level of VCC. However, it is important to ensure that the pullup resistors used with the interrupt pins are never pulled up to a value greater than V

+ 0.3V. As VCC falls below the battery voltage, a power-switching

circuit turns on the lithium energy source to maintain the clock and timer data functionality. Also ensure that during this time (battery-backup mode), the voltage present at INTA and INTB (INTB) never exceeds the battery voltage. If the active-high mode is selected for INTB (INTB), this pin only goes high in the presence of V

. During power-up, when V

circuit connects external V

exceeds V

for t

REC

and disconnects the V

rises above approximately 3.0V, the power-switching

energy source. Normal operation can resume after

BAT

is greater than V

. Data is

WATCHDOG TIMEKEEPER REGISTERS

The watchdog timekeeper has 64 8-bits-wide registers that contain all the timekeeping, alarm, watchdog, control, and data information. The clock, calendar, alarm, and watchdog registers are memory locations that contain external (user-accessible) and internal copies of the data. The external copies are independent of internal functions, except that they are updated periodically by the simultaneous transfer of the incremented internal copy (see Figure 1). The command register bits are affected by both internal and external functions. This register is discussed later. The 50 bytes of RAM registers can only be accessed from the external address and data bus. Registers 0, 1, 2, 4, 6, 8, 9, and A contain time-of-day and date information (see Figure 2). Time-of-day information is stored in binary-coded decimal (BCD). Registers 3, 5, and 7 contain the time-of-day alarm information. Time-of-day alarm information is stored in BCD. Register B is the command register and information in this register is binary. Registers C and D are the watchdog alarm registers and information stored in these two registers is in BCD. Registers E to 3F are user bytes and can be used to contain data at the user’s discretion.

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PIN DESCRIPTION

DIP EDIP PLCC

1 1 1

2, 3 — 2, 3 X1, X2

2, 3, 4,

21, 24,

4 N.C. No Connection

5–10 5–10 5–10 A5–A0 Address Inputs 11, 12, 13, 15,

16–19

11, 12, 13, 15,

16–19

11, 12, 13, 15,

16–19

14, 21 14 14, 21 GND Ground

20 20 20 22 22 22

23 23 23 SQW

24 — 24

25 — 25 V

26 26 26

27 27 27

NAME FUNCTION

INTA

Active-Low Interrupt Outp pullup resistor for proper operation. Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (C directly to the X1 and X2 pins. There is no need for external capacitors or resistors. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real Time Clocks.

DQ0, DQ1, DQ2, DQ3,

Data Input/Output

DQ4–DQ7

CE OE

Active-Low Chip-Enable Input Active-Low Output-Enable Input Square-Wave Output. Push-pull output. High impedance when V

is below VTP.

Active-Low RAM Clear. Used to clear (set to logic 1) all 50 bytes of user NV RAM, but does not affect the registers involved with time, alarm, and watchdog functions. To clear the RAM, RCLR must be forced to an input logic 0 (-0.3V to

RCLR

+0.8V) during battery-backup mode when V The RCLR function is designed to be used via human interface (shorting to ground or by switch) and not be driven with external buffers. This pin is internally pulled up and should be left floating when not in use. Input for Any Standard 3V Lithium Cell or Other Energy Source. Input voltage must be held between the minimum and maximum limits for proper operation. The supply should be connected directly to the V

BAT

in series with the battery to the V not necessary because reverse charging current-protection circuitry is provided internal to the device and has passed the requirements of Underwriters Laboratories for UL listing. This pin should be grounded but can be left floating. Active-Low (Active-High) Interrupt Output B. When the activehigh state is selected (IBH = 1), an open-drain pullup transistor connected to V

INTB

(INTB)

When the active-low state is selected (IBH = 0), an open-drain pulldown transistor connected to ground sinks current when the output is active. If active-high output operation is selected, a pulldown resistor is required for proper operation. When activelow output operation is selected, a pullup resistor is required for proper operation.

Active-Low Write-Enable Input

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DS1284/DS1286

ut A. This open-drain pin requires a

) of 6pF. The crystal is connected

is not applied.

pin. A diode must not be placed

BAT

pin. Furthermore, a diode is

BAT

sources current when the output is active.



CE OE W

DIP EDIP PLCC

28 28 28 VCC

Figure 1. Block Diagram

DS1284/DS1286

NAME FUNCTION

Primary Power-Supply Input. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and V

is below VTP, read and writes are inhibited.

However, the timekeeping function continues unaffected by the lower input voltage.

DS1286

only

0-A5

X1 X2

Oscillator

ddress Decode and Control



Internal Registers

External Registers,

clock, calendar,

time of day alarm

Command

User RAM

50 Bytes



40.96

Watchdog Alarm

Internal Counters

Data I/O Buffers

DQ0–DQ7

40.96

Update seconds through

years and check time of

day alarm

100Hz

External

Registers

PF delay

Internal RegistersInternal Counters

External

Registers

Hundredths of

Seconds

TD INT

WD INT

100Hz

Power Switch

IBH

BAT

GND

Swap

pins

DS1284/DS1286

DS1286 only



1024Hz

SQW

NTA

NTB

(INTB)

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DS1284/DS1286

HUNDREDTHS-OF-SECONDS GENERATOR

The hundredths-of-seconds generator circuit shown in the Block Diagram (Figure 1) is a state machine that divides the incoming frequency (4096Hz) by 41 for 24 cycles and 40 for 1 cycle. This produces a 100Hz output that is slightly off during the short term, and is exactly correct every 250ms. The divide ratio is given by:

Ratio = [41 x 24 + 40 x 1] / 25 = 40.96

Thus, the long-term average frequency output is exactly 100Hz.

Figure 2. Watchdog Timekeeper Registers

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DS1284/DS1286

TIME-OF-DAY REGISTERS

Registers 0, 1, 2, 4, 6, 8, 9, and A contain time-of-day data in BCD. Ten bits within these eight registers are not used and always read 0 regardless of how they are written. Bits 6 and 7 in the months register (9) are binary bits. When set to logic 0, EOSC (bit 7) enables the RTC oscillator. This bit is set to logic 1 as shipped from Dallas Semiconductor to prevent lithium energy consumption during storage and shipment. The user normally turns this bit on during device initialization. However, the oscillator can be turned on and off as necessary by setting this bit to the appropriate level. Bit 6 of this same byte controls the squarewave output (pin 23). When set to logic 0, the square-wave output pin outputs a 1024Hz square-wave signal. When set to logic 1, the square-wave output pin is in a high-impedance state. Bit 6 of the hours register is defined as the 12- or 24-hour select bit. When set to logic 1, the 12-hour format is selected. In the 12-hour format, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The time-of-day registers are updated every 0.01 seconds from the RTC, except when the TE bit (bit 7 of register B) is set low or the clock oscillator is not running. The preferred method of synchronizing data access to and from the watchdog timekeeper is to access the command register by doing a write cycle to address location 0B and setting the TE (transfer enable) bit to a logic 0. Doing so freezes the external time-of-day registers at the present recorded time, allowing access to occur without danger of simultaneous update. When the watch registers have been read or written, a second write cycle to location 0B, setting the TE bit to a logic 1, puts the time-of-day registers back to being updated every 0.01 second. No time is lost in the RTC because the internal copy of the time-of-day register buffers is continually incremented while the external memory registers are frozen.

An alternate method of reading and writing the time-of-day registers is to ignore synchronization. However, any single read may give erroneous data as the RTC may be in the process of updating the external memory registers as data is being read. The internal copies of seconds through years are incremented and time-of-day alarm is checked during the period that hundreds of seconds read 99 and are transferred to the external register when hundredths of seconds roll from 99 to 00. A way of making sure data is valid is to do multiple reads and compare. Writing the registers can also produce erroneous results for the same reasons. A way of making sure that the write cycle has caused proper update is to do read verifies and re-execute the write cycle if data is not correct. While the possibility of erroneous results from reads and write cycles has been stated, it is worth noting that the probability of an incorrect result is kept to a minimum due to the redundant structure of the watchdog timekeeper.

TIME-OF-DAY ALARM REGISTERS

Registers 3, 5, and 7 contain the time-of-day alarm registers. Bits 3, 4, 5, and 6 of register 7 always read 0 regardless of how they are written. Bit 7 of registers 3, 5, and 7 are mask bits (Figure 3). When all the mask bits are logic 0, a time-of-day alarm only occurs when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. An alarm is generated every day when bit 7 of register 7 is set to logic 1. Similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to logic 1. When bit 7 of registers 7, 5, and 3 is set to logic 1, an alarm occurs every minute when register 1 (seconds) rolls from 59 to 00.

Time-of-day alarm registers are written and read in the same format as the time-of-day registers. The time-of-day alarm flag and interrupt is always cleared when alarm registers are read or written.

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