DS1245Y/AB
1024k Nonvolatile SRAM
32-Pin Encapsulated Package
34-Pin PowerCap Module (PCM)
FEATURES
10 years minimum data r etent ion in the
absence of external power
Data is automatically pro tected during power
loss
Replaces 128k x 8 volatile stat ic RAM,
EEPROM or Flash memory
Unlimited write c ycles
Low-power CMOS
Read and write access t imes of 70 ns
Lithium energy sour ce is electrically
disconnected to ret ain freshness u nt il power is
applied for the first time
Full ±10% VCC operating range (DS1245Y)
Optional ±5% VCC operating range
(DS1245AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
JEDEC standard 32-pin DIP package
PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standard ized pinout for all nonvo lat ile
SRAM products
- Detachment featur e on PowerCap allows
easy removal using a regu lar screwdriver
PIN ASSIGNMENT
VCC
740-mil Extended
3
11
BAT
27
24
21
19
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
PIN DESCRIPTION
A0 - A16 - Address Inputs
DQ0 - DQ7 - Data In/Dat a Out
- Chip Enable
- Write Enable
- Output Enable
VCC - Power (+5V)
GND - Ground
NC - No Co nnect
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DS1245Y/AB
DESCRIPTION
The DS1245 1024k Nonvolatile SRAMs are1,048,576-bit, fully static, non volatile SRAMs o rganized as
131,072 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
control cir c uit ry wh ich c on stantly mon ito rs VCC for an o ut -of-toler a nc e c o ndit ion. W he n su c h a c o ndit io n
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to pr event dat a corru ption. DIP-package DS1245 devices can be used in place of existing 128k x
8 static RAMs directly confor ming to the popular bytewide 32-p in DIP standard. DS1245 de vices in th e
PowerCap Module package are direct ly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitr y is requ ired for micro pr ocessor interfacing.
READ MODE
The DS1245 execut es a read cycle whenever WE (Writ e Enable) is inactive (high) and CE (Chip Enable)
and OE (Out put Enable) are active (low). The unique address specified by the 17 address inputs (A0 A16) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available t o the eight
data output drivers within t
(Access Time) a fter the last add ress input signal is st able, providing t hat
ACC
and OE (Outp ut Enable) acces s t imes are a lso sat isfied . If OE and CE access times are not satisfied,
then data acces s must be measured fro m the lat er occurring signal (CE or OE) and the li miting parameter
is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1245 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later occurring falling edge of CE or WE will determine the st ar t of the write cycle.
The write cycle is terminated by the ear lier rising edge o f CE or
. All address inputs must be kept
valid throughout the write c ycle. WE must return to the high stat e for a minimum reco very time (tWR)
before anot her cycle can be initiat ed. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contentio n. Ho w ever , if the o ut put dr ivers ar e e nab led (CE and OE a ct ive) t hen
wil l disable the o utputs in t
from its falling edge.
ODW
DATA RETENTION MODE
The DS1245AB provides full functional c ap ab ilit y for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1245Y provides full functional capability for VCC greater than 4.5 volts and writeprotects by 4.25 volts. Data is maintained in the a bsence of VCC without a n y a dd ition al support circuitry.
The nonvolatile stat ic RAMs constantly monitor VCC. Should the supply vo ltage decay, the NV SRAMs
automatically write-protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximate ly 3.0 vo lts, a power switching c ircuit connects the lit hium
energy source to RAM to r etain data. During power-up , whe n VCC rises above approximately 3.0 volts,
the power sw itching c ircuit connect s external VCC to RAM and disconnects the lithium energy source.
Normal RAM operat ion can resu me after VCC exceeds 4.75 volts for the DS1245AB and 4.5 volts for the
DS1245Y.
FRESHNESS SEAL
Each DS1245 device is shipped from Maxim with its lit hium energy source disco nnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than 4.25 vo lts, the lit hiu m e nergy source
is enabled for batt ery back-up operation.
DS1245Y/AB
PACKAGES
The DS1245 devices are available in two packages: 32-pin DI P and 3 4-pin PowerCap Module (PCM).
The 3 2-p in DI P int egr at es a lit h iu m bat t er y, an S R AM memo r y and a no n vo lat ile c o ntr o l func t ion int o a
single package with a JEDEC-standard 600-mil DIP pino ut. The 34-pin PowerCap Module integrates
SRAM memo ry and nonvo lat ile cont ro l along w ith co nta cts fo r co nnection to the lithium battery in the
DS9034PC PowerCap. The PowerCap Module package design allows a DS1245 PCM device to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1245 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the
PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1245 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped
in separate containers. See t he DS90 34P C dat a sheet for further information.